From: Michael Walle <michael@walle.cc> To: Vladimir Oltean <olteanv@gmail.com> Cc: broonie@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, peng.ma@nxp.com Subject: Re: [PATCH 1/6] spi: spi-fsl-dspi: Don't access reserved fields in SPI_MCR Date: Mon, 09 Mar 2020 19:05:09 +0100 [thread overview] Message-ID: <c35b3c34123b43b26204a2cf360e7ec1@walle.cc> (raw) In-Reply-To: <20200309145624.10026-2-olteanv@gmail.com> Am 2020-03-09 15:56, schrieb Vladimir Oltean: > From: Vladimir Oltean <vladimir.oltean@nxp.com> > > The SPI_MCR_PCSIS macro assumes that the controller has a number of > chip > select signals equal to 6. That is not always the case, but actually is > described through the driver-specific " signals equal to 6. That is not > always the case, but actually is described through the driver-specific > "spi-num-chipselects" device tree binding. Repeated sentence? Was this your intention? -michael > LS1028A for example only has > 4 chip selects. > > Don't write to the upper bits of the PCSIS field, which are reserved in > the reference manual. > > Fixes: 349ad66c0ab0 ("spi:Add Freescale DSPI driver for Vybrid VF610 > platform") > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > drivers/spi/spi-fsl-dspi.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c > index 0683a3fbd48c..0ce26c1cbf62 100644 > --- a/drivers/spi/spi-fsl-dspi.c > +++ b/drivers/spi/spi-fsl-dspi.c > @@ -22,7 +22,7 @@ > > #define SPI_MCR 0x00 > #define SPI_MCR_MASTER BIT(31) > -#define SPI_MCR_PCSIS (0x3F << 16) > +#define SPI_MCR_PCSIS(x) ((x) << 16) > #define SPI_MCR_CLR_TXF BIT(11) > #define SPI_MCR_CLR_RXF BIT(10) > #define SPI_MCR_XSPI BIT(3) > @@ -1197,7 +1197,10 @@ static const struct regmap_config > dspi_xspi_regmap_config[] = { > > static void dspi_init(struct fsl_dspi *dspi) > { > - unsigned int mcr = SPI_MCR_PCSIS; > + unsigned int mcr; > + > + /* Set idle states for all chip select signals to high */ > + mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->num_chipselect - 1, 0)); > > if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) > mcr |= SPI_MCR_XSPI;
WARNING: multiple messages have this Message-ID (diff)
From: Michael Walle <michael-QKn5cuLxLXY@public.gmane.org> To: Vladimir Oltean <olteanv-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Cc: broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, eha-/iRVSOupHO4@public.gmane.org, angelo-BIYBQhTR83Y@public.gmane.org, andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, gustavo-L1vi/lXTdts+Va1GwOuvDg@public.gmane.org, weic-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, mhosny-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, peng.ma-3arQi8VN3Tc@public.gmane.org Subject: Re: [PATCH 1/6] spi: spi-fsl-dspi: Don't access reserved fields in SPI_MCR Date: Mon, 09 Mar 2020 19:05:09 +0100 [thread overview] Message-ID: <c35b3c34123b43b26204a2cf360e7ec1@walle.cc> (raw) In-Reply-To: <20200309145624.10026-2-olteanv-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Am 2020-03-09 15:56, schrieb Vladimir Oltean: > From: Vladimir Oltean <vladimir.oltean-3arQi8VN3Tc@public.gmane.org> > > The SPI_MCR_PCSIS macro assumes that the controller has a number of > chip > select signals equal to 6. That is not always the case, but actually is > described through the driver-specific " signals equal to 6. That is not > always the case, but actually is described through the driver-specific > "spi-num-chipselects" device tree binding. Repeated sentence? Was this your intention? -michael > LS1028A for example only has > 4 chip selects. > > Don't write to the upper bits of the PCSIS field, which are reserved in > the reference manual. > > Fixes: 349ad66c0ab0 ("spi:Add Freescale DSPI driver for Vybrid VF610 > platform") > Signed-off-by: Vladimir Oltean <vladimir.oltean-3arQi8VN3Tc@public.gmane.org> > --- > drivers/spi/spi-fsl-dspi.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c > index 0683a3fbd48c..0ce26c1cbf62 100644 > --- a/drivers/spi/spi-fsl-dspi.c > +++ b/drivers/spi/spi-fsl-dspi.c > @@ -22,7 +22,7 @@ > > #define SPI_MCR 0x00 > #define SPI_MCR_MASTER BIT(31) > -#define SPI_MCR_PCSIS (0x3F << 16) > +#define SPI_MCR_PCSIS(x) ((x) << 16) > #define SPI_MCR_CLR_TXF BIT(11) > #define SPI_MCR_CLR_RXF BIT(10) > #define SPI_MCR_XSPI BIT(3) > @@ -1197,7 +1197,10 @@ static const struct regmap_config > dspi_xspi_regmap_config[] = { > > static void dspi_init(struct fsl_dspi *dspi) > { > - unsigned int mcr = SPI_MCR_PCSIS; > + unsigned int mcr; > + > + /* Set idle states for all chip select signals to high */ > + mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->num_chipselect - 1, 0)); > > if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) > mcr |= SPI_MCR_XSPI;
next prev parent reply other threads:[~2020-03-09 18:05 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-09 14:56 [PATCH 0/6] NXP DSPI bugfixes and support for LS1028A Vladimir Oltean 2020-03-09 14:56 ` Vladimir Oltean 2020-03-09 14:56 ` [PATCH 1/6] spi: spi-fsl-dspi: Don't access reserved fields in SPI_MCR Vladimir Oltean 2020-03-09 18:05 ` Michael Walle [this message] 2020-03-09 18:05 ` Michael Walle 2020-03-09 18:09 ` Vladimir Oltean 2020-03-09 18:09 ` Vladimir Oltean 2020-03-09 14:56 ` [PATCH 2/6] spi: spi-fsl-dspi: Fix little endian access to PUSHR CMD and TXDATA Vladimir Oltean 2020-03-09 17:59 ` Michael Walle 2020-03-09 17:59 ` Michael Walle 2020-03-09 18:07 ` Vladimir Oltean 2020-03-09 18:07 ` Vladimir Oltean 2020-03-09 18:19 ` Michael Walle 2020-03-09 18:19 ` Michael Walle 2020-03-09 18:31 ` Vladimir Oltean 2020-03-09 18:31 ` Vladimir Oltean 2020-03-09 14:56 ` [PATCH 3/6] spi: spi-fsl-dspi: Fix oper_word_size of zero for DMA mode Vladimir Oltean 2020-03-09 14:56 ` Vladimir Oltean 2020-03-09 14:56 ` [PATCH 4/6] spi: spi-fsl-dspi: Add support for LS1028A Vladimir Oltean 2020-03-09 18:38 ` Michael Walle 2020-03-09 18:38 ` Michael Walle 2020-03-09 18:51 ` Vladimir Oltean 2020-03-09 18:51 ` Vladimir Oltean 2020-03-09 14:56 ` [PATCH 5/6] arm64: dts: ls1028a: Specify the DMA channels for the DSPI controllers Vladimir Oltean 2020-03-09 14:56 ` Vladimir Oltean 2020-03-09 19:06 ` Michael Walle 2020-03-09 19:06 ` Michael Walle 2020-03-09 19:59 ` Vladimir Oltean 2020-03-09 19:59 ` Vladimir Oltean 2020-03-09 20:17 ` Michael Walle 2020-03-09 14:56 ` [PATCH 6/6] arm64: dts: ls1028a-rdb: Add a spidev node for the mikroBUS Vladimir Oltean 2020-03-09 14:56 ` Vladimir Oltean 2020-03-09 18:35 ` Michael Walle 2020-03-09 18:35 ` Michael Walle 2020-03-09 18:50 ` Vladimir Oltean 2020-03-09 18:50 ` Vladimir Oltean 2020-03-09 18:58 ` Michael Walle 2020-03-09 18:58 ` Michael Walle 2020-03-09 18:03 ` [PATCH 0/6] NXP DSPI bugfixes and support for LS1028A Michael Walle 2020-03-09 18:03 ` Michael Walle 2020-03-09 18:14 ` Vladimir Oltean 2020-03-09 18:14 ` Vladimir Oltean 2020-03-09 18:31 ` Michael Walle 2020-03-09 18:48 ` Vladimir Oltean 2020-03-09 18:59 ` Michael Walle 2020-03-09 18:59 ` Michael Walle
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=c35b3c34123b43b26204a2cf360e7ec1@walle.cc \ --to=michael@walle.cc \ --cc=andrew.smirnov@gmail.com \ --cc=angelo@sysam.it \ --cc=broonie@kernel.org \ --cc=devicetree@vger.kernel.org \ --cc=eha@deif.com \ --cc=gustavo@embeddedor.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-spi@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=mhosny@nvidia.com \ --cc=olteanv@gmail.com \ --cc=peng.ma@nxp.com \ --cc=robh+dt@kernel.org \ --cc=shawnguo@kernel.org \ --cc=weic@nvidia.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.