* [cip-dev] [PATCH 4.4.y-cip 01/30] ARM: shmobile: Document RZ/G1H SoC DT binding
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 02/30] dt-bindings: reset: rcar-rst: Document r8a7742 reset module Biju Das
` (29 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 962 bytes --]
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 368d03531f39ffaa793a98b9a17c79d660b1cd1a upstream.
Document the RZ/G1H (r8a7742) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 26425a1e3bea..1f894d9a2d0f 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -13,6 +13,8 @@ SoCs:
compatible = "renesas,r8a73a4"
- R-Mobile A1 (R8A77400)
compatible = "renesas,r8a7740"
+ - RZ/G1H (R8A77420)
+ compatible = "renesas,r8a7742"
- RZ/G1M (R8A77430)
compatible = "renesas,r8a7743"
- RZ/G1N (R8A77440)
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5291): https://lists.cip-project.org/g/cip-dev/message/5291
Mute This Topic: https://lists.cip-project.org/mt/76477074/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 02/30] dt-bindings: reset: rcar-rst: Document r8a7742 reset module
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 01/30] ARM: shmobile: Document RZ/G1H SoC DT binding Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 03/30] soc: renesas: rcar-rst: Add support for RZ/G1H Biju Das
` (28 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1302 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 9e01d74ce0a154411c8991d6e34f4c470958eac3 upstream.
Document bindings for the RZ/G1H (R8A7742) reset module.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587678050-23468-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
index 270f54b5c6cd..e3ea9be09968 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
@@ -6,6 +6,7 @@ Required properties:
- compatible: Should be
- "renesas,<soctype>-rst" for R-Car Gen2 and RZ/G
Examples with soctypes are:
+ - "renesas,r8a7742-rst" (RZ/G1H)
- "renesas,r8a7743-rst" (RZ/G1M)
- "renesas,r8a7744-rst" (RZ/G1N)
- "renesas,r8a7745-rst" (RZ/G1E)
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5292): https://lists.cip-project.org/g/cip-dev/message/5292
Mute This Topic: https://lists.cip-project.org/mt/76477075/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 03/30] soc: renesas: rcar-rst: Add support for RZ/G1H
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 01/30] ARM: shmobile: Document RZ/G1H SoC DT binding Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 02/30] dt-bindings: reset: rcar-rst: Document r8a7742 reset module Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 04/30] ARM: shmobile: r8a7742: Add clock index macros for DT sources Biju Das
` (27 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1391 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 2f71832755a9422f5a62a13ea3e805df7b173837 upstream.
Add support for RZ/G1H (R8A7742) to the R-Car RST driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587678050-23468-6-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: Changed the text RZ/G to RZ/G1 ]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/soc/renesas/rcar-rst.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index 8eaf736b2b86..869fb10d6de5 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -31,7 +31,8 @@ static const struct rst_config rcar_rst_gen2 __initconst = {
};
static const struct of_device_id rcar_rst_matches[] __initconst = {
- /* RZ/G is handled like R-Car Gen2 */
+ /* RZ/G1 is handled like R-Car Gen2 */
+ { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5293): https://lists.cip-project.org/g/cip-dev/message/5293
Mute This Topic: https://lists.cip-project.org/mt/76477076/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 04/30] ARM: shmobile: r8a7742: Add clock index macros for DT sources
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (2 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 03/30] soc: renesas: rcar-rst: Add support for RZ/G1H Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 05/30] clk: shmobile: Document r8a7742 CPG clock support Biju Das
` (26 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 5400 bytes --]
Add macros usable by device tree sources to reference r8a7742 clocks by
index.
Unfortunately there is nothing that we can backport from mainline
for this, as the architecture of the clock driver has changed
quite dramatically over time.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
include/dt-bindings/clock/r8a7742-clock.h | 165 ++++++++++++++++++++++
1 file changed, 165 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a7742-clock.h
diff --git a/include/dt-bindings/clock/r8a7742-clock.h b/include/dt-bindings/clock/r8a7742-clock.h
new file mode 100644
index 000000000000..52a6d6bc4f2a
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7742-clock.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7742_H__
+#define __DT_BINDINGS_CLOCK_R8A7742_H__
+
+/* CPG */
+#define R8A7742_CLK_MAIN 0
+#define R8A7742_CLK_PLL0 1
+#define R8A7742_CLK_PLL1 2
+#define R8A7742_CLK_PLL3 3
+#define R8A7742_CLK_LB 4
+#define R8A7742_CLK_QSPI 5
+#define R8A7742_CLK_SDH 6
+#define R8A7742_CLK_SD0 7
+#define R8A7742_CLK_SD1 8
+#define R8A7742_CLK_Z 9
+#define R8A7742_CLK_Z2 10
+#define R8A7742_CLK_RCAN 11
+
+/* MSTP0 */
+#define R8A7742_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7742_CLK_VCP1 0
+#define R8A7742_CLK_VCP0 1
+#define R8A7742_CLK_VPC1 2
+#define R8A7742_CLK_VPC0 3
+#define R8A7742_CLK_TMU1 11
+#define R8A7742_CLK_3DG 12
+#define R8A7742_CLK_2DDMAC 15
+#define R8A7742_CLK_FDP1_2 17
+#define R8A7742_CLK_FDP1_1 18
+#define R8A7742_CLK_FDP1_0 19
+#define R8A7742_CLK_TMU3 21
+#define R8A7742_CLK_TMU2 22
+#define R8A7742_CLK_CMT0 24
+#define R8A7742_CLK_TMU0 25
+#define R8A7742_CLK_VSP1_DU1 27
+#define R8A7742_CLK_VSP1_DU0 28
+#define R8A7742_CLK_VSP1_R 30
+#define R8A7742_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7742_CLK_SCIFA2 2
+#define R8A7742_CLK_SCIFA1 3
+#define R8A7742_CLK_SCIFA0 4
+#define R8A7742_CLK_MSIOF2 5
+#define R8A7742_CLK_SCIFB0 6
+#define R8A7742_CLK_SCIFB1 7
+#define R8A7742_CLK_MSIOF1 8
+#define R8A7742_CLK_MSIOF3 15
+#define R8A7742_CLK_SCIFB2 16
+#define R8A7742_CLK_SYS_DMAC1 18
+#define R8A7742_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7742_CLK_IIC2 0
+#define R8A7742_CLK_TPU0 4
+#define R8A7742_CLK_MMCIF1 5
+#define R8A7742_CLK_SCIF2 10
+#define R8A7742_CLK_SDHI3 11
+#define R8A7742_CLK_SDHI2 12
+#define R8A7742_CLK_SDHI1 13
+#define R8A7742_CLK_SDHI0 14
+#define R8A7742_CLK_MMCIF0 15
+#define R8A7742_CLK_IIC0 18
+#define R8A7742_CLK_PCIEC 19
+#define R8A7742_CLK_IIC1 23
+#define R8A7742_CLK_SSUSB 28
+#define R8A7742_CLK_CMT1 29
+#define R8A7742_CLK_USBDMAC0 30
+#define R8A7742_CLK_USBDMAC1 31
+
+/* MSTP4 */
+#define R8A7742_CLK_RWDT 2
+#define R8A7742_CLK_IRQC 7
+#define R8A7742_CLK_INTC_SYS 8
+
+/* MSTP5 */
+#define R8A7742_CLK_AUDIO_DMAC1 1
+#define R8A7742_CLK_AUDIO_DMAC0 2
+#define R8A7742_CLK_THERMAL 22
+#define R8A7742_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7742_CLK_EHCI 3
+#define R8A7742_CLK_HSUSB 4
+#define R8A7742_CLK_HSCIF1 16
+#define R8A7742_CLK_HSCIF0 17
+#define R8A7742_CLK_SCIF1 20
+#define R8A7742_CLK_SCIF0 21
+#define R8A7742_CLK_DU2 22
+#define R8A7742_CLK_DU1 23
+#define R8A7742_CLK_DU0 24
+#define R8A7742_CLK_LVDS1 25
+#define R8A7742_CLK_LVDS0 26
+
+/* MSTP8 */
+#define R8A7742_CLK_R_GP2D 7
+#define R8A7742_CLK_VIN3 8
+#define R8A7742_CLK_VIN2 9
+#define R8A7742_CLK_VIN1 10
+#define R8A7742_CLK_VIN0 11
+#define R8A7742_CLK_ETHERAVB 12
+#define R8A7742_CLK_ETHER 13
+#define R8A7742_CLK_SATA1 14
+#define R8A7742_CLK_SATA0 15
+#define R8A7742_CLK_IMR_X2_1 20
+#define R8A7742_CLK_IMR_X2_0 21
+#define R8A7742_CLK_IMR_LSX2_1 22
+#define R8A7742_CLK_IMR_LSX2_0 23
+
+/* MSTP9 */
+#define R8A7742_CLK_GPIO5 7
+#define R8A7742_CLK_GPIO4 8
+#define R8A7742_CLK_GPIO3 9
+#define R8A7742_CLK_GPIO2 10
+#define R8A7742_CLK_GPIO1 11
+#define R8A7742_CLK_GPIO0 12
+#define R8A7742_CLK_RCAN1 15
+#define R8A7742_CLK_RCAN0 16
+#define R8A7742_CLK_QSPI_MOD 17
+#define R8A7742_CLK_IICDVFS 26
+#define R8A7742_CLK_I2C3 28
+#define R8A7742_CLK_I2C2 29
+#define R8A7742_CLK_I2C1 30
+#define R8A7742_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7742_CLK_SSI_ALL 5
+#define R8A7742_CLK_SSI9 6
+#define R8A7742_CLK_SSI8 7
+#define R8A7742_CLK_SSI7 8
+#define R8A7742_CLK_SSI6 9
+#define R8A7742_CLK_SSI5 10
+#define R8A7742_CLK_SSI4 11
+#define R8A7742_CLK_SSI3 12
+#define R8A7742_CLK_SSI2 13
+#define R8A7742_CLK_SSI1 14
+#define R8A7742_CLK_SSI0 15
+#define R8A7742_CLK_SCU_ALL 17
+#define R8A7742_CLK_SCU_DVC1 18
+#define R8A7742_CLK_SCU_DVC0 19
+#define R8A7742_CLK_SCU_CTU1_MIX1 20
+#define R8A7742_CLK_SCU_CTU0_MIX0 21
+#define R8A7742_CLK_SCU_SRC9 22
+#define R8A7742_CLK_SCU_SRC8 23
+#define R8A7742_CLK_SCU_SRC7 24
+#define R8A7742_CLK_SCU_SRC6 25
+#define R8A7742_CLK_SCU_SRC5 26
+#define R8A7742_CLK_SCU_SRC4 27
+#define R8A7742_CLK_SCU_SRC3 28
+#define R8A7742_CLK_SCU_SRC2 29
+#define R8A7742_CLK_SCU_SRC1 30
+#define R8A7742_CLK_SCU_SRC0 31
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7742_H__ */
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5294): https://lists.cip-project.org/g/cip-dev/message/5294
Mute This Topic: https://lists.cip-project.org/mt/76477077/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 05/30] clk: shmobile: Document r8a7742 CPG clock support
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (3 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 04/30] ARM: shmobile: r8a7742: Add clock index macros for DT sources Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 06/30] clk: shmobile: Document r8a7742 MSTP " Biju Das
` (25 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1048 bytes --]
Document r8a7742 CPG clock support.
The clock driver architecture has changed quite dramatically
over time, there is nothing we can backport from mainline
for this, hence the new patch.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 631cd38792af..198d1da3f7a6 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -8,6 +8,7 @@ CPG Module Stop (MSTP) Clocks.
Required Properties:
- compatible: Must be one of
+ - "renesas,r8a7742-cpg-clocks" for the r8a7742 CPG
- "renesas,r8a7743-cpg-clocks" for the r8a7743 CPG
- "renesas,r8a7744-cpg-clocks" for the r8a7744 CPG
- "renesas,r8a7745-cpg-clocks" for the r8a7745 CPG
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5295): https://lists.cip-project.org/g/cip-dev/message/5295
Mute This Topic: https://lists.cip-project.org/mt/76477078/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 06/30] clk: shmobile: Document r8a7742 MSTP clock support
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (4 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 05/30] clk: shmobile: Document r8a7742 CPG clock support Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 07/30] clk: shmobile: Document r8a7742 CPG DIV6 " Biju Das
` (24 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1276 bytes --]
Document r8a7742 MSTP clock support.
The clock driver architecture has changed quite dramatically
over time, there is nothing we can backport from mainline
for this, hence the new patch.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 1f64680fb108..3787cb252b44 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -13,6 +13,7 @@ Required Properties:
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
- "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
+ - "renesas,r8a7742-mstp-clocks" for R8A7742 (RZ/G1H) MSTP gate clocks
- "renesas,r8a7743-mstp-clocks" for R8A7743 (RZ/G1M) MSTP gate clocks
- "renesas,r8a7744-mstp-clocks" for R8A7744 (RZ/G1N) MSTP gate clocks
- "renesas,r8a7745-mstp-clocks" for R8A7745 (RZ/G1E) MSTP gate clocks
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5296): https://lists.cip-project.org/g/cip-dev/message/5296
Mute This Topic: https://lists.cip-project.org/mt/76477079/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 07/30] clk: shmobile: Document r8a7742 CPG DIV6 clock support
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (5 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 06/30] clk: shmobile: Document r8a7742 MSTP " Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 08/30] clk: shmobile: Compile clk-rcar-gen2.c when using the r8a7742 Biju Das
` (23 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1215 bytes --]
Document r8a7742 CPG DIV6 clock support.
The clock driver architecture has changed quite dramatically
over time, there is nothing we can backport from mainline
for this, hence the new patch.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../devicetree/bindings/clock/renesas,cpg-div6-clocks.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
index 7b05affc93f1..c60b174e3350 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -9,6 +9,7 @@ Required Properties:
- compatible: Must be one of the following
- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
+ - "renesas,r8a7742-div6-clock" for R8A7742 (RZ/G1H) DIV6 clocks
- "renesas,r8a7743-div6-clock" for R8A7743 (RZ/G1M) DIV6 clocks
- "renesas,r8a7744-div6-clock" for R8A7744 (RZ/G1N) DIV6 clocks
- "renesas,r8a7745-div6-clock" for R8A7745 (RZ/G1E) DIV6 clocks
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5297): https://lists.cip-project.org/g/cip-dev/message/5297
Mute This Topic: https://lists.cip-project.org/mt/76477080/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 08/30] clk: shmobile: Compile clk-rcar-gen2.c when using the r8a7742
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (6 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 07/30] clk: shmobile: Document r8a7742 CPG DIV6 " Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 09/30] ARM: shmobile: r8a7742: Basic SoC support Biju Das
` (22 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 913 bytes --]
This patch makes sure clk-rcar-gen2,c gets compiled when
CONFIG_ARCH_R8A7742 is selected, similarly to what done by
commit:
7bac4ad3e40f ("CIP: Build essential clock driver for Renesas
RZ/G1 platforms")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/shmobile/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 6badac598707..2f9fb407aa32 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o
obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o
+obj-$(CONFIG_ARCH_R8A7742) += clk-rcar-gen2.o
obj-$(CONFIG_ARCH_R8A7743) += clk-rcar-gen2.o
obj-$(CONFIG_ARCH_R8A7744) += clk-rcar-gen2.o
obj-$(CONFIG_ARCH_R8A7745) += clk-rcar-gen2.o
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5298): https://lists.cip-project.org/g/cip-dev/message/5298
Mute This Topic: https://lists.cip-project.org/mt/76477081/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 09/30] ARM: shmobile: r8a7742: Basic SoC support
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (7 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 08/30] clk: shmobile: Compile clk-rcar-gen2.c when using the r8a7742 Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 10/30] soc: renesas: Add Renesas R8A7742 config option Biju Das
` (21 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1876 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 135e7a156ae2c1a7a1f0c1d44bf2b3daece04bbf upstream.
Add minimal support for the RZ/G1H (R8A7742) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587678050-23468-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: removed compatible string renesas,r8a7742-cpg-mssr, added config option for rz/g1h]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/mach-shmobile/pm-rcar-gen2.c | 2 ++
arch/arm/mach-shmobile/setup-rcar-gen2.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index dd1c9e08f3ea..c0c52458d9c9 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -97,6 +97,8 @@ void __init rcar_gen2_pm_init(void)
syscier = 0x013111ef;
else if (of_machine_is_compatible("renesas,r8a7791"))
syscier = 0x00111003;
+ else if (of_machine_is_compatible("renesas,r8a7742"))
+ syscier = 0x013111ef;
else if (of_machine_is_compatible("renesas,r8a7743"))
syscier = 0x00101003;
else if (of_machine_is_compatible("renesas,r8a7744"))
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 50c57c8c4f40..bd9985459651 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -207,6 +207,7 @@ DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)")
MACHINE_END
static const char * const rz_g1_boards_compat_dt[] __initconst = {
+ "renesas,r8a7742",
"renesas,r8a7743",
"renesas,r8a7744",
"renesas,r8a7745",
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5299): https://lists.cip-project.org/g/cip-dev/message/5299
Mute This Topic: https://lists.cip-project.org/mt/76477082/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 10/30] soc: renesas: Add Renesas R8A7742 config option
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (8 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 09/30] ARM: shmobile: r8a7742: Basic SoC support Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 11/30] ARM: debug-ll: Add support for r8a7742 Biju Das
` (20 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1166 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit cdc8abe763c99a6c2b854d7096eaf1ea21017a42 upstream.
Add configuration option for the RZ/G1H (R8A77420) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588197415-13747-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: Moved config option from soc/renesas/Kconfig to here]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/mach-shmobile/Kconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 79b66a1ce96b..a51df53f0914 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -64,6 +64,11 @@ config ARCH_R8A7740
select ARCH_RMOBILE
select RENESAS_INTC_IRQPIN
+config ARCH_R8A7742
+ bool "RZ/G1H (R8A77420)"
+ select ARCH_RCAR_GEN2
+ select ARM_ERRATA_798181 if SMP
+
config ARCH_R8A7743
bool "RZ/G1M (R8A77430)"
select ARCH_RCAR_GEN2
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5300): https://lists.cip-project.org/g/cip-dev/message/5300
Mute This Topic: https://lists.cip-project.org/mt/76477083/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 11/30] ARM: debug-ll: Add support for r8a7742
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (9 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 10/30] soc: renesas: Add Renesas R8A7742 config option Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 12/30] ARM: shmobile: defconfig: Enable r8a7742 SoC Biju Das
` (19 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 2554 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 96866b1a1d32318b6bbc321a762bf79db1f4686e upstream.
Enable low-level debugging support for RZ/G1H (R8A7742). RZ/G1H uses
SCIFA2 for the debug console.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588197415-13747-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/Kconfig.debug | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index f647c067d930..7df076789a3a 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -846,6 +846,13 @@ choice
Say Y here if you want kernel low-level debugging support
via SCIF4 on Renesas RZ/G1E (R8A7745).
+ config DEBUG_RCAR_GEN2_SCIFA2
+ bool "Kernel low-level debugging messages via SCIFA2 on R8A7742"
+ depends on ARCH_R8A7742
+ help
+ Say Y here if you want kernel low-level debugging support
+ via SCIFA2 on Renesas RZ/G1H (R8A7742).
+
config DEBUG_RMOBILE_SCIFA0
bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
depends on ARCH_R8A73A4
@@ -1351,6 +1358,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF1
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4
+ default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIFA2
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
@@ -1448,6 +1456,7 @@ config DEBUG_UART_PHYS
default 0xe4007000 if DEBUG_HIP04_UART
default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0
default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1
+ default 0xe6c60000 if DEBUG_RCAR_GEN2_SCIFA2
default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4
default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2
default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
@@ -1487,6 +1496,7 @@ config DEBUG_UART_PHYS
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \
DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
+ DEBUG_RCAR_GEN2_SCIFA2 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5301): https://lists.cip-project.org/g/cip-dev/message/5301
Mute This Topic: https://lists.cip-project.org/mt/76477084/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 12/30] ARM: shmobile: defconfig: Enable r8a7742 SoC
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (10 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 11/30] ARM: debug-ll: Add support for r8a7742 Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 13/30] ARM: multi_v7_defconfig: " Biju Das
` (18 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1041 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 1a90c5ba48c43aeaeccebcd3e092888b670a4bab upstream.
Enable recently added r8a7742 (RZ/G1H) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588197415-13747-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/configs/shmobile_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 151fad5c0b8d..03040b696689 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -14,6 +14,7 @@ CONFIG_ARCH_EMEV2=y
CONFIG_ARCH_R7S72100=y
CONFIG_ARCH_R8A73A4=y
CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7742=y
CONFIG_ARCH_R8A7743=y
CONFIG_ARCH_R8A7744=y
CONFIG_ARCH_R8A7745=y
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5302): https://lists.cip-project.org/g/cip-dev/message/5302
Mute This Topic: https://lists.cip-project.org/mt/76477085/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 13/30] ARM: multi_v7_defconfig: Enable r8a7742 SoC
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (11 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 12/30] ARM: shmobile: defconfig: Enable r8a7742 SoC Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 14/30] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings Biju Das
` (17 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1041 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 44b6141ebe936808fc59b386e3e259bef6c9bba6 upstream.
Enable recently added r8a7742 (RZ/G1H) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588197415-13747-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index f969bb231cf6..74a69583b75b 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -80,6 +80,7 @@ CONFIG_ARCH_EMEV2=y
CONFIG_ARCH_R7S72100=y
CONFIG_ARCH_R8A73A4=y
CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7742=y
CONFIG_ARCH_R8A7743=y
CONFIG_ARCH_R8A7744=y
CONFIG_ARCH_R8A7745=y
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5303): https://lists.cip-project.org/g/cip-dev/message/5303
Mute This Topic: https://lists.cip-project.org/mt/76477086/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 14/30] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (12 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 13/30] ARM: multi_v7_defconfig: " Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 15/30] dt-bindings: serial: renesas,scif: " Biju Das
` (16 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1645 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 0280a04ed9dbdaaae552b79b7a704625bd8e27cf upstream.
RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFA ports,
so document the SoC specific bindings.
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Rob Herring <robh@kernel.org>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index d2db8565d413..c57622ef52eb 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -9,6 +9,7 @@ Required properties:
- "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
- "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
- "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
+ - "renesas,scifa-r8a7742" for R8A7742 (RZ/G1H) SCIFA compatible UART.
- "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
- "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
- "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART.
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5304): https://lists.cip-project.org/g/cip-dev/message/5304
Mute This Topic: https://lists.cip-project.org/mt/76477087/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 15/30] dt-bindings: serial: renesas,scif: Document r8a7742 bindings
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (13 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 14/30] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 16/30] dt-bindings: serial: renesas,scifb: " Biju Das
` (15 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1602 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 8908a822663f6958f56174120de383ff955874be upstream.
RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIF ports,
so document the SoC specific bindings.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index c57622ef52eb..14768b504d13 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -9,6 +9,7 @@ Required properties:
- "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
- "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
- "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
+ - "renesas,scif-r8a7742" for R8A7742 (RZ/G1H) SCIF compatible UART.
- "renesas,scifa-r8a7742" for R8A7742 (RZ/G1H) SCIFA compatible UART.
- "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
- "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5305): https://lists.cip-project.org/g/cip-dev/message/5305
Mute This Topic: https://lists.cip-project.org/mt/76477088/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 16/30] dt-bindings: serial: renesas,scifb: Document r8a7742 bindings
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (14 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 15/30] dt-bindings: serial: renesas,scif: " Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 17/30] dt-bindings: serial: renesas,hscif: " Biju Das
` (14 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1593 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 3cf1601ab00ce55820e6130611f536b326563a7e upstream.
RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFB ports,
so document the SoC specific bindings.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index 14768b504d13..dff8cb1a2980 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -11,6 +11,7 @@ Required properties:
- "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
- "renesas,scif-r8a7742" for R8A7742 (RZ/G1H) SCIF compatible UART.
- "renesas,scifa-r8a7742" for R8A7742 (RZ/G1H) SCIFA compatible UART.
+ - "renesas,scifb-r8a7742" for R8A7742 (RZ/G1H) SCIFB compatible UART.
- "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
- "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
- "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART.
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5306): https://lists.cip-project.org/g/cip-dev/message/5306
Mute This Topic: https://lists.cip-project.org/mt/76477089/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 17/30] dt-bindings: serial: renesas,hscif: Document r8a7742 bindings
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (15 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 16/30] dt-bindings: serial: renesas,scifb: " Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 18/30] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings Biju Das
` (13 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1588 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 65994c09bc66d7241be2f7d6eb3b43f894ba2db0 upstream.
RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible HSCIF ports,
so document the SoC specific bindings.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index dff8cb1a2980..05bb154d6243 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -12,6 +12,7 @@ Required properties:
- "renesas,scif-r8a7742" for R8A7742 (RZ/G1H) SCIF compatible UART.
- "renesas,scifa-r8a7742" for R8A7742 (RZ/G1H) SCIFA compatible UART.
- "renesas,scifb-r8a7742" for R8A7742 (RZ/G1H) SCIFB compatible UART.
+ - "renesas,hscif-r8a7742" for R8A7742 (RZ/G1H) HSCIF compatible UART.
- "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
- "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
- "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART.
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5307): https://lists.cip-project.org/g/cip-dev/message/5307
Mute This Topic: https://lists.cip-project.org/mt/76477090/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 18/30] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (16 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 17/30] dt-bindings: serial: renesas,hscif: " Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 19/30] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Biju Das
` (12 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1563 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 194f9b21ad64740eb9675703037fe42113cea65c upstream.
Add support for r8a7742 SoC. Renesas RZ/G1H (R8A7742) MMCIF is identical
to the R-Car Gen2 family.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1588794695-27852-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
[biju: removed interrupt related changes]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/mmc/renesas,mmcif.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
index ccbcd765a6ec..6aeb67f5131d 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
+++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
@@ -9,6 +9,7 @@ Required properties:
- compatible: should be "renesas,mmcif-<soctype>", "renesas,sh-mmcif" as a
fallback. Examples with <soctype> are:
- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
+ - "renesas,mmcif-r8a7742" for the MMCIF found in r8a7742 SoCs
- "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
- "renesas,mmcif-r8a7744" for the MMCIF found in r8a7744 SoCs
- "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5308): https://lists.cip-project.org/g/cip-dev/message/5308
Mute This Topic: https://lists.cip-project.org/mt/76477091/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 19/30] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (17 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 18/30] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 20/30] pinctrl: sh-pfc: r8a7790: Use PINMUX_SINGLE() instead of raw PINMUX_DATA() Biju Das
` (11 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1639 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit baf674bf717f8224f33e453e1df92a96c4d6ce48 upstream.
Document PFC support for the RZ/G1H (R8A7742) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588542414-14826-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index f2008d0e5fd2..90c9bf8beca2 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -13,6 +13,7 @@ Required Properties:
- "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+ - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller.
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5309): https://lists.cip-project.org/g/cip-dev/message/5309
Mute This Topic: https://lists.cip-project.org/mt/76477092/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 20/30] pinctrl: sh-pfc: r8a7790: Use PINMUX_SINGLE() instead of raw PINMUX_DATA()
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (18 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 19/30] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 21/30] pinctrl: sh-pfc: r8a7790: Add SCIF_CLK support Biju Das
` (10 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1595 bytes --]
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 01af9ecbd7bd7d688c54d73a7fa8f7e10ab29d8c upstream.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index d9924b0d53b7..1acad99d6466 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -806,15 +806,15 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
- PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
- PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
- PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
- PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
- PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
- PINMUX_DATA(AVS1_MARK, FN_AVS1),
- PINMUX_DATA(AVS2_MARK, FN_AVS2),
- PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
- PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
+ PINMUX_SINGLE(VI1_DATA7_VI1_B7),
+ PINMUX_SINGLE(USB0_PWEN),
+ PINMUX_SINGLE(USB0_OVC_VBUS),
+ PINMUX_SINGLE(USB2_PWEN),
+ PINMUX_SINGLE(USB2_OVC),
+ PINMUX_SINGLE(AVS1),
+ PINMUX_SINGLE(AVS2),
+ PINMUX_SINGLE(DU_DOTCLKIN0),
+ PINMUX_SINGLE(DU_DOTCLKIN2),
PINMUX_IPSR_DATA(IP0_2_0, D0),
PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5310): https://lists.cip-project.org/g/cip-dev/message/5310
Mute This Topic: https://lists.cip-project.org/mt/76477098/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 21/30] pinctrl: sh-pfc: r8a7790: Add SCIF_CLK support
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (19 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 20/30] pinctrl: sh-pfc: r8a7790: Use PINMUX_SINGLE() instead of raw PINMUX_DATA() Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 22/30] pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to avb_mii group Biju Das
` (9 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 2403 bytes --]
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 53ec9ccd1c62b644d81674e013b1800dd88ec92b upstream.
Add pins, groups, and a function for SCIF_CLK, which is the external
clock source for the Baud Rate Generator for External Clock (BRG) on
(H)SCIF.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 1acad99d6466..0602ae4ec039 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -3236,6 +3236,21 @@ static const unsigned int scifb2_data_c_pins[] = {
static const unsigned int scifb2_data_c_mux[] = {
SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
};
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(4, 26),
+};
+static const unsigned int scif_clk_mux[] = {
+ SCIF_CLK_MARK,
+};
+static const unsigned int scif_clk_b_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int scif_clk_b_mux[] = {
+ SCIF_CLK_B_MARK,
+};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
@@ -4139,6 +4154,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb2_clk_b),
SH_PFC_PIN_GROUP(scifb2_ctrl_b),
SH_PFC_PIN_GROUP(scifb2_data_c),
+ SH_PFC_PIN_GROUP(scif_clk),
+ SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -4555,6 +4572,11 @@ static const char * const scifb2_groups[] = {
"scifb2_data_c",
};
+static const char * const scif_clk_groups[] = {
+ "scif_clk",
+ "scif_clk_b",
+};
+
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
@@ -4729,6 +4751,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scifb0),
SH_PFC_FUNCTION(scifb1),
SH_PFC_FUNCTION(scifb2),
+ SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5311): https://lists.cip-project.org/g/cip-dev/message/5311
Mute This Topic: https://lists.cip-project.org/mt/76477099/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 22/30] pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to avb_mii group
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (20 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 21/30] pinctrl: sh-pfc: r8a7790: Add SCIF_CLK support Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 23/30] pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support Biju Das
` (8 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1870 bytes --]
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 66e9fe1ec73929a9f7326856699d262bab8e9fb0 upstream.
The pin controller drivers for all R-Car Gen2 SoCs have entries for the
EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2.
Add the missing pin to restore consistency.
Note that technically TX_ER is an optional signal in the MII bus, and
thus could have its own group, but this is currently not supported by
any R-Car Gen2 pin controller driver.
Fixes: 19ef697d1eb7be06 ("sh-pfc: r8a7790: add EtherAVB pin groups")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 0602ae4ec039..a790e913e6bb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -1848,8 +1848,8 @@ static const unsigned int avb_mii_pins[] = {
RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
- RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
- RCAR_GP_PIN(3, 12),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
};
static const unsigned int avb_mii_mux[] = {
AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
@@ -1859,8 +1859,8 @@ static const unsigned int avb_mii_mux[] = {
AVB_RXD3_MARK,
AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
- AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
- AVB_COL_MARK,
+ AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
+ AVB_TX_CLK_MARK, AVB_COL_MARK,
};
static const unsigned int avb_gmii_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5312): https://lists.cip-project.org/g/cip-dev/message/5312
Mute This Topic: https://lists.cip-project.org/mt/76477100/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 23/30] pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (21 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 22/30] pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to avb_mii group Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 24/30] ARM: dts: r8a7742: Initial SoC device tree Biju Das
` (7 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 27723 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 4ecc7ff82ecfdf44997ed2a1016945fc8f6fca3e upstream.
Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790),
however it doesn't have several automotive specific peripherals. Add
automotive-specific pin groups/functions along with common pin
groups/functions for supporting both r8a7790 and r8a7742 SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588542414-14826-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: removed voltage switching, tdsel related changes]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pinctrl/sh-pfc/Kconfig | 5 +
drivers/pinctrl/sh-pfc/Makefile | 1 +
drivers/pinctrl/sh-pfc/core.c | 6 +
drivers/pinctrl/sh-pfc/core.h | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 743 ++++++++++++++-------------
5 files changed, 404 insertions(+), 352 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index eef770b6acc6..f4a2a9f708a4 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -35,6 +35,11 @@ config PINCTRL_PFC_R8A7740
depends on ARCH_R8A7740
select PINCTRL_SH_PFC
+config PINCTRL_PFC_R8A7742
+ def_bool y
+ depends on ARCH_R8A7742
+ select PINCTRL_SH_PFC
+
config PINCTRL_PFC_R8A7743
def_bool y
depends on ARCH_R8A7743
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 5310c07daaa2..39180441e538 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7744) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 6827a398ed0f..0fd6833b8259 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -453,6 +453,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a7740_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7742
+ {
+ .compatible = "renesas,pfc-r8a7742",
+ .data = &r8a7742_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7743
{
.compatible = "renesas,pfc-r8a7743",
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 5675ecf3bc94..d67d2fb8888a 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -69,6 +69,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
extern const struct sh_pfc_soc_info emev2_pinmux_info;
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7742_pinmux_info;
extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index a790e913e6bb..00b64c5ec866 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -3957,297 +3957,304 @@ static const unsigned int vin3_clk_mux[] = {
VI3_CLK_MARK,
};
-static const struct sh_pfc_pin_group pinmux_groups[] = {
- SH_PFC_PIN_GROUP(audio_clk_a),
- SH_PFC_PIN_GROUP(audio_clk_b),
- SH_PFC_PIN_GROUP(audio_clk_c),
- SH_PFC_PIN_GROUP(audio_clkout),
- SH_PFC_PIN_GROUP(audio_clkout_b),
- SH_PFC_PIN_GROUP(audio_clkout_c),
- SH_PFC_PIN_GROUP(audio_clkout_d),
- SH_PFC_PIN_GROUP(avb_link),
- SH_PFC_PIN_GROUP(avb_magic),
- SH_PFC_PIN_GROUP(avb_phy_int),
- SH_PFC_PIN_GROUP(avb_mdio),
- SH_PFC_PIN_GROUP(avb_mii),
- SH_PFC_PIN_GROUP(avb_gmii),
- SH_PFC_PIN_GROUP(du_rgb666),
- SH_PFC_PIN_GROUP(du_rgb888),
- SH_PFC_PIN_GROUP(du_clk_out_0),
- SH_PFC_PIN_GROUP(du_clk_out_1),
- SH_PFC_PIN_GROUP(du_sync_0),
- SH_PFC_PIN_GROUP(du_sync_1),
- SH_PFC_PIN_GROUP(du_cde),
- SH_PFC_PIN_GROUP(du0_clk_in),
- SH_PFC_PIN_GROUP(du1_clk_in),
- SH_PFC_PIN_GROUP(du2_clk_in),
- SH_PFC_PIN_GROUP(eth_link),
- SH_PFC_PIN_GROUP(eth_magic),
- SH_PFC_PIN_GROUP(eth_mdio),
- SH_PFC_PIN_GROUP(eth_rmii),
- SH_PFC_PIN_GROUP(hscif0_data),
- SH_PFC_PIN_GROUP(hscif0_clk),
- SH_PFC_PIN_GROUP(hscif0_ctrl),
- SH_PFC_PIN_GROUP(hscif0_data_b),
- SH_PFC_PIN_GROUP(hscif0_ctrl_b),
- SH_PFC_PIN_GROUP(hscif0_data_c),
- SH_PFC_PIN_GROUP(hscif0_ctrl_c),
- SH_PFC_PIN_GROUP(hscif0_data_d),
- SH_PFC_PIN_GROUP(hscif0_ctrl_d),
- SH_PFC_PIN_GROUP(hscif0_data_e),
- SH_PFC_PIN_GROUP(hscif0_ctrl_e),
- SH_PFC_PIN_GROUP(hscif0_data_f),
- SH_PFC_PIN_GROUP(hscif0_ctrl_f),
- SH_PFC_PIN_GROUP(hscif1_data),
- SH_PFC_PIN_GROUP(hscif1_clk),
- SH_PFC_PIN_GROUP(hscif1_ctrl),
- SH_PFC_PIN_GROUP(hscif1_data_b),
- SH_PFC_PIN_GROUP(hscif1_clk_b),
- SH_PFC_PIN_GROUP(hscif1_ctrl_b),
- SH_PFC_PIN_GROUP(i2c0),
- SH_PFC_PIN_GROUP(i2c1),
- SH_PFC_PIN_GROUP(i2c1_b),
- SH_PFC_PIN_GROUP(i2c1_c),
- SH_PFC_PIN_GROUP(i2c2),
- SH_PFC_PIN_GROUP(i2c2_b),
- SH_PFC_PIN_GROUP(i2c2_c),
- SH_PFC_PIN_GROUP(i2c2_d),
- SH_PFC_PIN_GROUP(i2c2_e),
- SH_PFC_PIN_GROUP(i2c3),
- SH_PFC_PIN_GROUP(iic0),
- SH_PFC_PIN_GROUP(iic1),
- SH_PFC_PIN_GROUP(iic1_b),
- SH_PFC_PIN_GROUP(iic1_c),
- SH_PFC_PIN_GROUP(iic2),
- SH_PFC_PIN_GROUP(iic2_b),
- SH_PFC_PIN_GROUP(iic2_c),
- SH_PFC_PIN_GROUP(iic2_d),
- SH_PFC_PIN_GROUP(iic2_e),
- SH_PFC_PIN_GROUP(iic3),
- SH_PFC_PIN_GROUP(intc_irq0),
- SH_PFC_PIN_GROUP(intc_irq1),
- SH_PFC_PIN_GROUP(intc_irq2),
- SH_PFC_PIN_GROUP(intc_irq3),
- SH_PFC_PIN_GROUP(mlb_3pin),
- SH_PFC_PIN_GROUP(mmc0_data1),
- SH_PFC_PIN_GROUP(mmc0_data4),
- SH_PFC_PIN_GROUP(mmc0_data8),
- SH_PFC_PIN_GROUP(mmc0_ctrl),
- SH_PFC_PIN_GROUP(mmc1_data1),
- SH_PFC_PIN_GROUP(mmc1_data4),
- SH_PFC_PIN_GROUP(mmc1_data8),
- SH_PFC_PIN_GROUP(mmc1_ctrl),
- SH_PFC_PIN_GROUP(msiof0_clk),
- SH_PFC_PIN_GROUP(msiof0_sync),
- SH_PFC_PIN_GROUP(msiof0_ss1),
- SH_PFC_PIN_GROUP(msiof0_ss2),
- SH_PFC_PIN_GROUP(msiof0_rx),
- SH_PFC_PIN_GROUP(msiof0_tx),
- SH_PFC_PIN_GROUP(msiof0_clk_b),
- SH_PFC_PIN_GROUP(msiof0_ss1_b),
- SH_PFC_PIN_GROUP(msiof0_ss2_b),
- SH_PFC_PIN_GROUP(msiof0_rx_b),
- SH_PFC_PIN_GROUP(msiof0_tx_b),
- SH_PFC_PIN_GROUP(msiof1_clk),
- SH_PFC_PIN_GROUP(msiof1_sync),
- SH_PFC_PIN_GROUP(msiof1_ss1),
- SH_PFC_PIN_GROUP(msiof1_ss2),
- SH_PFC_PIN_GROUP(msiof1_rx),
- SH_PFC_PIN_GROUP(msiof1_tx),
- SH_PFC_PIN_GROUP(msiof1_clk_b),
- SH_PFC_PIN_GROUP(msiof1_ss1_b),
- SH_PFC_PIN_GROUP(msiof1_ss2_b),
- SH_PFC_PIN_GROUP(msiof1_rx_b),
- SH_PFC_PIN_GROUP(msiof1_tx_b),
- SH_PFC_PIN_GROUP(msiof2_clk),
- SH_PFC_PIN_GROUP(msiof2_sync),
- SH_PFC_PIN_GROUP(msiof2_ss1),
- SH_PFC_PIN_GROUP(msiof2_ss2),
- SH_PFC_PIN_GROUP(msiof2_rx),
- SH_PFC_PIN_GROUP(msiof2_tx),
- SH_PFC_PIN_GROUP(msiof3_clk),
- SH_PFC_PIN_GROUP(msiof3_sync),
- SH_PFC_PIN_GROUP(msiof3_ss1),
- SH_PFC_PIN_GROUP(msiof3_ss2),
- SH_PFC_PIN_GROUP(msiof3_rx),
- SH_PFC_PIN_GROUP(msiof3_tx),
- SH_PFC_PIN_GROUP(msiof3_clk_b),
- SH_PFC_PIN_GROUP(msiof3_sync_b),
- SH_PFC_PIN_GROUP(msiof3_rx_b),
- SH_PFC_PIN_GROUP(msiof3_tx_b),
- SH_PFC_PIN_GROUP(pwm0),
- SH_PFC_PIN_GROUP(pwm0_b),
- SH_PFC_PIN_GROUP(pwm1),
- SH_PFC_PIN_GROUP(pwm1_b),
- SH_PFC_PIN_GROUP(pwm2),
- SH_PFC_PIN_GROUP(pwm3),
- SH_PFC_PIN_GROUP(pwm4),
- SH_PFC_PIN_GROUP(pwm5),
- SH_PFC_PIN_GROUP(pwm6),
- SH_PFC_PIN_GROUP(qspi_ctrl),
- SH_PFC_PIN_GROUP(qspi_data2),
- SH_PFC_PIN_GROUP(qspi_data4),
- SH_PFC_PIN_GROUP(scif0_data),
- SH_PFC_PIN_GROUP(scif0_clk),
- SH_PFC_PIN_GROUP(scif0_ctrl),
- SH_PFC_PIN_GROUP(scif0_data_b),
- SH_PFC_PIN_GROUP(scif1_data),
- SH_PFC_PIN_GROUP(scif1_clk),
- SH_PFC_PIN_GROUP(scif1_ctrl),
- SH_PFC_PIN_GROUP(scif1_data_b),
- SH_PFC_PIN_GROUP(scif1_data_c),
- SH_PFC_PIN_GROUP(scif1_data_d),
- SH_PFC_PIN_GROUP(scif1_clk_d),
- SH_PFC_PIN_GROUP(scif1_data_e),
- SH_PFC_PIN_GROUP(scif1_clk_e),
- SH_PFC_PIN_GROUP(scif2_data),
- SH_PFC_PIN_GROUP(scif2_clk),
- SH_PFC_PIN_GROUP(scif2_data_b),
- SH_PFC_PIN_GROUP(scifa0_data),
- SH_PFC_PIN_GROUP(scifa0_clk),
- SH_PFC_PIN_GROUP(scifa0_ctrl),
- SH_PFC_PIN_GROUP(scifa0_data_b),
- SH_PFC_PIN_GROUP(scifa0_clk_b),
- SH_PFC_PIN_GROUP(scifa0_ctrl_b),
- SH_PFC_PIN_GROUP(scifa1_data),
- SH_PFC_PIN_GROUP(scifa1_clk),
- SH_PFC_PIN_GROUP(scifa1_ctrl),
- SH_PFC_PIN_GROUP(scifa1_data_b),
- SH_PFC_PIN_GROUP(scifa1_clk_b),
- SH_PFC_PIN_GROUP(scifa1_ctrl_b),
- SH_PFC_PIN_GROUP(scifa1_data_c),
- SH_PFC_PIN_GROUP(scifa1_clk_c),
- SH_PFC_PIN_GROUP(scifa1_ctrl_c),
- SH_PFC_PIN_GROUP(scifa1_data_d),
- SH_PFC_PIN_GROUP(scifa1_clk_d),
- SH_PFC_PIN_GROUP(scifa1_ctrl_d),
- SH_PFC_PIN_GROUP(scifa2_data),
- SH_PFC_PIN_GROUP(scifa2_clk),
- SH_PFC_PIN_GROUP(scifa2_ctrl),
- SH_PFC_PIN_GROUP(scifa2_data_b),
- SH_PFC_PIN_GROUP(scifa2_data_c),
- SH_PFC_PIN_GROUP(scifa2_clk_c),
- SH_PFC_PIN_GROUP(scifb0_data),
- SH_PFC_PIN_GROUP(scifb0_clk),
- SH_PFC_PIN_GROUP(scifb0_ctrl),
- SH_PFC_PIN_GROUP(scifb0_data_b),
- SH_PFC_PIN_GROUP(scifb0_clk_b),
- SH_PFC_PIN_GROUP(scifb0_ctrl_b),
- SH_PFC_PIN_GROUP(scifb0_data_c),
- SH_PFC_PIN_GROUP(scifb1_data),
- SH_PFC_PIN_GROUP(scifb1_clk),
- SH_PFC_PIN_GROUP(scifb1_ctrl),
- SH_PFC_PIN_GROUP(scifb1_data_b),
- SH_PFC_PIN_GROUP(scifb1_clk_b),
- SH_PFC_PIN_GROUP(scifb1_ctrl_b),
- SH_PFC_PIN_GROUP(scifb1_data_c),
- SH_PFC_PIN_GROUP(scifb1_data_d),
- SH_PFC_PIN_GROUP(scifb1_data_e),
- SH_PFC_PIN_GROUP(scifb1_clk_e),
- SH_PFC_PIN_GROUP(scifb1_data_f),
- SH_PFC_PIN_GROUP(scifb1_data_g),
- SH_PFC_PIN_GROUP(scifb1_clk_g),
- SH_PFC_PIN_GROUP(scifb2_data),
- SH_PFC_PIN_GROUP(scifb2_clk),
- SH_PFC_PIN_GROUP(scifb2_ctrl),
- SH_PFC_PIN_GROUP(scifb2_data_b),
- SH_PFC_PIN_GROUP(scifb2_clk_b),
- SH_PFC_PIN_GROUP(scifb2_ctrl_b),
- SH_PFC_PIN_GROUP(scifb2_data_c),
- SH_PFC_PIN_GROUP(scif_clk),
- SH_PFC_PIN_GROUP(scif_clk_b),
- SH_PFC_PIN_GROUP(sdhi0_data1),
- SH_PFC_PIN_GROUP(sdhi0_data4),
- SH_PFC_PIN_GROUP(sdhi0_ctrl),
- SH_PFC_PIN_GROUP(sdhi0_cd),
- SH_PFC_PIN_GROUP(sdhi0_wp),
- SH_PFC_PIN_GROUP(sdhi1_data1),
- SH_PFC_PIN_GROUP(sdhi1_data4),
- SH_PFC_PIN_GROUP(sdhi1_ctrl),
- SH_PFC_PIN_GROUP(sdhi1_cd),
- SH_PFC_PIN_GROUP(sdhi1_wp),
- SH_PFC_PIN_GROUP(sdhi2_data1),
- SH_PFC_PIN_GROUP(sdhi2_data4),
- SH_PFC_PIN_GROUP(sdhi2_ctrl),
- SH_PFC_PIN_GROUP(sdhi2_cd),
- SH_PFC_PIN_GROUP(sdhi2_wp),
- SH_PFC_PIN_GROUP(sdhi3_data1),
- SH_PFC_PIN_GROUP(sdhi3_data4),
- SH_PFC_PIN_GROUP(sdhi3_ctrl),
- SH_PFC_PIN_GROUP(sdhi3_cd),
- SH_PFC_PIN_GROUP(sdhi3_wp),
- SH_PFC_PIN_GROUP(ssi0_data),
- SH_PFC_PIN_GROUP(ssi0129_ctrl),
- SH_PFC_PIN_GROUP(ssi1_data),
- SH_PFC_PIN_GROUP(ssi1_ctrl),
- SH_PFC_PIN_GROUP(ssi2_data),
- SH_PFC_PIN_GROUP(ssi2_ctrl),
- SH_PFC_PIN_GROUP(ssi3_data),
- SH_PFC_PIN_GROUP(ssi34_ctrl),
- SH_PFC_PIN_GROUP(ssi4_data),
- SH_PFC_PIN_GROUP(ssi4_ctrl),
- SH_PFC_PIN_GROUP(ssi5),
- SH_PFC_PIN_GROUP(ssi5_b),
- SH_PFC_PIN_GROUP(ssi5_c),
- SH_PFC_PIN_GROUP(ssi6),
- SH_PFC_PIN_GROUP(ssi6_b),
- SH_PFC_PIN_GROUP(ssi7_data),
- SH_PFC_PIN_GROUP(ssi7_b_data),
- SH_PFC_PIN_GROUP(ssi7_c_data),
- SH_PFC_PIN_GROUP(ssi78_ctrl),
- SH_PFC_PIN_GROUP(ssi78_b_ctrl),
- SH_PFC_PIN_GROUP(ssi78_c_ctrl),
- SH_PFC_PIN_GROUP(ssi8_data),
- SH_PFC_PIN_GROUP(ssi8_b_data),
- SH_PFC_PIN_GROUP(ssi8_c_data),
- SH_PFC_PIN_GROUP(ssi9_data),
- SH_PFC_PIN_GROUP(ssi9_ctrl),
- SH_PFC_PIN_GROUP(tpu0_to0),
- SH_PFC_PIN_GROUP(tpu0_to1),
- SH_PFC_PIN_GROUP(tpu0_to2),
- SH_PFC_PIN_GROUP(tpu0_to3),
- SH_PFC_PIN_GROUP(usb0),
- SH_PFC_PIN_GROUP(usb0_ovc_vbus),
- SH_PFC_PIN_GROUP(usb1),
- SH_PFC_PIN_GROUP(usb2),
- VIN_DATA_PIN_GROUP(vin0_data, 24),
- VIN_DATA_PIN_GROUP(vin0_data, 20),
- SH_PFC_PIN_GROUP(vin0_data18),
- VIN_DATA_PIN_GROUP(vin0_data, 16),
- VIN_DATA_PIN_GROUP(vin0_data, 12),
- VIN_DATA_PIN_GROUP(vin0_data, 10),
- VIN_DATA_PIN_GROUP(vin0_data, 8),
- VIN_DATA_PIN_GROUP(vin0_data, 4),
- SH_PFC_PIN_GROUP(vin0_sync),
- SH_PFC_PIN_GROUP(vin0_field),
- SH_PFC_PIN_GROUP(vin0_clkenb),
- SH_PFC_PIN_GROUP(vin0_clk),
- VIN_DATA_PIN_GROUP(vin1_data, 24),
- VIN_DATA_PIN_GROUP(vin1_data, 20),
- SH_PFC_PIN_GROUP(vin1_data18),
- VIN_DATA_PIN_GROUP(vin1_data, 16),
- VIN_DATA_PIN_GROUP(vin1_data, 12),
- VIN_DATA_PIN_GROUP(vin1_data, 10),
- VIN_DATA_PIN_GROUP(vin1_data, 8),
- VIN_DATA_PIN_GROUP(vin1_data, 4),
- SH_PFC_PIN_GROUP(vin1_sync),
- SH_PFC_PIN_GROUP(vin1_field),
- SH_PFC_PIN_GROUP(vin1_clkenb),
- SH_PFC_PIN_GROUP(vin1_clk),
- VIN_DATA_PIN_GROUP(vin2_data, 24),
- SH_PFC_PIN_GROUP(vin2_data18),
- VIN_DATA_PIN_GROUP(vin2_data, 16),
- VIN_DATA_PIN_GROUP(vin2_data, 8),
- VIN_DATA_PIN_GROUP(vin2_data, 4),
- SH_PFC_PIN_GROUP(vin2_sync),
- SH_PFC_PIN_GROUP(vin2_field),
- SH_PFC_PIN_GROUP(vin2_clkenb),
- SH_PFC_PIN_GROUP(vin2_clk),
- SH_PFC_PIN_GROUP(vin3_data8),
- SH_PFC_PIN_GROUP(vin3_sync),
- SH_PFC_PIN_GROUP(vin3_field),
- SH_PFC_PIN_GROUP(vin3_clkenb),
- SH_PFC_PIN_GROUP(vin3_clk),
+static const struct {
+ struct sh_pfc_pin_group common[289];
+ struct sh_pfc_pin_group automotive[1];
+} pinmux_groups = {
+ .common = {
+ SH_PFC_PIN_GROUP(audio_clk_a),
+ SH_PFC_PIN_GROUP(audio_clk_b),
+ SH_PFC_PIN_GROUP(audio_clk_c),
+ SH_PFC_PIN_GROUP(audio_clkout),
+ SH_PFC_PIN_GROUP(audio_clkout_b),
+ SH_PFC_PIN_GROUP(audio_clkout_c),
+ SH_PFC_PIN_GROUP(audio_clkout_d),
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_mii),
+ SH_PFC_PIN_GROUP(avb_gmii),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_out_0),
+ SH_PFC_PIN_GROUP(du_clk_out_1),
+ SH_PFC_PIN_GROUP(du_sync_0),
+ SH_PFC_PIN_GROUP(du_sync_1),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du0_clk_in),
+ SH_PFC_PIN_GROUP(du1_clk_in),
+ SH_PFC_PIN_GROUP(du2_clk_in),
+ SH_PFC_PIN_GROUP(eth_link),
+ SH_PFC_PIN_GROUP(eth_magic),
+ SH_PFC_PIN_GROUP(eth_mdio),
+ SH_PFC_PIN_GROUP(eth_rmii),
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif0_data_b),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif0_data_c),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_c),
+ SH_PFC_PIN_GROUP(hscif0_data_d),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_d),
+ SH_PFC_PIN_GROUP(hscif0_data_e),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_e),
+ SH_PFC_PIN_GROUP(hscif0_data_f),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_f),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data_b),
+ SH_PFC_PIN_GROUP(hscif1_clk_b),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c1_b),
+ SH_PFC_PIN_GROUP(i2c1_c),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c2_c),
+ SH_PFC_PIN_GROUP(i2c2_d),
+ SH_PFC_PIN_GROUP(i2c2_e),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(iic0),
+ SH_PFC_PIN_GROUP(iic1),
+ SH_PFC_PIN_GROUP(iic1_b),
+ SH_PFC_PIN_GROUP(iic1_c),
+ SH_PFC_PIN_GROUP(iic2),
+ SH_PFC_PIN_GROUP(iic2_b),
+ SH_PFC_PIN_GROUP(iic2_c),
+ SH_PFC_PIN_GROUP(iic2_d),
+ SH_PFC_PIN_GROUP(iic2_e),
+ SH_PFC_PIN_GROUP(iic3),
+ SH_PFC_PIN_GROUP(intc_irq0),
+ SH_PFC_PIN_GROUP(intc_irq1),
+ SH_PFC_PIN_GROUP(intc_irq2),
+ SH_PFC_PIN_GROUP(intc_irq3),
+ SH_PFC_PIN_GROUP(mmc0_data1),
+ SH_PFC_PIN_GROUP(mmc0_data4),
+ SH_PFC_PIN_GROUP(mmc0_data8),
+ SH_PFC_PIN_GROUP(mmc0_ctrl),
+ SH_PFC_PIN_GROUP(mmc1_data1),
+ SH_PFC_PIN_GROUP(mmc1_data4),
+ SH_PFC_PIN_GROUP(mmc1_data8),
+ SH_PFC_PIN_GROUP(mmc1_ctrl),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_rx),
+ SH_PFC_PIN_GROUP(msiof0_tx),
+ SH_PFC_PIN_GROUP(msiof0_clk_b),
+ SH_PFC_PIN_GROUP(msiof0_ss1_b),
+ SH_PFC_PIN_GROUP(msiof0_ss2_b),
+ SH_PFC_PIN_GROUP(msiof0_rx_b),
+ SH_PFC_PIN_GROUP(msiof0_tx_b),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_rx),
+ SH_PFC_PIN_GROUP(msiof1_tx),
+ SH_PFC_PIN_GROUP(msiof1_clk_b),
+ SH_PFC_PIN_GROUP(msiof1_ss1_b),
+ SH_PFC_PIN_GROUP(msiof1_ss2_b),
+ SH_PFC_PIN_GROUP(msiof1_rx_b),
+ SH_PFC_PIN_GROUP(msiof1_tx_b),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_rx),
+ SH_PFC_PIN_GROUP(msiof2_tx),
+ SH_PFC_PIN_GROUP(msiof3_clk),
+ SH_PFC_PIN_GROUP(msiof3_sync),
+ SH_PFC_PIN_GROUP(msiof3_ss1),
+ SH_PFC_PIN_GROUP(msiof3_ss2),
+ SH_PFC_PIN_GROUP(msiof3_rx),
+ SH_PFC_PIN_GROUP(msiof3_tx),
+ SH_PFC_PIN_GROUP(msiof3_clk_b),
+ SH_PFC_PIN_GROUP(msiof3_sync_b),
+ SH_PFC_PIN_GROUP(msiof3_rx_b),
+ SH_PFC_PIN_GROUP(msiof3_tx_b),
+ SH_PFC_PIN_GROUP(pwm0),
+ SH_PFC_PIN_GROUP(pwm0_b),
+ SH_PFC_PIN_GROUP(pwm1),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2),
+ SH_PFC_PIN_GROUP(pwm3),
+ SH_PFC_PIN_GROUP(pwm4),
+ SH_PFC_PIN_GROUP(pwm5),
+ SH_PFC_PIN_GROUP(pwm6),
+ SH_PFC_PIN_GROUP(qspi_ctrl),
+ SH_PFC_PIN_GROUP(qspi_data2),
+ SH_PFC_PIN_GROUP(qspi_data4),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_data_c),
+ SH_PFC_PIN_GROUP(scif1_data_d),
+ SH_PFC_PIN_GROUP(scif1_clk_d),
+ SH_PFC_PIN_GROUP(scif1_data_e),
+ SH_PFC_PIN_GROUP(scif1_clk_e),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scifa0_data),
+ SH_PFC_PIN_GROUP(scifa0_clk),
+ SH_PFC_PIN_GROUP(scifa0_ctrl),
+ SH_PFC_PIN_GROUP(scifa0_data_b),
+ SH_PFC_PIN_GROUP(scifa0_clk_b),
+ SH_PFC_PIN_GROUP(scifa0_ctrl_b),
+ SH_PFC_PIN_GROUP(scifa1_data),
+ SH_PFC_PIN_GROUP(scifa1_clk),
+ SH_PFC_PIN_GROUP(scifa1_ctrl),
+ SH_PFC_PIN_GROUP(scifa1_data_b),
+ SH_PFC_PIN_GROUP(scifa1_clk_b),
+ SH_PFC_PIN_GROUP(scifa1_ctrl_b),
+ SH_PFC_PIN_GROUP(scifa1_data_c),
+ SH_PFC_PIN_GROUP(scifa1_clk_c),
+ SH_PFC_PIN_GROUP(scifa1_ctrl_c),
+ SH_PFC_PIN_GROUP(scifa1_data_d),
+ SH_PFC_PIN_GROUP(scifa1_clk_d),
+ SH_PFC_PIN_GROUP(scifa1_ctrl_d),
+ SH_PFC_PIN_GROUP(scifa2_data),
+ SH_PFC_PIN_GROUP(scifa2_clk),
+ SH_PFC_PIN_GROUP(scifa2_ctrl),
+ SH_PFC_PIN_GROUP(scifa2_data_b),
+ SH_PFC_PIN_GROUP(scifa2_data_c),
+ SH_PFC_PIN_GROUP(scifa2_clk_c),
+ SH_PFC_PIN_GROUP(scifb0_data),
+ SH_PFC_PIN_GROUP(scifb0_clk),
+ SH_PFC_PIN_GROUP(scifb0_ctrl),
+ SH_PFC_PIN_GROUP(scifb0_data_b),
+ SH_PFC_PIN_GROUP(scifb0_clk_b),
+ SH_PFC_PIN_GROUP(scifb0_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb0_data_c),
+ SH_PFC_PIN_GROUP(scifb1_data),
+ SH_PFC_PIN_GROUP(scifb1_clk),
+ SH_PFC_PIN_GROUP(scifb1_ctrl),
+ SH_PFC_PIN_GROUP(scifb1_data_b),
+ SH_PFC_PIN_GROUP(scifb1_clk_b),
+ SH_PFC_PIN_GROUP(scifb1_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb1_data_c),
+ SH_PFC_PIN_GROUP(scifb1_data_d),
+ SH_PFC_PIN_GROUP(scifb1_data_e),
+ SH_PFC_PIN_GROUP(scifb1_clk_e),
+ SH_PFC_PIN_GROUP(scifb1_data_f),
+ SH_PFC_PIN_GROUP(scifb1_data_g),
+ SH_PFC_PIN_GROUP(scifb1_clk_g),
+ SH_PFC_PIN_GROUP(scifb2_data),
+ SH_PFC_PIN_GROUP(scifb2_clk),
+ SH_PFC_PIN_GROUP(scifb2_ctrl),
+ SH_PFC_PIN_GROUP(scifb2_data_b),
+ SH_PFC_PIN_GROUP(scifb2_clk_b),
+ SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb2_data_c),
+ SH_PFC_PIN_GROUP(scif_clk),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd),
+ SH_PFC_PIN_GROUP(sdhi2_wp),
+ SH_PFC_PIN_GROUP(sdhi3_data1),
+ SH_PFC_PIN_GROUP(sdhi3_data4),
+ SH_PFC_PIN_GROUP(sdhi3_ctrl),
+ SH_PFC_PIN_GROUP(sdhi3_cd),
+ SH_PFC_PIN_GROUP(sdhi3_wp),
+ SH_PFC_PIN_GROUP(ssi0_data),
+ SH_PFC_PIN_GROUP(ssi0129_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_data),
+ SH_PFC_PIN_GROUP(ssi1_ctrl),
+ SH_PFC_PIN_GROUP(ssi2_data),
+ SH_PFC_PIN_GROUP(ssi2_ctrl),
+ SH_PFC_PIN_GROUP(ssi3_data),
+ SH_PFC_PIN_GROUP(ssi34_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data),
+ SH_PFC_PIN_GROUP(ssi4_ctrl),
+ SH_PFC_PIN_GROUP(ssi5),
+ SH_PFC_PIN_GROUP(ssi5_b),
+ SH_PFC_PIN_GROUP(ssi5_c),
+ SH_PFC_PIN_GROUP(ssi6),
+ SH_PFC_PIN_GROUP(ssi6_b),
+ SH_PFC_PIN_GROUP(ssi7_data),
+ SH_PFC_PIN_GROUP(ssi7_b_data),
+ SH_PFC_PIN_GROUP(ssi7_c_data),
+ SH_PFC_PIN_GROUP(ssi78_ctrl),
+ SH_PFC_PIN_GROUP(ssi78_b_ctrl),
+ SH_PFC_PIN_GROUP(ssi78_c_ctrl),
+ SH_PFC_PIN_GROUP(ssi8_data),
+ SH_PFC_PIN_GROUP(ssi8_b_data),
+ SH_PFC_PIN_GROUP(ssi8_c_data),
+ SH_PFC_PIN_GROUP(ssi9_data),
+ SH_PFC_PIN_GROUP(ssi9_ctrl),
+ SH_PFC_PIN_GROUP(tpu0_to0),
+ SH_PFC_PIN_GROUP(tpu0_to1),
+ SH_PFC_PIN_GROUP(tpu0_to2),
+ SH_PFC_PIN_GROUP(tpu0_to3),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb0_ovc_vbus),
+ SH_PFC_PIN_GROUP(usb1),
+ SH_PFC_PIN_GROUP(usb2),
+ VIN_DATA_PIN_GROUP(vin0_data, 24),
+ VIN_DATA_PIN_GROUP(vin0_data, 20),
+ SH_PFC_PIN_GROUP(vin0_data18),
+ VIN_DATA_PIN_GROUP(vin0_data, 16),
+ VIN_DATA_PIN_GROUP(vin0_data, 12),
+ VIN_DATA_PIN_GROUP(vin0_data, 10),
+ VIN_DATA_PIN_GROUP(vin0_data, 8),
+ VIN_DATA_PIN_GROUP(vin0_data, 4),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ VIN_DATA_PIN_GROUP(vin1_data, 24),
+ VIN_DATA_PIN_GROUP(vin1_data, 20),
+ SH_PFC_PIN_GROUP(vin1_data18),
+ VIN_DATA_PIN_GROUP(vin1_data, 16),
+ VIN_DATA_PIN_GROUP(vin1_data, 12),
+ VIN_DATA_PIN_GROUP(vin1_data, 10),
+ VIN_DATA_PIN_GROUP(vin1_data, 8),
+ VIN_DATA_PIN_GROUP(vin1_data, 4),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+ VIN_DATA_PIN_GROUP(vin2_data, 24),
+ SH_PFC_PIN_GROUP(vin2_data18),
+ VIN_DATA_PIN_GROUP(vin2_data, 16),
+ VIN_DATA_PIN_GROUP(vin2_data, 8),
+ VIN_DATA_PIN_GROUP(vin2_data, 4),
+ SH_PFC_PIN_GROUP(vin2_sync),
+ SH_PFC_PIN_GROUP(vin2_field),
+ SH_PFC_PIN_GROUP(vin2_clkenb),
+ SH_PFC_PIN_GROUP(vin2_clk),
+ SH_PFC_PIN_GROUP(vin3_data8),
+ SH_PFC_PIN_GROUP(vin3_sync),
+ SH_PFC_PIN_GROUP(vin3_field),
+ SH_PFC_PIN_GROUP(vin3_clkenb),
+ SH_PFC_PIN_GROUP(vin3_clk),
+ },
+ .automotive = {
+ SH_PFC_PIN_GROUP(mlb_3pin),
+ }
};
static const char * const audio_clk_groups[] = {
@@ -4708,63 +4715,70 @@ static const char * const vin3_groups[] = {
"vin3_clk",
};
-static const struct sh_pfc_function pinmux_functions[] = {
- SH_PFC_FUNCTION(audio_clk),
- SH_PFC_FUNCTION(avb),
- SH_PFC_FUNCTION(du),
- SH_PFC_FUNCTION(du0),
- SH_PFC_FUNCTION(du1),
- SH_PFC_FUNCTION(du2),
- SH_PFC_FUNCTION(eth),
- SH_PFC_FUNCTION(hscif0),
- SH_PFC_FUNCTION(hscif1),
- SH_PFC_FUNCTION(i2c0),
- SH_PFC_FUNCTION(i2c1),
- SH_PFC_FUNCTION(i2c2),
- SH_PFC_FUNCTION(i2c3),
- SH_PFC_FUNCTION(iic0),
- SH_PFC_FUNCTION(iic1),
- SH_PFC_FUNCTION(iic2),
- SH_PFC_FUNCTION(iic3),
- SH_PFC_FUNCTION(intc),
- SH_PFC_FUNCTION(mlb),
- SH_PFC_FUNCTION(mmc0),
- SH_PFC_FUNCTION(mmc1),
- SH_PFC_FUNCTION(msiof0),
- SH_PFC_FUNCTION(msiof1),
- SH_PFC_FUNCTION(msiof2),
- SH_PFC_FUNCTION(msiof3),
- SH_PFC_FUNCTION(pwm0),
- SH_PFC_FUNCTION(pwm1),
- SH_PFC_FUNCTION(pwm2),
- SH_PFC_FUNCTION(pwm3),
- SH_PFC_FUNCTION(pwm4),
- SH_PFC_FUNCTION(pwm5),
- SH_PFC_FUNCTION(pwm6),
- SH_PFC_FUNCTION(qspi),
- SH_PFC_FUNCTION(scif0),
- SH_PFC_FUNCTION(scif1),
- SH_PFC_FUNCTION(scif2),
- SH_PFC_FUNCTION(scifa0),
- SH_PFC_FUNCTION(scifa1),
- SH_PFC_FUNCTION(scifa2),
- SH_PFC_FUNCTION(scifb0),
- SH_PFC_FUNCTION(scifb1),
- SH_PFC_FUNCTION(scifb2),
- SH_PFC_FUNCTION(scif_clk),
- SH_PFC_FUNCTION(sdhi0),
- SH_PFC_FUNCTION(sdhi1),
- SH_PFC_FUNCTION(sdhi2),
- SH_PFC_FUNCTION(sdhi3),
- SH_PFC_FUNCTION(ssi),
- SH_PFC_FUNCTION(tpu0),
- SH_PFC_FUNCTION(usb0),
- SH_PFC_FUNCTION(usb1),
- SH_PFC_FUNCTION(usb2),
- SH_PFC_FUNCTION(vin0),
- SH_PFC_FUNCTION(vin1),
- SH_PFC_FUNCTION(vin2),
- SH_PFC_FUNCTION(vin3),
+static const struct {
+ struct sh_pfc_function common[55];
+ struct sh_pfc_function automotive[1];
+} pinmux_functions = {
+ .common = {
+ SH_PFC_FUNCTION(audio_clk),
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(du0),
+ SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(du2),
+ SH_PFC_FUNCTION(eth),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(iic0),
+ SH_PFC_FUNCTION(iic1),
+ SH_PFC_FUNCTION(iic2),
+ SH_PFC_FUNCTION(iic3),
+ SH_PFC_FUNCTION(intc),
+ SH_PFC_FUNCTION(mmc0),
+ SH_PFC_FUNCTION(mmc1),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(pwm5),
+ SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scifa0),
+ SH_PFC_FUNCTION(scifa1),
+ SH_PFC_FUNCTION(scifa2),
+ SH_PFC_FUNCTION(scifb0),
+ SH_PFC_FUNCTION(scifb1),
+ SH_PFC_FUNCTION(scifb2),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(sdhi3),
+ SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(tpu0),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(usb2),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+ SH_PFC_FUNCTION(vin2),
+ SH_PFC_FUNCTION(vin3),
+ },
+ .automotive = {
+ SH_PFC_FUNCTION(mlb),
+ }
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -5707,6 +5721,28 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
+#ifdef CONFIG_PINCTRL_PFC_R8A7742
+const struct sh_pfc_soc_info r8a7742_pinmux_info = {
+ .name = "r8a77420_pfc",
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.name = "r8a77900_pfc",
.unlock_reg = 0xe6060000, /* PMMR */
@@ -5715,13 +5751,16 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
- .groups = pinmux_groups,
- .nr_groups = ARRAY_SIZE(pinmux_groups),
- .functions = pinmux_functions,
- .nr_functions = ARRAY_SIZE(pinmux_functions),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+ ARRAY_SIZE(pinmux_groups.automotive),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+ ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
+#endif
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5313): https://lists.cip-project.org/g/cip-dev/message/5313
Mute This Topic: https://lists.cip-project.org/mt/76477101/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 24/30] ARM: dts: r8a7742: Initial SoC device tree
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (22 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 23/30] pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 25/30] dt-bindings: gpio: renesas, rcar-gpio: Add r8a7742 (RZ/G1H) support Biju Das
` (6 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 25954 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit eb4cdda7a30b3f9894fd5a58e0201fa57861183f upstream.
The initial R8A7742 SoC device tree including CPU[0-8], PMU, PFC,
CPG, RST, SYSC, ICRAM[0-2], SCIFA2, MMC1, DMAC[0-1], GIC, PRR, timer
and the required clock descriptions.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588542414-14826-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: reworked on clock, removed sysc, prr device nodes]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 769 +++++++++++++++++++++++++++++++++
1 file changed, 769 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7742.dtsi
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
new file mode 100644
index 000000000000..af2ea73f9557
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -0,0 +1,769 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a7742 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/r8a7742-clock.h>
+
+/ {
+ compatible = "renesas,r8a7742";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* Special CPG clocks */
+ cpg_clocks: cpg_clocks@e6150000 {
+ compatible = "renesas,r8a7742-cpg-clocks",
+ "renesas,rcar-gen2-cpg-clocks";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk &usb_extal_clk>;
+ #clock-cells = <1>;
+ clock-output-names = "main", "pll0", "pll1", "pll3",
+ "lb", "qspi", "sdh", "sd0", "sd1",
+ "z", "rcan";
+ #power-domain-cells = <0>;
+ };
+
+ /* Variable factor clocks */
+ sd2_clk: sd2_clk@e6150078 {
+ compatible = "renesas,r8a7742-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0 0xe6150078 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "sd2";
+ };
+ sd3_clk: sd3_clk@e615026c {
+ compatible = "renesas,r8a7742-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0 0xe615026c 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "sd3";
+ };
+ mmc0_clk: mmc0_clk@e6150240 {
+ compatible = "renesas,r8a7742-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0 0xe6150240 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "mmc0";
+ };
+ mmc1_clk: mmc1_clk@e6150244 {
+ compatible = "renesas,r8a7742-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0 0xe6150244 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "mmc1";
+ };
+ ssp_clk: ssp_clk@e6150248 {
+ compatible = "renesas,r8a7742-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0 0xe6150248 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "ssp";
+ };
+ ssprs_clk: ssprs_clk@e615024c {
+ compatible = "renesas,r8a7742-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0 0xe615024c 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "ssprs";
+ };
+
+ /* Fixed factor clocks */
+ pll1_div2_clk: pll1_div2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "pll1_div2";
+ };
+ z2_clk: z2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "z2";
+ };
+ zg_clk: zg_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <3>;
+ clock-mult = <1>;
+ clock-output-names = "zg";
+ };
+ zx_clk: zx_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <3>;
+ clock-mult = <1>;
+ clock-output-names = "zx";
+ };
+ zs_clk: zs_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <6>;
+ clock-mult = <1>;
+ clock-output-names = "zs";
+ };
+ hp_clk: hp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <12>;
+ clock-mult = <1>;
+ clock-output-names = "hp";
+ };
+ i_clk: i_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "i";
+ };
+ b_clk: b_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <12>;
+ clock-mult = <1>;
+ clock-output-names = "b";
+ };
+ p_clk: p_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <24>;
+ clock-mult = <1>;
+ clock-output-names = "p";
+ };
+ cl_clk: cl_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <48>;
+ clock-mult = <1>;
+ clock-output-names = "cl";
+ };
+ m2_clk: m2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "m2";
+ };
+ imp_clk: imp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clock-output-names = "imp";
+ };
+ rclk_clk: rclk_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <(48 * 1024)>;
+ clock-mult = <1>;
+ clock-output-names = "rclk";
+ };
+ oscclk_clk: oscclk_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <(12 * 1024)>;
+ clock-mult = <1>;
+ clock-output-names = "oscclk";
+ };
+ zb3_clk: zb3_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clock-output-names = "zb3";
+ };
+ zb3d2_clk: zb3d2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "zb3d2";
+ };
+ ddr_clk: ddr_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7742_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "ddr";
+ };
+ mp_clk: mp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-div = <15>;
+ clock-mult = <1>;
+ clock-output-names = "mp";
+ };
+ cp_clk: cp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&extal_clk>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "cp";
+ };
+
+ /* Gate clocks */
+ mstp0_clks: mstp0_clks@e6150130 {
+ compatible = "renesas,r8a7742-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+ clocks = <&mp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <R8A7742_CLK_MSIOF0>;
+ clock-output-names = "msiof0";
+ };
+ mstp1_clks: mstp1_clks@e6150134 {
+ compatible = "renesas,r8a7742-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+ clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
+ <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
+ <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
+ <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
+ <&zs_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7742_CLK_VCP1 R8A7742_CLK_VCP0
+ R8A7742_CLK_VPC1 R8A7742_CLK_VPC0
+ R8A7742_CLK_TMU1 R8A7742_CLK_3DG
+ R8A7742_CLK_2DDMAC R8A7742_CLK_FDP1_2
+ R8A7742_CLK_FDP1_1 R8A7742_CLK_FDP1_0
+ R8A7742_CLK_TMU3 R8A7742_CLK_TMU2
+ R8A7742_CLK_CMT0 R8A7742_CLK_TMU0
+ R8A7742_CLK_VSP1_DU1 R8A7742_CLK_VSP1_DU0
+ R8A7742_CLK_VSP1_R R8A7742_CLK_VSP1_S
+ >;
+ clock-output-names =
+ "vcp1", "vcp0", "vpc1", "vpc0", "tmu1",
+ "3dg", "2ddmac", "fdp1-2", "fdp1-1", "fdp1-0",
+ "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+ "vsp1-du0", "vspr", "vsps";
+ };
+ mstp2_clks: mstp2_clks@e6150138 {
+ compatible = "renesas,r8a7742-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+ clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+ <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
+ <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7742_CLK_SCIFA2 R8A7742_CLK_SCIFA1 R8A7742_CLK_SCIFA0
+ R8A7742_CLK_MSIOF2 R8A7742_CLK_SCIFB0 R8A7742_CLK_SCIFB1
+ R8A7742_CLK_MSIOF1 R8A7742_CLK_MSIOF3 R8A7742_CLK_SCIFB2
+ R8A7742_CLK_SYS_DMAC1 R8A7742_CLK_SYS_DMAC0
+ >;
+ clock-output-names =
+ "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
+ "scifb1", "msiof1", "msiof3", "scifb2",
+ "sys-dmac1", "sys-dmac0";
+ };
+ mstp3_clks: mstp3_clks@e615013c {
+ compatible = "renesas,r8a7742-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+ clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
+ <&sd2_clk>, <&cpg_clocks R8A7742_CLK_SD1>, <&cpg_clocks R8A7742_CLK_SD0>, <&mmc0_clk>,
+ <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
+ <&hp_clk>, <&hp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7742_CLK_IIC2 R8A7742_CLK_TPU0 R8A7742_CLK_MMCIF1 R8A7742_CLK_SCIF2 R8A7742_CLK_SDHI3
+ R8A7742_CLK_SDHI2 R8A7742_CLK_SDHI1 R8A7742_CLK_SDHI0 R8A7742_CLK_MMCIF0
+ R8A7742_CLK_IIC0 R8A7742_CLK_PCIEC R8A7742_CLK_IIC1 R8A7742_CLK_SSUSB R8A7742_CLK_CMT1
+ R8A7742_CLK_USBDMAC0 R8A7742_CLK_USBDMAC1
+ >;
+ clock-output-names =
+ "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
+ "sdhi2", "sdhi1", "sdhi0", "mmcif0",
+ "iic0", "pciec", "iic1", "ssusb", "cmt1",
+ "usbdmac0", "usbdmac1";
+ };
+ mstp4_clks: mstp4_clks@e6150140 {
+ compatible = "renesas,r8a7742-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+ clocks = <&cp_clk>, <&rclk_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <R8A7742_CLK_IRQC R8A7742_CLK_RWDT R8A7742_CLK_INTC_SYS>;
+ clock-output-names = "irqc", "rwdt", "intc-sys";
+ };
+ mstp5_clks: mstp5_clks@e6150144 {
+ compatible = "renesas,r8a7742-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+ clocks = <&hp_clk>, <&hp_clk>,
+ <&extal_clk>, <&p_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7742_CLK_AUDIO_DMAC0 R8A7742_CLK_AUDIO_DMAC1
+ R8A7742_CLK_THERMAL R8A7742_CLK_PWM
+ >;
+ clock-output-names = "audmac0", "audmac1",
+ "thermal", "pwm";
+ };
+ mstp7_clks: mstp7_clks@e615014c {
+ compatible = "renesas,r8a7742-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+ clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+ <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
+ <&zx_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7742_CLK_EHCI R8A7742_CLK_HSUSB R8A7742_CLK_HSCIF1
+ R8A7742_CLK_HSCIF0 R8A7742_CLK_SCIF1 R8A7742_CLK_SCIF0
+ R8A7742_CLK_DU2 R8A7742_CLK_DU1 R8A7742_CLK_DU0
+ R8A7742_CLK_LVDS1 R8A7742_CLK_LVDS0
+ >;
+ clock-output-names =
+ "ehci", "hsusb", "hscif1", "hscif0", "scif1",
+ "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
+ };
+ mstp8_clks: mstp8_clks@e6150990 {
+ compatible = "renesas,r8a7742-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+ clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
+ <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
+ <&zs_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7742_CLK_R_GP2D R8A7742_CLK_VIN3 R8A7742_CLK_VIN2
+ R8A7742_CLK_VIN1 R8A7742_CLK_VIN0
+ R8A7742_CLK_ETHERAVB R8A7742_CLK_ETHER
+ R8A7742_CLK_SATA1 R8A7742_CLK_SATA0
+ R8A7742_CLK_IMR_X2_1 R8A7742_CLK_IMR_X2_0
+ R8A7742_CLK_IMR_LSX2_1 R8A7742_CLK_IMR_LSX2_0
+ >;
+ clock-output-names =
+ "r-gp2d", "vin3", "vin2", "vin1", "vin0",
+ "etheravb", "ether", "sata1", "sata0",
+ "imr-x2-1", "imr-x2-0", "imr-lsx2-1", "imr-lsx2-0";
+ };
+ mstp9_clks: mstp9_clks@e6150994 {
+ compatible = "renesas,r8a7742-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+ clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
+ <&cp_clk>, <&cp_clk>, <&cp_clk>,
+ <&p_clk>, <&p_clk>, <&cpg_clocks R8A7742_CLK_QSPI>, <&cp_clk>,
+ <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7742_CLK_GPIO5 R8A7742_CLK_GPIO4 R8A7742_CLK_GPIO3
+ R8A7742_CLK_GPIO2 R8A7742_CLK_GPIO1 R8A7742_CLK_GPIO0
+ R8A7742_CLK_RCAN1 R8A7742_CLK_RCAN0 R8A7742_CLK_QSPI_MOD R8A7742_CLK_IICDVFS
+ R8A7742_CLK_I2C3 R8A7742_CLK_I2C2 R8A7742_CLK_I2C1 R8A7742_CLK_I2C0
+ >;
+ clock-output-names =
+ "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
+ "rcan1", "rcan0", "qspi_mod", "iic3",
+ "i2c3", "i2c2", "i2c1", "i2c0";
+ };
+ mstp10_clks: mstp10_clks@e6150998 {
+ compatible = "renesas,r8a7742-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+ clocks = <&p_clk>,
+ <&mstp10_clks R8A7742_CLK_SSI_ALL>, <&mstp10_clks R8A7742_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7742_CLK_SSI_ALL>, <&mstp10_clks R8A7742_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7742_CLK_SSI_ALL>, <&mstp10_clks R8A7742_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7742_CLK_SSI_ALL>, <&mstp10_clks R8A7742_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7742_CLK_SSI_ALL>, <&mstp10_clks R8A7742_CLK_SSI_ALL>,
+ <&p_clk>,
+ <&mstp10_clks R8A7742_CLK_SCU_ALL>, <&mstp10_clks R8A7742_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7742_CLK_SCU_ALL>, <&mstp10_clks R8A7742_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7742_CLK_SCU_ALL>, <&mstp10_clks R8A7742_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7742_CLK_SCU_ALL>, <&mstp10_clks R8A7742_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7742_CLK_SCU_ALL>, <&mstp10_clks R8A7742_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7742_CLK_SCU_ALL>, <&mstp10_clks R8A7742_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7742_CLK_SCU_ALL>, <&mstp10_clks R8A7742_CLK_SCU_ALL>;
+
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7742_CLK_SSI_ALL
+ R8A7742_CLK_SSI9 R8A7742_CLK_SSI8 R8A7742_CLK_SSI7 R8A7742_CLK_SSI6 R8A7742_CLK_SSI5
+ R8A7742_CLK_SSI4 R8A7742_CLK_SSI3 R8A7742_CLK_SSI2 R8A7742_CLK_SSI1 R8A7742_CLK_SSI0
+ R8A7742_CLK_SCU_ALL
+ R8A7742_CLK_SCU_DVC1 R8A7742_CLK_SCU_DVC0
+ R8A7742_CLK_SCU_CTU1_MIX1 R8A7742_CLK_SCU_CTU0_MIX0
+ R8A7742_CLK_SCU_SRC9 R8A7742_CLK_SCU_SRC8 R8A7742_CLK_SCU_SRC7 R8A7742_CLK_SCU_SRC6 R8A7742_CLK_SCU_SRC5
+ R8A7742_CLK_SCU_SRC4 R8A7742_CLK_SCU_SRC3 R8A7742_CLK_SCU_SRC2 R8A7742_CLK_SCU_SRC1 R8A7742_CLK_SCU_SRC0
+ >;
+ clock-output-names =
+ "ssi-all",
+ "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+ "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+ "scu-all",
+ "scu-dvc1", "scu-dvc0",
+ "scu-ctu1-mix1", "scu-ctu0-mix0",
+ "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
+ "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg_clocks R8A7742_CLK_Z>;
+ power-domains = <&cpg_clocks>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg_clocks R8A7742_CLK_Z>;
+ power-domains = <&cpg_clocks>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg_clocks R8A7742_CLK_Z>;
+ power-domains = <&cpg_clocks>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg_clocks R8A7742_CLK_Z>;
+ power-domains = <&cpg_clocks>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg_clocks R8A7742_CLK_Z2>;
+ power-domains = <&cpg_clocks>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg_clocks R8A7742_CLK_Z2>;
+ power-domains = <&cpg_clocks>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg_clocks R8A7742_CLK_Z2>;
+ power-domains = <&cpg_clocks>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg_clocks R8A7742_CLK_Z2>;
+ power-domains = <&cpg_clocks>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ L2_CA15: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&cpg_clocks>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ L2_CA7: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&cpg_clocks>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ pmu-0 {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ pmu-1 {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7742";
+ reg = <0 0xe6060000 0 0x250>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7742-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x100>;
+ };
+ };
+
+ icram2: sram@e6300000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe6300000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x40000>;
+ };
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7742",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&mstp2_clks R8A7742_CLK_SYS_DMAC0>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7742",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&mstp2_clks R8A7742_CLK_SYS_DMAC1>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7742",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 0x40>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7742_CLK_SCIFA2>;
+ clock-names = "sci_ick";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ mmcif1: mmc@ee220000 {
+ compatible = "renesas,mmcif-r8a7742",
+ "renesas,sh-mmcif";
+ reg = <0 0xee220000 0 0x80>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7742_CLK_MMCIF1>;
+ dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
+ <&dmac1 0xe1>, <&dmac1 0xe2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&mstp4_clks R8A7742_CLK_INTC_SYS>;
+ clock-names = "clk";
+ power-domains = <&cpg_clocks>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+};
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5314): https://lists.cip-project.org/g/cip-dev/message/5314
Mute This Topic: https://lists.cip-project.org/mt/76477103/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 25/30] dt-bindings: gpio: renesas, rcar-gpio: Add r8a7742 (RZ/G1H) support
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (23 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 24/30] ARM: dts: r8a7742: Initial SoC device tree Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 26/30] ARM: dts: r8a7742: Add GPIO nodes Biju Das
` (5 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1486 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 39c7c93de02c2c0c150ff41f33068c201b964050 upstream.
Renesas RZ/G1H (R8A7742) SoC GPIO blocks are identical to the R-Car Gen2
family. Add support for its GPIO controllers.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
index 52fa8e4d8353..74e2897013c8 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -3,6 +3,7 @@
Required Properties:
- compatible: should contain one or more of the following:
+ - "renesas,gpio-r8a7742": for R8A7742 (RZ/G1H) compatible GPIO controller.
- "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
- "renesas,gpio-r8a7744": for R8A7744 (RZ/G1N) compatible GPIO controller.
- "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5315): https://lists.cip-project.org/g/cip-dev/message/5315
Mute This Topic: https://lists.cip-project.org/mt/76477104/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 26/30] ARM: dts: r8a7742: Add GPIO nodes
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (24 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 25/30] dt-bindings: gpio: renesas, rcar-gpio: Add r8a7742 (RZ/G1H) support Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 27/30] dt-bindings: arm: renesas: Document iW-RainboW-G21M-Qseven-RZG1H SoM Biju Das
` (4 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 3522 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 7fc3b53a7bd6ebfffd22a75f57175b80fa3df834
Describe GPIO blocks in the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588794695-27852-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: removed resets and updated clocks, power-domain properties]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 84 ++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index af2ea73f9557..9e26313e09e1 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -606,6 +606,90 @@
#size-cells = <2>;
ranges;
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7742_CLK_GPIO0>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 30>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7742_CLK_GPIO1>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 30>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7742_CLK_GPIO2>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7742_CLK_GPIO3>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7742_CLK_GPIO4>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7742_CLK_GPIO5>;
+ power-domains = <&cpg_clocks>;
+ };
+
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7742";
reg = <0 0xe6060000 0 0x250>;
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5316): https://lists.cip-project.org/g/cip-dev/message/5316
Mute This Topic: https://lists.cip-project.org/mt/76477105/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 27/30] dt-bindings: arm: renesas: Document iW-RainboW-G21M-Qseven-RZG1H SoM
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (25 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 26/30] ARM: dts: r8a7742: Add GPIO nodes Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 28/30] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM Biju Das
` (3 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1622 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 844beed47182903212d8230ac6d729be1287733e upstream.
Document the iW-RainboW-G21M-Qseven-RZG1H device tree bindings,
listing it as a supported system on module.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588542414-14826-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 1f894d9a2d0f..0afd43e6764d 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -61,6 +61,8 @@ Boards:
compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
- iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
compatible = "iwave,g22m", "renesas,r8a7745"
+ - iWave Systems RZ/G1H Qseven System On Module (iW-RainboW-G21M-Qseven)
+ compatible = "iwave,g21m", "renesas,r8a7742"
- iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5317): https://lists.cip-project.org/g/cip-dev/message/5317
Mute This Topic: https://lists.cip-project.org/mt/76477106/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 28/30] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (26 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 27/30] dt-bindings: arm: renesas: Document iW-RainboW-G21M-Qseven-RZG1H SoM Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 29/30] dt-bindings: arm: renesas: Document iW-RainboW-G21D-Qseven-RZG1H board Biju Das
` (2 subsequent siblings)
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1938 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 269785eaba09172c5189e30d2202084586aeabdd upstream.
Add support for iWave RZ/G1H Qseven System On Module.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588542414-14826-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 53 +++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7742-iwg21m.dtsi
diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
new file mode 100644
index 000000000000..85aff429d408
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave RZ/G1H Qseven SOM
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a7742.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "iwave,g21m", "renesas,r8a7742";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ memory@200000000 {
+ device_type = "memory";
+ reg = <2 0x00000000 0 0x40000000>;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ mmc1_pins: mmc1 {
+ groups = "mmc1_data4", "mmc1_ctrl";
+ function = "mmc1";
+ };
+};
+
+&mmcif1 {
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <®_3p3v>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5318): https://lists.cip-project.org/g/cip-dev/message/5318
Mute This Topic: https://lists.cip-project.org/mt/76477107/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 29/30] dt-bindings: arm: renesas: Document iW-RainboW-G21D-Qseven-RZG1H board
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (27 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 28/30] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 30/30] ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H Biju Das
2020-08-28 18:28 ` [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Pavel Machek
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1614 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 0b5832238d369a71f90a221d17b92761595c8067 upsream.
Document the iW-RainboW-G21D-Qseven-RZG1H device tree bindings,
listing it as a supported board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588542414-14826-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 0afd43e6764d..066eabf49d57 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -61,6 +61,8 @@ Boards:
compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
- iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
compatible = "iwave,g22m", "renesas,r8a7745"
+ - iWave Systems RZ/G1H Qseven Development Platform (iW-RainboW-G21D-Qseven)
+ compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"
- iWave Systems RZ/G1H Qseven System On Module (iW-RainboW-G21M-Qseven)
compatible = "iwave,g21m", "renesas,r8a7742"
- iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5319): https://lists.cip-project.org/g/cip-dev/message/5319
Mute This Topic: https://lists.cip-project.org/mt/76477108/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 30/30] ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (28 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 29/30] dt-bindings: arm: renesas: Document iW-RainboW-G21D-Qseven-RZG1H board Biju Das
@ 2020-08-28 15:41 ` Biju Das
2020-08-28 18:28 ` [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Pavel Machek
30 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-28 15:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 2141 bytes --]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 48ad3c4a334ad1e583f5159f43c3623ecaffc9f9 upstream.
Add support for iWave RainboW-G21D-Qseven board based on RZ/G1H.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588542414-14826-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 37 +++++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f279346925a7..09d505aa0d3d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -546,6 +546,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r7s72100-genmai.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
+ r8a7742-iwg21d-q7.dtb \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7744-iwg20d-q7.dtb \
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
new file mode 100644
index 000000000000..1f5c35c66d91
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave-RZ/G1H Qseven board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a7742-iwg21m.dtsi"
+
+/ {
+ model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H";
+ compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
+
+ aliases {
+ serial2 = &scifa2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait";
+ stdout-path = "serial2:115200n8";
+ };
+};
+
+&pfc {
+ scifa2_pins: scifa2 {
+ groups = "scifa2_data_c";
+ function = "scifa2";
+ };
+};
+
+&scifa2 {
+ pinctrl-0 = <&scifa2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5320): https://lists.cip-project.org/g/cip-dev/message/5320
Mute This Topic: https://lists.cip-project.org/mt/76477109/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support
2020-08-28 15:41 [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Biju Das
` (29 preceding siblings ...)
2020-08-28 15:41 ` [cip-dev] [PATCH 4.4.y-cip 30/30] ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H Biju Das
@ 2020-08-28 18:28 ` Pavel Machek
2020-08-29 11:51 ` Pavel Machek
30 siblings, 1 reply; 34+ messages in thread
From: Pavel Machek @ 2020-08-28 18:28 UTC (permalink / raw)
To: Biju Das
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Chris Paterson,
Prabhakar Mahadev Lad
[-- Attachment #1.1: Type: text/plain, Size: 464 bytes --]
Hi!
> This patch series add basic support for iWave RZ/G1H platform based on
> r8a7742 SoC to 4.4.y-cip kernel. Most of the patches in this series
> are cherry-picked from mainline.
Series looks okay to me, I can apply it if there are no comments (and
if gitlab cooperates).
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5325): https://lists.cip-project.org/g/cip-dev/message/5325
Mute This Topic: https://lists.cip-project.org/mt/76477073/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support
2020-08-28 18:28 ` [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support Pavel Machek
@ 2020-08-29 11:51 ` Pavel Machek
2020-08-31 15:05 ` Biju Das
0 siblings, 1 reply; 34+ messages in thread
From: Pavel Machek @ 2020-08-29 11:51 UTC (permalink / raw)
To: Pavel Machek
Cc: Biju Das, cip-dev, Nobuhiro Iwamatsu, Chris Paterson,
Prabhakar Mahadev Lad
[-- Attachment #1.1: Type: text/plain, Size: 499 bytes --]
Hi!
> > This patch series add basic support for iWave RZ/G1H platform based on
> > r8a7742 SoC to 4.4.y-cip kernel. Most of the patches in this series
> > are cherry-picked from mainline.
>
> Series looks okay to me, I can apply it if there are no comments (and
> if gitlab cooperates).
Applied and pushed out.
Thanks,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5328): https://lists.cip-project.org/g/cip-dev/message/5328
Mute This Topic: https://lists.cip-project.org/mt/76477073/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [cip-dev] [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support
2020-08-29 11:51 ` Pavel Machek
@ 2020-08-31 15:05 ` Biju Das
0 siblings, 0 replies; 34+ messages in thread
From: Biju Das @ 2020-08-31 15:05 UTC (permalink / raw)
To: Pavel Machek
Cc: cip-dev, Nobuhiro Iwamatsu, Chris Paterson, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1354 bytes --]
Thanks Pavel.
Cheers,
Biju
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 29 August 2020 12:52
> To: Pavel Machek <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; cip-dev@lists.cip-project.org;
> Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: Re: [PATCH 4.4.y-cip 00/30] Add iWave RZ/G1H basic board support
>
> Hi!
>
> > > This patch series add basic support for iWave RZ/G1H platform based
> > > on
> > > r8a7742 SoC to 4.4.y-cip kernel. Most of the patches in this series
> > > are cherry-picked from mainline.
> >
> > Series looks okay to me, I can apply it if there are no comments (and
> > if gitlab cooperates).
>
> Applied and pushed out.
>
> Thanks,
> Pavel
>
> --
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
[-- Attachment #2: Type: text/plain, Size: 419 bytes --]
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5340): https://lists.cip-project.org/g/cip-dev/message/5340
Mute This Topic: https://lists.cip-project.org/mt/76477073/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply [flat|nested] 34+ messages in thread