* [cip-dev] [PATCH 4.19.y-cip 01/17] arm64: dts: renesas: r8a774e1: Add FCPF and FCPV instances
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 02/17] arm64: dts: renesas: r8a774e1: Add VSP instances Lad Prabhakar
` (16 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 2753 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit a3855ebcded87ff8368e61139d98c891a842e7b2 upstream.
Add FCPF and FCPV instances to the r8a774e1 dtsi.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200810092208.27320-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied changes to dtsi]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 64 +++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 8e9292d46cc4..2020ed243c62 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1620,6 +1620,70 @@
status = "disabled";
};
+ fcpf0: fcp@fe950000 {
+ compatible = "renesas,fcpf";
+ reg = <0 0xfe950000 0 0x200>;
+ clocks = <&cpg CPG_MOD 615>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 615>;
+ };
+
+ fcpf1: fcp@fe951000 {
+ compatible = "renesas,fcpf";
+ reg = <0 0xfe951000 0 0x200>;
+ clocks = <&cpg CPG_MOD 614>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 614>;
+ };
+
+ fcpvb0: fcp@fe96f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe96f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 607>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 607>;
+ };
+
+ fcpvb1: fcp@fe92f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe92f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 606>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 606>;
+ };
+
+ fcpvi0: fcp@fe9af000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe9af000 0 0x200>;
+ clocks = <&cpg CPG_MOD 611>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 611>;
+ };
+
+ fcpvi1: fcp@fe9bf000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe9bf000 0 0x200>;
+ clocks = <&cpg CPG_MOD 610>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 610>;
+ };
+
+ fcpvd0: fcp@fea27000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea27000 0 0x200>;
+ clocks = <&cpg CPG_MOD 603>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 603>;
+ };
+
+ fcpvd1: fcp@fea2f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea2f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 602>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 602>;
+ };
+
hdmi0: hdmi@fead0000 {
reg = <0 0xfead0000 0 0x10000>;
status = "disabled";
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 02/17] arm64: dts: renesas: r8a774e1: Add VSP instances
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 01/17] arm64: dts: renesas: r8a774e1: Add FCPF and FCPV instances Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 03/17] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes Lad Prabhakar
` (15 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 2882 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 4398ab2367fa0394170543845041d26afcefe421 upstream.
The RZ/G2H (R8A774E1) has 6 VSP instances.
Based on the work done for r8a7795 SoC.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200810092208.27320-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied changes to dtsi]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 66 +++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 2020ed243c62..453efa21e9d5 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1620,6 +1620,72 @@
status = "disabled";
};
+ vspbc: vsp@fe920000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe920000 0 0x8000>;
+ interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 624>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 624>;
+
+ renesas,fcp = <&fcpvb1>;
+ };
+
+ vspbd: vsp@fe960000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe960000 0 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 626>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 626>;
+
+ renesas,fcp = <&fcpvb0>;
+ };
+
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x5000>;
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 623>;
+
+ renesas,fcp = <&fcpvd0>;
+ };
+
+ vspd1: vsp@fea28000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea28000 0 0x5000>;
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 622>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 622>;
+
+ renesas,fcp = <&fcpvd1>;
+ };
+
+ vspi0: vsp@fe9a0000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe9a0000 0 0x8000>;
+ interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 631>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 631>;
+
+ renesas,fcp = <&fcpvi0>;
+ };
+
+ vspi1: vsp@fe9b0000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe9b0000 0 0x8000>;
+ interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 630>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 630>;
+
+ renesas,fcp = <&fcpvi1>;
+ };
+
fcpf0: fcp@fe950000 {
compatible = "renesas,fcpf";
reg = <0 0xfe950000 0 0x200>;
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 03/17] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 01/17] arm64: dts: renesas: r8a774e1: Add FCPF and FCPV instances Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 02/17] arm64: dts: renesas: r8a774e1: Add VSP instances Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 04/17] dt-bindings: display: renesas,du: Document r8a774e1 bindings Lad Prabhakar
` (14 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1633 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit ff9e786f0ee0cc33aedabaa56678cb45d3c1ca0b upstream.
Add FDP1 device nodes to R8A774E1 (RZ/G2H) SoC dtsi.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200827145315.26261-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 453efa21e9d5..76a4d53db888 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1686,6 +1686,26 @@
renesas,fcp = <&fcpvi1>;
};
+ fdp1@fe940000 {
+ compatible = "renesas,fdp1";
+ reg = <0 0xfe940000 0 0x2400>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 119>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 119>;
+ renesas,fcp = <&fcpf0>;
+ };
+
+ fdp1@fe944000 {
+ compatible = "renesas,fdp1";
+ reg = <0 0xfe944000 0 0x2400>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 118>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ resets = <&cpg 118>;
+ renesas,fcp = <&fcpf1>;
+ };
+
fcpf0: fcp@fe950000 {
compatible = "renesas,fcpf";
reg = <0 0xfe950000 0 0x200>;
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 04/17] dt-bindings: display: renesas,du: Document r8a774e1 bindings
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (2 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 03/17] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 05/17] drm: rcar-du: Add support for R8A774E1 SoC Lad Prabhakar
` (13 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 2085 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 4b6f2b971e8d142474b7ab7e6d3c23e38d83057f upstream.
Document the RZ/G2H (a.k.a. r8a774e1) SoC in the R-Car DU bindings.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/display/renesas,du.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt
index 8f9d65c8912b..9282d79aba9f 100644
--- a/Documentation/devicetree/bindings/display/renesas,du.txt
+++ b/Documentation/devicetree/bindings/display/renesas,du.txt
@@ -7,6 +7,7 @@ Required Properties:
- "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
- "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU
- "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
+ - "renesas,du-r8a774e1" for R8A774E1 (RZ/G2H) compatible DU
- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
@@ -55,6 +56,7 @@ corresponding to each DU output.
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 -
R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
+ R8A774E1 (RZ/G2H) DPAD 0 HDMI 0 LVDS 0 -
R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 05/17] drm: rcar-du: Add support for R8A774E1 SoC
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (3 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 04/17] dt-bindings: display: renesas,du: Document r8a774e1 bindings Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 06/17] arm64: dts: renesas: r8a774e1: Populate DU device node Lad Prabhakar
` (12 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 2464 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 31057d444d41ea820a5c61126e2c810a80a16e79 upstream.
Hookup RZ/G2H (R8A774E1) to DU driver. R8A774E1 has one RGB output,
one LVDS output and one HDMI output.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 30 +++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index d881a2757427..9ab442d80b04 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -164,6 +164,35 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
.lvds_clk_mask = BIT(1) | BIT(0),
};
+static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
+ .gen = 3,
+ .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ | RCAR_DU_FEATURE_VSP1_SOURCE
+ | RCAR_DU_FEATURE_INTERLACED
+ | RCAR_DU_FEATURE_TVM_SYNC,
+ .channels_mask = BIT(3) | BIT(1) | BIT(0),
+ .routes = {
+ /*
+ * R8A774E1 has one RGB output, one LVDS output and one HDMI
+ * output.
+ */
+ [RCAR_DU_OUTPUT_DPAD0] = {
+ .possible_crtcs = BIT(2),
+ .port = 0,
+ },
+ [RCAR_DU_OUTPUT_HDMI0] = {
+ .possible_crtcs = BIT(1),
+ .port = 1,
+ },
+ [RCAR_DU_OUTPUT_LVDS0] = {
+ .possible_crtcs = BIT(0),
+ .port = 2,
+ },
+ },
+ .num_lvds = 1,
+ .dpll_mask = BIT(1),
+};
+
static const struct rcar_du_device_info rcar_du_r8a7779_info = {
.gen = 1,
.features = RCAR_DU_FEATURE_INTERLACED
@@ -396,6 +425,7 @@ static const struct of_device_id rcar_du_of_table[] = {
{ .compatible = "renesas,du-r8a774a1", .data = &rcar_du_r8a774a1_info },
{ .compatible = "renesas,du-r8a774b1", .data = &rcar_du_r8a774b1_info },
{ .compatible = "renesas,du-r8a774c0", .data = &rcar_du_r8a774c0_info },
+ { .compatible = "renesas,du-r8a774e1", .data = &rcar_du_r8a774e1_info },
{ .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
{ .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
{ .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 06/17] arm64: dts: renesas: r8a774e1: Populate DU device node
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (4 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 05/17] drm: rcar-du: Add support for R8A774E1 SoC Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 07/17] dt-bindings: display: renesas,dw-hdmi: Add r8a774e1 support Lad Prabhakar
` (11 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1940 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit f22d0550b83570b10e8f4a474d9629fd4ad76db7 upstream.
Populate the DU device node properties in R8A774E1 SoC dtsi.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200812140217.24251-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Renamed renesas,vsps property to vsps]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 76a4d53db888..3a19ac715f04 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1793,22 +1793,39 @@
};
du: display@feb00000 {
+ compatible = "renesas,du-r8a774e1";
reg = <0 0xfeb00000 0 0x80000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 721>;
+ clock-names = "du.0", "du.1", "du.3";
+ resets = <&cpg 724>, <&cpg 722>;
+ reset-names = "du.0", "du.3";
status = "disabled";
- /* placeholder */
+ vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
+ du_out_rgb: endpoint {
+ };
};
port@1 {
reg = <1>;
+ du_out_hdmi0: endpoint {
+ };
};
port@2 {
reg = <2>;
+ du_out_lvds0: endpoint {
+ };
};
};
};
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 07/17] dt-bindings: display: renesas,dw-hdmi: Add r8a774e1 support
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (5 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 06/17] arm64: dts: renesas: r8a774e1: Populate DU device node Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 08/17] arm64: dts: renesas: r8a774e1: Populate HDMI encoder node Lad Prabhakar
` (10 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1540 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 0c905a0a30d16c43efc381a29f509fbff606b91d upstream.
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[PL: Manually applied changes to binding document]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../devicetree/bindings/display/bridge/renesas,dw-hdmi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
index db680413e89c..9b02bd66124d 100644
--- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
@@ -13,6 +13,7 @@ Required properties:
- compatible : Shall contain one or more of
- "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
+ - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
- "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
- "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 08/17] arm64: dts: renesas: r8a774e1: Populate HDMI encoder node
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (6 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 07/17] dt-bindings: display: renesas,dw-hdmi: Add r8a774e1 support Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 09/17] dt-bindings: display: renesas,lvds: Document r8a774e1 bindings Lad Prabhakar
` (9 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1907 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 5698b68de784f483fa4ea405a49097854c4886e4 upstream.
Populate HDMI node properties in R8A774E1 SoC dtsi.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200812140217.24251-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 3a19ac715f04..8ee028207ce7 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1771,22 +1771,32 @@
};
hdmi0: hdmi@fead0000 {
+ compatible = "renesas,r8a774e1-hdmi",
+ "renesas,rcar-gen3-hdmi";
reg = <0 0xfead0000 0 0x10000>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 729>,
+ <&cpg CPG_CORE R8A774E1_CLK_HDMI>;
+ clock-names = "iahb", "isfr";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 729>;
status = "disabled";
- /* placeholder */
-
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
+ dw_hdmi0_in: endpoint {
+ remote-endpoint = <&du_out_hdmi0>;
+ };
};
port@1 {
reg = <1>;
};
port@2 {
+ /* HDMI sound */
reg = <2>;
};
};
@@ -1820,6 +1830,7 @@
port@1 {
reg = <1>;
du_out_hdmi0: endpoint {
+ remote-endpoint = <&dw_hdmi0_in>;
};
};
port@2 {
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 09/17] dt-bindings: display: renesas,lvds: Document r8a774e1 bindings
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (7 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 08/17] arm64: dts: renesas: r8a774e1: Populate HDMI encoder node Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 10/17] drm: rcar-du: lvds: Add support for R8A774E1 SoC Lad Prabhakar
` (8 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1715 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 45d6ec79dd42258ada43fedf3bb00c04ae7c17eb upstream.
Document the RZ/G2H (R8A774E1) LVDS bindings.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[PL: Patched text version of bindings file]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../devicetree/bindings/display/bridge/renesas,lvds.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
index 10e2e8e9eb20..f60a10e649eb 100644
--- a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
@@ -10,6 +10,7 @@ Required properties:
- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
- "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders
- "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
+ - "renesas,r8a774e1-lvds" for R8A774E1 (RZ/G2H) compatible LVDS encoders
- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
- "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 10/17] drm: rcar-du: lvds: Add support for R8A774E1 SoC
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (8 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 09/17] dt-bindings: display: renesas,lvds: Document r8a774e1 bindings Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 11/17] arm64: dts: renesas: r8a774e1: Add LVDS device node Lad Prabhakar
` (7 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1603 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 6d981d276110c7d6e866179db4bb1c6cbfcd1819 upstream.
The LVDS encoder on RZ/G2H (R8A774E1) SoC is identical to R-Car Gen3 so
just reuse the rcar_lvds_gen3_info structure to hookup R8A774E1 to LVDS
encoder driver.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[PL: Manually applied changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/gpu/drm/rcar-du/rcar_lvds.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
index e4d0bd043613..fe39b54975b0 100644
--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
+++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
@@ -953,6 +953,7 @@ static const struct of_device_id rcar_lvds_of_table[] = {
{ .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info },
{ .compatible = "renesas,r8a774b1-lvds", .data = &rcar_lvds_gen3_info },
{ .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
+ { .compatible = "renesas,r8a774e1-lvds", .data = &rcar_lvds_gen3_info },
{ .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
{ .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
{ .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 11/17] arm64: dts: renesas: r8a774e1: Add LVDS device node
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (9 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 10/17] drm: rcar-du: lvds: Add support for R8A774E1 SoC Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 12/17] arm64: dts: renesas: r8a774e1-hihope-rzg2h: Setup DU clocks Lad Prabhakar
` (6 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1678 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 112441c24bcdf806335ae0f52e1b4107c6a962ec upstream.
Add the LVDS device node to R8A774E1 to SoC dtsi and connect it with
the DU node.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200812140217.24251-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 27 +++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 8ee028207ce7..b6e491954c9a 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1836,6 +1836,33 @@
port@2 {
reg = <2>;
du_out_lvds0: endpoint {
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+ };
+ };
+
+ lvds0: lvds@feb90000 {
+ compatible = "renesas,r8a774e1-lvds";
+ reg = <0 0xfeb90000 0 0x14>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 727>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
};
};
};
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 12/17] arm64: dts: renesas: r8a774e1-hihope-rzg2h: Setup DU clocks
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (10 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 11/17] arm64: dts: renesas: r8a774e1: Add LVDS device node Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 13/17] dt-bindings: pwm: renesas,pwm-rcar: Add r8a774e1 support Lad Prabhakar
` (5 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1196 bytes --]
commit 2e23a1db4840e6adf4072802d4d91edf4a375b90 upstream.
Setup up the required clocks for the DU to be functional.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200812140217.24251-10-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts
index cdbe527e9340..12f9242e263b 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts
@@ -24,3 +24,14 @@
reg = <0x5 0x00000000 0x0 0x80000000>;
};
};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 721>,
+ <&versaclock5 1>,
+ <&x302_clk>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 13/17] dt-bindings: pwm: renesas,pwm-rcar: Add r8a774e1 support
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (11 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 12/17] arm64: dts: renesas: r8a774e1-hihope-rzg2h: Setup DU clocks Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 14/17] arm64: dts: renesas: r8a774e1: Add PWM device nodes Lad Prabhakar
` (4 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1482 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 0142ee3f2e88ef894427e926b3c8ad7c95964b01 upstream.
Document RZ/G2H (R8A774E1) SoC bindings.
No driver change is needed due to the fallback compatible value
"renesas,pwm-rcar".
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
[PL: Patched text version of bindings file]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
index 3627516b0dad..6b8d831f306a 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
+++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
@@ -6,6 +6,7 @@ Required Properties:
- "renesas,pwm-r8a7745": for RZ/G1E
- "renesas,pwm-r8a774a1": for RZ/G2M
- "renesas,pwm-r8a774c0": for RZ/G2E
+ - "renesas,pwm-r8a774e1": for RZ/G2H
- "renesas,pwm-r8a7778": for R-Car M1A
- "renesas,pwm-r8a7779": for R-Car H1
- "renesas,pwm-r8a7790": for R-Car H2
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 14/17] arm64: dts: renesas: r8a774e1: Add PWM device nodes
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (12 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 13/17] dt-bindings: pwm: renesas,pwm-rcar: Add r8a774e1 support Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 15/17] arm64: dts: renesas: Add HiHope RZ/G2H board with idk-1110wr display Lad Prabhakar
` (3 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 3023 bytes --]
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 557e64084abae2a31f494ac51e4cec549a3bf5ae upstream.
This patch adds PWM[0123456] device nodes to the RZ/G2H (a.k.a R8A774E1)
device tree.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200825104455.18000-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 64 ++++++++++++++++++++++-
1 file changed, 63 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index b6e491954c9a..271045556aa0 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1203,11 +1203,73 @@
};
pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
+ };
- /* placeholder */
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
};
scif0: serial@e6e60000 {
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 15/17] arm64: dts: renesas: Add HiHope RZ/G2H board with idk-1110wr display
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (13 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 14/17] arm64: dts: renesas: r8a774e1: Add PWM device nodes Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 16/17] dt-bindings: sound: renesas, rsnd: Document r8a774e1 bindings Lad Prabhakar
` (2 subsequent siblings)
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 2285 bytes --]
commit e9f0fb53ac88c1ccf3728b47c687838b6054f481 upstream.
The HiHope RZ/G2H is advertised as compatible with panel idk-1110wr from
Advantech, however the panel isn't sold alongside the board. New dts,
enabling the lvds node to get the panel to work with HiHope RZ/G2H.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200827181918.30130-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied changes to Makefile]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
.../r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts | 15 +++++++++++++++
2 files changed, 16 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 73cf57a3919b..16d63679f358 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \
r8a774c0-ek874-idk-2121wr.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb
+dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts
new file mode 100644
index 000000000000..3b7339127bc0
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H sub board connected
+ * to an Advantech IDK-1110WR 10.1" LVDS panel
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h-ex.dts"
+#include "hihope-rzg2-ex-lvds.dtsi"
+#include "rzg2-advantech-idk-1110wr-panel.dtsi"
+
+&lvds0 {
+ status = "okay";
+};
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 16/17] dt-bindings: sound: renesas, rsnd: Document r8a774e1 bindings
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (14 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 15/17] arm64: dts: renesas: Add HiHope RZ/G2H board with idk-1110wr display Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 17/17] arm64: dts: renesas: r8a774e1: Add audio support Lad Prabhakar
2020-11-04 2:31 ` [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Nobuhiro Iwamatsu
17 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1297 bytes --]
commit 92e37407811b98a7eb54eb6a6b3d65847a46e0e6 upstream.
Document SoC specific bindings for RZ/G2H (r8a774e1) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594919915-5225-15-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
index a65c97d92008..438e6c19694e 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
@@ -347,6 +347,7 @@ Required properties:
- "renesas,rcar_sound-r8a774a1" (RZ/G2M)
- "renesas,rcar_sound-r8a774b1" (RZ/G2N)
- "renesas,rcar_sound-r8a774c0" (RZ/G2E)
+ - "renesas,rcar_sound-r8a774e1" (RZ/G2H)
- "renesas,rcar_sound-r8a7778" (R-Car M1A)
- "renesas,rcar_sound-r8a7779" (R-Car H1)
- "renesas,rcar_sound-r8a7790" (R-Car H2)
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 17/17] arm64: dts: renesas: r8a774e1: Add audio support
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (15 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 16/17] dt-bindings: sound: renesas, rsnd: Document r8a774e1 bindings Lad Prabhakar
@ 2020-11-03 17:33 ` Lad Prabhakar
2020-11-04 2:25 ` Nobuhiro Iwamatsu
2020-11-04 2:31 ` [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Nobuhiro Iwamatsu
17 siblings, 1 reply; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-03 17:33 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 15864 bytes --]
commit 8183a7938cfec0569d77755af5ce5ff5589f3540 upstream.
Add sound support for the RZ/G2H SoC (a.k.a. R8A774E1).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594919915-5225-16-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied the changes to dtsi]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 478 +++++++++++++++++++++-
1 file changed, 475 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 271045556aa0..9af3ddbe5454 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1435,6 +1435,19 @@
};
rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ /*
+ * #clock-cells is required for audio_clkout0/1/2/3
+ *
+ * clkout : #clock-cells = <0>; <&rcar_sound>;
+ * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
@@ -1442,17 +1455,476 @@
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
- status = "disabled";
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE R8A774E1_CLK_S0D4>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
- /* placeholder */
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssiu {
+ ssiu00: ssiu-0 {
+ dmas = <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx";
+ };
+ ssiu01: ssiu-1 {
+ dmas = <&audma0 0x35>, <&audma1 0x36>;
+ dma-names = "rx", "tx";
+ };
+ ssiu02: ssiu-2 {
+ dmas = <&audma0 0x37>, <&audma1 0x38>;
+ dma-names = "rx", "tx";
+ };
+ ssiu03: ssiu-3 {
+ dmas = <&audma0 0x47>, <&audma1 0x48>;
+ dma-names = "rx", "tx";
+ };
+ ssiu04: ssiu-4 {
+ dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dma-names = "rx", "tx";
+ };
+ ssiu05: ssiu-5 {
+ dmas = <&audma0 0x43>, <&audma1 0x44>;
+ dma-names = "rx", "tx";
+ };
+ ssiu06: ssiu-6 {
+ dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dma-names = "rx", "tx";
+ };
+ ssiu07: ssiu-7 {
+ dmas = <&audma0 0x53>, <&audma1 0x54>;
+ dma-names = "rx", "tx";
+ };
+ ssiu10: ssiu-8 {
+ dmas = <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx";
+ };
+ ssiu11: ssiu-9 {
+ dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu12: ssiu-10 {
+ dmas = <&audma0 0x57>, <&audma1 0x58>;
+ dma-names = "rx", "tx";
+ };
+ ssiu13: ssiu-11 {
+ dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu14: ssiu-12 {
+ dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dma-names = "rx", "tx";
+ };
+ ssiu15: ssiu-13 {
+ dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dma-names = "rx", "tx";
+ };
+ ssiu16: ssiu-14 {
+ dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dma-names = "rx", "tx";
+ };
+ ssiu17: ssiu-15 {
+ dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dma-names = "rx", "tx";
+ };
+ ssiu20: ssiu-16 {
+ dmas = <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx";
+ };
+ ssiu21: ssiu-17 {
+ dmas = <&audma0 0x67>, <&audma1 0x68>;
+ dma-names = "rx", "tx";
+ };
+ ssiu22: ssiu-18 {
+ dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu23: ssiu-19 {
+ dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu24: ssiu-20 {
+ dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dma-names = "rx", "tx";
+ };
+ ssiu25: ssiu-21 {
+ dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dma-names = "rx", "tx";
+ };
+ ssiu26: ssiu-22 {
+ dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dma-names = "rx", "tx";
+ };
+ ssiu27: ssiu-23 {
+ dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dma-names = "rx", "tx";
+ };
+ ssiu30: ssiu-24 {
+ dmas = <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx";
+ };
+ ssiu31: ssiu-25 {
+ dmas = <&audma0 0x21>, <&audma1 0x22>;
+ dma-names = "rx", "tx";
+ };
+ ssiu32: ssiu-26 {
+ dmas = <&audma0 0x23>, <&audma1 0x24>;
+ dma-names = "rx", "tx";
+ };
+ ssiu33: ssiu-27 {
+ dmas = <&audma0 0x25>, <&audma1 0x26>;
+ dma-names = "rx", "tx";
+ };
+ ssiu34: ssiu-28 {
+ dmas = <&audma0 0x27>, <&audma1 0x28>;
+ dma-names = "rx", "tx";
+ };
+ ssiu35: ssiu-29 {
+ dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu36: ssiu-30 {
+ dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu37: ssiu-31 {
+ dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu40: ssiu-32 {
+ dmas = <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx";
+ };
+ ssiu41: ssiu-33 {
+ dmas = <&audma0 0x17>, <&audma1 0x18>;
+ dma-names = "rx", "tx";
+ };
+ ssiu42: ssiu-34 {
+ dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu43: ssiu-35 {
+ dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu44: ssiu-36 {
+ dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu45: ssiu-37 {
+ dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dma-names = "rx", "tx";
+ };
+ ssiu46: ssiu-38 {
+ dmas = <&audma0 0x31>, <&audma1 0x32>;
+ dma-names = "rx", "tx";
+ };
+ ssiu47: ssiu-39 {
+ dmas = <&audma0 0x33>, <&audma1 0x34>;
+ dma-names = "rx", "tx";
+ };
+ ssiu50: ssiu-40 {
+ dmas = <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx";
+ };
+ ssiu60: ssiu-41 {
+ dmas = <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx";
+ };
+ ssiu70: ssiu-42 {
+ dmas = <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx";
+ };
+ ssiu80: ssiu-43 {
+ dmas = <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx";
+ };
+ ssiu90: ssiu-44 {
+ dmas = <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx";
+ };
+ ssiu91: ssiu-45 {
+ dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dma-names = "rx", "tx";
+ };
+ ssiu92: ssiu-46 {
+ dmas = <&audma0 0x81>, <&audma1 0x82>;
+ dma-names = "rx", "tx";
+ };
+ ssiu93: ssiu-47 {
+ dmas = <&audma0 0x83>, <&audma1 0x84>;
+ dma-names = "rx", "tx";
+ };
+ ssiu94: ssiu-48 {
+ dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dma-names = "rx", "tx";
+ };
+ ssiu95: ssiu-49 {
+ dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dma-names = "rx", "tx";
+ };
+ ssiu96: ssiu-50 {
+ dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dma-names = "rx", "tx";
+ };
+ ssiu97: ssiu-51 {
+ dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dma-names = "rx", "tx";
+ };
+ };
rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>;
+ dma-names = "rx", "tx";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>;
+ dma-names = "rx", "tx";
+ };
ssi2: ssi-2 {
- /* placeholder */
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>;
+ dma-names = "rx", "tx";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>;
+ dma-names = "rx", "tx";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>;
+ dma-names = "rx", "tx";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>;
+ dma-names = "rx", "tx";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>;
+ dma-names = "rx", "tx";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>;
+ dma-names = "rx", "tx";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>;
+ dma-names = "rx", "tx";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>;
+ dma-names = "rx", "tx";
};
};
};
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a774e1",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
+ <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
+ <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
+ <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
+ <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
+ <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
+ <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
+ <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a774e1",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
+ <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
+ <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
+ <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
+ <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
+ <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
+ <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
+ <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
+ };
+
xhci0: usb@ee000000 {
reg = <0 0xee000000 0 0xc00>;
status = "disabled";
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [cip-dev] [PATCH 4.19.y-cip 17/17] arm64: dts: renesas: r8a774e1: Add audio support
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 17/17] arm64: dts: renesas: r8a774e1: Add audio support Lad Prabhakar
@ 2020-11-04 2:25 ` Nobuhiro Iwamatsu
2020-11-04 11:00 ` Lad Prabhakar
0 siblings, 1 reply; 25+ messages in thread
From: Nobuhiro Iwamatsu @ 2020-11-04 2:25 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, cip-dev, pavel; +Cc: biju.das.jz
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Hi,
> -----Original Message-----
> From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
> Sent: Wednesday, November 4, 2020 2:34 AM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: [PATCH 4.19.y-cip 17/17] arm64: dts: renesas: r8a774e1: Add audio support
>
> commit 8183a7938cfec0569d77755af5ce5ff5589f3540 upstream.
>
> Add sound support for the RZ/G2H SoC (a.k.a. R8A774E1).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Link: https://lore.kernel.org/r/1594919915-5225-16-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> [PL: Manually applied the changes to dtsi]
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 478 +++++++++++++++++++++-
> 1 file changed, 475 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> index 271045556aa0..9af3ddbe5454 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> @@ -1435,6 +1435,19 @@
> };
>
> rcar_sound: sound@ec500000 {
> + /*
> + * #sound-dai-cells is required
> + *
> + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
> + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
> + */
> + /*
> + * #clock-cells is required for audio_clkout0/1/2/3
> + *
> + * clkout : #clock-cells = <0>; <&rcar_sound>;
> + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
> + */
> + compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
> reg = <0 0xec500000 0 0x1000>, /* SCU */
> <0 0xec5a0000 0 0x100>, /* ADG */
> <0 0xec540000 0 0x1000>, /* SSIU */
> @@ -1442,17 +1455,476 @@
> <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
> reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
>
> - status = "disabled";
> + clocks = <&cpg CPG_MOD 1005>,
> + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
> + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
> + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
> + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
> + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
> + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
> + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
> + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
> + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
> + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
> + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
> + <&audio_clk_a>, <&audio_clk_b>,
There is no definition for audio_clk_b.
The clock will be overwritten by hihope-rev4.dtsi, but I think it needs to be define like audio_clk_a.
Best regards,
Nobuhiro
> + <&audio_clk_c>,
> + <&cpg CPG_CORE R8A774E1_CLK_S0D4>;
> + clock-names = "ssi-all",
> + "ssi.9", "ssi.8", "ssi.7", "ssi.6",
> + "ssi.5", "ssi.4", "ssi.3", "ssi.2",
> + "ssi.1", "ssi.0",
> + "src.9", "src.8", "src.7", "src.6",
> + "src.5", "src.4", "src.3", "src.2",
> + "src.1", "src.0",
> + "mix.1", "mix.0",
> + "ctu.1", "ctu.0",
> + "dvc.0", "dvc.1",
> + "clk_a", "clk_b", "clk_c", "clk_i";
> + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
> + resets = <&cpg 1005>,
> + <&cpg 1006>, <&cpg 1007>,
> + <&cpg 1008>, <&cpg 1009>,
> + <&cpg 1010>, <&cpg 1011>,
> + <&cpg 1012>, <&cpg 1013>,
> + <&cpg 1014>, <&cpg 1015>;
> + reset-names = "ssi-all",
> + "ssi.9", "ssi.8", "ssi.7", "ssi.6",
> + "ssi.5", "ssi.4", "ssi.3", "ssi.2",
> + "ssi.1", "ssi.0";
> + status = "disabled";
> +
> + rcar_sound,dvc {
> + dvc0: dvc-0 {
> + dmas = <&audma1 0xbc>;
> + dma-names = "tx";
> + };
> + dvc1: dvc-1 {
> + dmas = <&audma1 0xbe>;
> + dma-names = "tx";
> + };
> + };
>
> - /* placeholder */
> + rcar_sound,mix {
> + mix0: mix-0 { };
> + mix1: mix-1 { };
> + };
> +
> + rcar_sound,ctu {
> + ctu00: ctu-0 { };
> + ctu01: ctu-1 { };
> + ctu02: ctu-2 { };
> + ctu03: ctu-3 { };
> + ctu10: ctu-4 { };
> + ctu11: ctu-5 { };
> + ctu12: ctu-6 { };
> + ctu13: ctu-7 { };
> + };
> +
> + rcar_sound,src {
> + src0: src-0 {
> + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x85>, <&audma1 0x9a>;
> + dma-names = "rx", "tx";
> + };
> + src1: src-1 {
> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x87>, <&audma1 0x9c>;
> + dma-names = "rx", "tx";
> + };
> + src2: src-2 {
> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x89>, <&audma1 0x9e>;
> + dma-names = "rx", "tx";
> + };
> + src3: src-3 {
> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x8b>, <&audma1 0xa0>;
> + dma-names = "rx", "tx";
> + };
> + src4: src-4 {
> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x8d>, <&audma1 0xb0>;
> + dma-names = "rx", "tx";
> + };
> + src5: src-5 {
> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x8f>, <&audma1 0xb2>;
> + dma-names = "rx", "tx";
> + };
> + src6: src-6 {
> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x91>, <&audma1 0xb4>;
> + dma-names = "rx", "tx";
> + };
> + src7: src-7 {
> + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x93>, <&audma1 0xb6>;
> + dma-names = "rx", "tx";
> + };
> + src8: src-8 {
> + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x95>, <&audma1 0xb8>;
> + dma-names = "rx", "tx";
> + };
> + src9: src-9 {
> + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x97>, <&audma1 0xba>;
> + dma-names = "rx", "tx";
> + };
> + };
> +
> + rcar_sound,ssiu {
> + ssiu00: ssiu-0 {
> + dmas = <&audma0 0x15>, <&audma1 0x16>;
> + dma-names = "rx", "tx";
> + };
> + ssiu01: ssiu-1 {
> + dmas = <&audma0 0x35>, <&audma1 0x36>;
> + dma-names = "rx", "tx";
> + };
> + ssiu02: ssiu-2 {
> + dmas = <&audma0 0x37>, <&audma1 0x38>;
> + dma-names = "rx", "tx";
> + };
> + ssiu03: ssiu-3 {
> + dmas = <&audma0 0x47>, <&audma1 0x48>;
> + dma-names = "rx", "tx";
> + };
> + ssiu04: ssiu-4 {
> + dmas = <&audma0 0x3F>, <&audma1 0x40>;
> + dma-names = "rx", "tx";
> + };
> + ssiu05: ssiu-5 {
> + dmas = <&audma0 0x43>, <&audma1 0x44>;
> + dma-names = "rx", "tx";
> + };
> + ssiu06: ssiu-6 {
> + dmas = <&audma0 0x4F>, <&audma1 0x50>;
> + dma-names = "rx", "tx";
> + };
> + ssiu07: ssiu-7 {
> + dmas = <&audma0 0x53>, <&audma1 0x54>;
> + dma-names = "rx", "tx";
> + };
> + ssiu10: ssiu-8 {
> + dmas = <&audma0 0x49>, <&audma1 0x4a>;
> + dma-names = "rx", "tx";
> + };
> + ssiu11: ssiu-9 {
> + dmas = <&audma0 0x4B>, <&audma1 0x4C>;
> + dma-names = "rx", "tx";
> + };
> + ssiu12: ssiu-10 {
> + dmas = <&audma0 0x57>, <&audma1 0x58>;
> + dma-names = "rx", "tx";
> + };
> + ssiu13: ssiu-11 {
> + dmas = <&audma0 0x59>, <&audma1 0x5A>;
> + dma-names = "rx", "tx";
> + };
> + ssiu14: ssiu-12 {
> + dmas = <&audma0 0x5F>, <&audma1 0x60>;
> + dma-names = "rx", "tx";
> + };
> + ssiu15: ssiu-13 {
> + dmas = <&audma0 0xC3>, <&audma1 0xC4>;
> + dma-names = "rx", "tx";
> + };
> + ssiu16: ssiu-14 {
> + dmas = <&audma0 0xC7>, <&audma1 0xC8>;
> + dma-names = "rx", "tx";
> + };
> + ssiu17: ssiu-15 {
> + dmas = <&audma0 0xCB>, <&audma1 0xCC>;
> + dma-names = "rx", "tx";
> + };
> + ssiu20: ssiu-16 {
> + dmas = <&audma0 0x63>, <&audma1 0x64>;
> + dma-names = "rx", "tx";
> + };
> + ssiu21: ssiu-17 {
> + dmas = <&audma0 0x67>, <&audma1 0x68>;
> + dma-names = "rx", "tx";
> + };
> + ssiu22: ssiu-18 {
> + dmas = <&audma0 0x6B>, <&audma1 0x6C>;
> + dma-names = "rx", "tx";
> + };
> + ssiu23: ssiu-19 {
> + dmas = <&audma0 0x6D>, <&audma1 0x6E>;
> + dma-names = "rx", "tx";
> + };
> + ssiu24: ssiu-20 {
> + dmas = <&audma0 0xCF>, <&audma1 0xCE>;
> + dma-names = "rx", "tx";
> + };
> + ssiu25: ssiu-21 {
> + dmas = <&audma0 0xEB>, <&audma1 0xEC>;
> + dma-names = "rx", "tx";
> + };
> + ssiu26: ssiu-22 {
> + dmas = <&audma0 0xED>, <&audma1 0xEE>;
> + dma-names = "rx", "tx";
> + };
> + ssiu27: ssiu-23 {
> + dmas = <&audma0 0xEF>, <&audma1 0xF0>;
> + dma-names = "rx", "tx";
> + };
> + ssiu30: ssiu-24 {
> + dmas = <&audma0 0x6f>, <&audma1 0x70>;
> + dma-names = "rx", "tx";
> + };
> + ssiu31: ssiu-25 {
> + dmas = <&audma0 0x21>, <&audma1 0x22>;
> + dma-names = "rx", "tx";
> + };
> + ssiu32: ssiu-26 {
> + dmas = <&audma0 0x23>, <&audma1 0x24>;
> + dma-names = "rx", "tx";
> + };
> + ssiu33: ssiu-27 {
> + dmas = <&audma0 0x25>, <&audma1 0x26>;
> + dma-names = "rx", "tx";
> + };
> + ssiu34: ssiu-28 {
> + dmas = <&audma0 0x27>, <&audma1 0x28>;
> + dma-names = "rx", "tx";
> + };
> + ssiu35: ssiu-29 {
> + dmas = <&audma0 0x29>, <&audma1 0x2A>;
> + dma-names = "rx", "tx";
> + };
> + ssiu36: ssiu-30 {
> + dmas = <&audma0 0x2B>, <&audma1 0x2C>;
> + dma-names = "rx", "tx";
> + };
> + ssiu37: ssiu-31 {
> + dmas = <&audma0 0x2D>, <&audma1 0x2E>;
> + dma-names = "rx", "tx";
> + };
> + ssiu40: ssiu-32 {
> + dmas = <&audma0 0x71>, <&audma1 0x72>;
> + dma-names = "rx", "tx";
> + };
> + ssiu41: ssiu-33 {
> + dmas = <&audma0 0x17>, <&audma1 0x18>;
> + dma-names = "rx", "tx";
> + };
> + ssiu42: ssiu-34 {
> + dmas = <&audma0 0x19>, <&audma1 0x1A>;
> + dma-names = "rx", "tx";
> + };
> + ssiu43: ssiu-35 {
> + dmas = <&audma0 0x1B>, <&audma1 0x1C>;
> + dma-names = "rx", "tx";
> + };
> + ssiu44: ssiu-36 {
> + dmas = <&audma0 0x1D>, <&audma1 0x1E>;
> + dma-names = "rx", "tx";
> + };
> + ssiu45: ssiu-37 {
> + dmas = <&audma0 0x1F>, <&audma1 0x20>;
> + dma-names = "rx", "tx";
> + };
> + ssiu46: ssiu-38 {
> + dmas = <&audma0 0x31>, <&audma1 0x32>;
> + dma-names = "rx", "tx";
> + };
> + ssiu47: ssiu-39 {
> + dmas = <&audma0 0x33>, <&audma1 0x34>;
> + dma-names = "rx", "tx";
> + };
> + ssiu50: ssiu-40 {
> + dmas = <&audma0 0x73>, <&audma1 0x74>;
> + dma-names = "rx", "tx";
> + };
> + ssiu60: ssiu-41 {
> + dmas = <&audma0 0x75>, <&audma1 0x76>;
> + dma-names = "rx", "tx";
> + };
> + ssiu70: ssiu-42 {
> + dmas = <&audma0 0x79>, <&audma1 0x7a>;
> + dma-names = "rx", "tx";
> + };
> + ssiu80: ssiu-43 {
> + dmas = <&audma0 0x7b>, <&audma1 0x7c>;
> + dma-names = "rx", "tx";
> + };
> + ssiu90: ssiu-44 {
> + dmas = <&audma0 0x7d>, <&audma1 0x7e>;
> + dma-names = "rx", "tx";
> + };
> + ssiu91: ssiu-45 {
> + dmas = <&audma0 0x7F>, <&audma1 0x80>;
> + dma-names = "rx", "tx";
> + };
> + ssiu92: ssiu-46 {
> + dmas = <&audma0 0x81>, <&audma1 0x82>;
> + dma-names = "rx", "tx";
> + };
> + ssiu93: ssiu-47 {
> + dmas = <&audma0 0x83>, <&audma1 0x84>;
> + dma-names = "rx", "tx";
> + };
> + ssiu94: ssiu-48 {
> + dmas = <&audma0 0xA3>, <&audma1 0xA4>;
> + dma-names = "rx", "tx";
> + };
> + ssiu95: ssiu-49 {
> + dmas = <&audma0 0xA5>, <&audma1 0xA6>;
> + dma-names = "rx", "tx";
> + };
> + ssiu96: ssiu-50 {
> + dmas = <&audma0 0xA7>, <&audma1 0xA8>;
> + dma-names = "rx", "tx";
> + };
> + ssiu97: ssiu-51 {
> + dmas = <&audma0 0xA9>, <&audma1 0xAA>;
> + dma-names = "rx", "tx";
> + };
> + };
>
> rcar_sound,ssi {
> + ssi0: ssi-0 {
> + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x01>, <&audma1 0x02>;
> + dma-names = "rx", "tx";
> + };
> + ssi1: ssi-1 {
> + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x03>, <&audma1 0x04>;
> + dma-names = "rx", "tx";
> + };
> ssi2: ssi-2 {
> - /* placeholder */
> + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x05>, <&audma1 0x06>;
> + dma-names = "rx", "tx";
> + };
> + ssi3: ssi-3 {
> + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x07>, <&audma1 0x08>;
> + dma-names = "rx", "tx";
> + };
> + ssi4: ssi-4 {
> + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x09>, <&audma1 0x0a>;
> + dma-names = "rx", "tx";
> + };
> + ssi5: ssi-5 {
> + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x0b>, <&audma1 0x0c>;
> + dma-names = "rx", "tx";
> + };
> + ssi6: ssi-6 {
> + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x0d>, <&audma1 0x0e>;
> + dma-names = "rx", "tx";
> + };
> + ssi7: ssi-7 {
> + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x0f>, <&audma1 0x10>;
> + dma-names = "rx", "tx";
> + };
> + ssi8: ssi-8 {
> + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x11>, <&audma1 0x12>;
> + dma-names = "rx", "tx";
> + };
> + ssi9: ssi-9 {
> + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&audma0 0x13>, <&audma1 0x14>;
> + dma-names = "rx", "tx";
> };
> };
> };
>
> + audma0: dma-controller@ec700000 {
> + compatible = "renesas,dmac-r8a774e1",
> + "renesas,rcar-dmac";
> + reg = <0 0xec700000 0 0x10000>;
> + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15";
> + clocks = <&cpg CPG_MOD 502>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
> + resets = <&cpg 502>;
> + #dma-cells = <1>;
> + dma-channels = <16>;
> + iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
> + <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
> + <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
> + <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
> + <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
> + <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
> + <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
> + <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
> + };
> +
> + audma1: dma-controller@ec720000 {
> + compatible = "renesas,dmac-r8a774e1",
> + "renesas,rcar-dmac";
> + reg = <0 0xec720000 0 0x10000>;
> + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15";
> + clocks = <&cpg CPG_MOD 501>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
> + resets = <&cpg 501>;
> + #dma-cells = <1>;
> + dma-channels = <16>;
> + iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
> + <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
> + <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
> + <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
> + <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
> + <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
> + <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
> + <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
> + };
> +
> xhci0: usb@ee000000 {
> reg = <0 0xee000000 0 0xc00>;
> status = "disabled";
> --
> 2.17.1
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^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [cip-dev] [PATCH 4.19.y-cip 17/17] arm64: dts: renesas: r8a774e1: Add audio support
2020-11-04 2:25 ` Nobuhiro Iwamatsu
@ 2020-11-04 11:00 ` Lad Prabhakar
0 siblings, 0 replies; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-04 11:00 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, cip-dev, pavel; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 4424 bytes --]
Hi Nobuhiro,
Thank you for the review.
> -----Original Message-----
> From: nobuhiro1.iwamatsu@toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp>
> Sent: 04 November 2020 02:25
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org; pavel@denx.de
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: RE: [PATCH 4.19.y-cip 17/17] arm64: dts: renesas: r8a774e1: Add audio support
>
> Hi,
>
> > -----Original Message-----
> > From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
> > Sent: Wednesday, November 4, 2020 2:34 AM
> > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> > <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
> > Cc: Biju Das <biju.das.jz@bp.renesas.com>
> > Subject: [PATCH 4.19.y-cip 17/17] arm64: dts: renesas: r8a774e1: Add audio support
> >
> > commit 8183a7938cfec0569d77755af5ce5ff5589f3540 upstream.
> >
> > Add sound support for the RZ/G2H SoC (a.k.a. R8A774E1).
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> > Link: https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fr%2F1594919915-5225-16-git-send-email-
> prabhakar.mahadev-lad.rj%40bp.renesas.com&data=04%7C01%7Cprabhakar.mahadev-
> lad.rj%40bp.renesas.com%7C349a7c0b44a24c71d5ce08d88068dd5f%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637400535
> 165761476%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&
> sdata=Kh6RbUFAryKsjio9NKDXhYxtr6Kw6oGW1ZDOKmbBi%2Bs%3D&reserved=0
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > [PL: Manually applied the changes to dtsi]
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 478 +++++++++++++++++++++-
> > 1 file changed, 475 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> > index 271045556aa0..9af3ddbe5454 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> > @@ -1435,6 +1435,19 @@
> > };
> >
> > rcar_sound: sound@ec500000 {
> > + /*
> > + * #sound-dai-cells is required
> > + *
> > + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
> > + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
> > + */
> > + /*
> > + * #clock-cells is required for audio_clkout0/1/2/3
> > + *
> > + * clkout : #clock-cells = <0>; <&rcar_sound>;
> > + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
> > + */
> > + compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
> > reg = <0 0xec500000 0 0x1000>, /* SCU */
> > <0 0xec5a0000 0 0x100>, /* ADG */
> > <0 0xec540000 0 0x1000>, /* SSIU */
> > @@ -1442,17 +1455,476 @@
> > <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
> > reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
> >
> > - status = "disabled";
> > + clocks = <&cpg CPG_MOD 1005>,
> > + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
> > + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
> > + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
> > + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
> > + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
> > + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
> > + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
> > + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
> > + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
> > + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
> > + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> > + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> > + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
> > + <&audio_clk_a>, <&audio_clk_b>,
>
>
> There is no definition for audio_clk_b.
> The clock will be overwritten by hihope-rev4.dtsi, but I think it needs to be define like audio_clk_a.
>
Agreed, I have posted a fix upstream [1] will re-send the patches once it hits -rc.
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20201104105508.21197-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support
2020-11-03 17:33 [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Lad Prabhakar
` (16 preceding siblings ...)
2020-11-03 17:33 ` [cip-dev] [PATCH 4.19.y-cip 17/17] arm64: dts: renesas: r8a774e1: Add audio support Lad Prabhakar
@ 2020-11-04 2:31 ` Nobuhiro Iwamatsu
2020-11-04 8:28 ` Pavel Machek
17 siblings, 1 reply; 25+ messages in thread
From: Nobuhiro Iwamatsu @ 2020-11-04 2:31 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, cip-dev, pavel; +Cc: biju.das.jz
[-- Attachment #1: Type: text/plain, Size: 2883 bytes --]
Hi,
> -----Original Message-----
> From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
> Sent: Wednesday, November 4, 2020 2:33 AM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support
>
> Hi All,
>
> This patch series adds support for following peripheral to Renesas
> RZ/G2H,
> * FCPF, FCPV
> * FDP1
> * PWM
> * DU, HDMI, LVDS
> * Sound
>
> All the patches have been cherry picked from Linux kernel v5.10-rc2.
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (4):
> arm64: dts: renesas: r8a774e1-hihope-rzg2h: Setup DU clocks
> arm64: dts: renesas: Add HiHope RZ/G2H board with idk-1110wr display
> dt-bindings: sound: renesas, rsnd: Document r8a774e1 bindings
> arm64: dts: renesas: r8a774e1: Add audio support
>
> Marian-Cristian Rotariu (13):
> arm64: dts: renesas: r8a774e1: Add FCPF and FCPV instances
> arm64: dts: renesas: r8a774e1: Add VSP instances
> arm64: dts: renesas: r8a774e1: Add FDP1 device nodes
> dt-bindings: display: renesas,du: Document r8a774e1 bindings
> drm: rcar-du: Add support for R8A774E1 SoC
> arm64: dts: renesas: r8a774e1: Populate DU device node
> dt-bindings: display: renesas,dw-hdmi: Add r8a774e1 support
> arm64: dts: renesas: r8a774e1: Populate HDMI encoder node
> dt-bindings: display: renesas,lvds: Document r8a774e1 bindings
> drm: rcar-du: lvds: Add support for R8A774E1 SoC
> arm64: dts: renesas: r8a774e1: Add LVDS device node
> dt-bindings: pwm: renesas,pwm-rcar: Add r8a774e1 support
> arm64: dts: renesas: r8a774e1: Add PWM device nodes
>
> .../display/bridge/renesas,dw-hdmi.txt | 1 +
> .../bindings/display/bridge/renesas,lvds.txt | 1 +
> .../bindings/display/renesas,du.txt | 2 +
> .../bindings/pwm/renesas,pwm-rcar.txt | 1 +
> .../bindings/sound/renesas,rsnd.txt | 1 +
> arch/arm64/boot/dts/renesas/Makefile | 1 +
> .../r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts | 15 +
> .../dts/renesas/r8a774e1-hihope-rzg2h.dts | 11 +
> arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 751 +++++++++++++++++-
> drivers/gpu/drm/rcar-du/rcar_du_drv.c | 30 +
> drivers/gpu/drm/rcar-du/rcar_lvds.c | 1 +
> 11 files changed, 809 insertions(+), 6 deletions(-)
> create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts
>
I reviewed this patch series. I commented to 17/17.
I don't think this issue will affect our reference board, but it should be fixed.
And looks good to me without 17/17.
Best regards,
Nobuhiro
> --
> 2.17.1
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^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support
2020-11-04 2:31 ` [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support Nobuhiro Iwamatsu
@ 2020-11-04 8:28 ` Pavel Machek
2020-11-04 11:04 ` Lad Prabhakar
0 siblings, 1 reply; 25+ messages in thread
From: Pavel Machek @ 2020-11-04 8:28 UTC (permalink / raw)
To: nobuhiro1.iwamatsu; +Cc: prabhakar.mahadev-lad.rj, cip-dev, pavel, biju.das.jz
[-- Attachment #1.1: Type: text/plain, Size: 815 bytes --]
Hi!
> > This patch series adds support for following peripheral to Renesas
> > RZ/G2H,
> > * FCPF, FCPV
> > * FDP1
> > * PWM
> > * DU, HDMI, LVDS
> > * Sound
> >
> > All the patches have been cherry picked from Linux kernel
> > v5.10-rc2.
> > create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts
> >
>
> I reviewed this patch series. I commented to 17/17.
> I don't think this issue will affect our reference board, but it should be fixed.
>
> And looks good to me without 17/17.
I don't see any problems with patches up-to 16, and our testing
passes, so I applied that.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support
2020-11-04 8:28 ` Pavel Machek
@ 2020-11-04 11:04 ` Lad Prabhakar
2020-11-13 11:06 ` Nobuhiro Iwamatsu
0 siblings, 1 reply; 25+ messages in thread
From: Lad Prabhakar @ 2020-11-04 11:04 UTC (permalink / raw)
To: Pavel Machek, nobuhiro1.iwamatsu; +Cc: cip-dev, Biju Das
[-- Attachment #1: Type: text/plain, Size: 1160 bytes --]
Hi Pavel, Nobuhiro,
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 04 November 2020 08:29
> To: nobuhiro1.iwamatsu@toshiba.co.jp
> Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org; pavel@denx.de; Biju Das
> <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support
>
> Hi!
>
> > > This patch series adds support for following peripheral to Renesas
> > > RZ/G2H,
> > > * FCPF, FCPV
> > > * FDP1
> > > * PWM
> > > * DU, HDMI, LVDS
> > > * Sound
> > >
> > > All the patches have been cherry picked from Linux kernel
> > > v5.10-rc2.
>
> > > create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts
> > >
> >
> > I reviewed this patch series. I commented to 17/17.
> > I don't think this issue will affect our reference board, but it should be fixed.
> >
> > And looks good to me without 17/17.
>
> I don't see any problems with patches up-to 16, and our testing
> passes, so I applied that.
>
Thank you.
Cheers,
Prabhakar
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^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support
2020-11-04 11:04 ` Lad Prabhakar
@ 2020-11-13 11:06 ` Nobuhiro Iwamatsu
2020-11-13 18:10 ` Pavel Machek
0 siblings, 1 reply; 25+ messages in thread
From: Nobuhiro Iwamatsu @ 2020-11-13 11:06 UTC (permalink / raw)
To: cip-dev, pavel; +Cc: biju.das.jz
[-- Attachment #1: Type: text/plain, Size: 2132 bytes --]
Hi all,
Sorry, I noticed that the commits in this patch series did not have the signed-off-by tag by CIP kernel maintainers.
I force-pushed with signed-off-by tag. Please note that the commit-hash of git tree will change and you
will not be able to update it with 'git pull'. Please use 'git remote update' or other git command instead of.
Best regards,
Nobuhiro
> -----Original Message-----
> From: cip-dev@lists.cip-project.org [mailto:cip-dev@lists.cip-project.org] On Behalf Of Lad Prabhakar
> Sent: Wednesday, November 4, 2020 8:04 PM
> To: Pavel Machek <pavel@denx.de>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>
> Cc: cip-dev@lists.cip-project.org; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound
> support
>
> Hi Pavel, Nobuhiro,
>
> > -----Original Message-----
> > From: Pavel Machek <pavel@denx.de>
> > Sent: 04 November 2020 08:29
> > To: nobuhiro1.iwamatsu@toshiba.co.jp
> > Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org; pavel@denx.de;
> Biju Das
> > <biju.das.jz@bp.renesas.com>
> > Subject: Re: [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support
> >
> > Hi!
> >
> > > > This patch series adds support for following peripheral to Renesas
> > > > RZ/G2H,
> > > > * FCPF, FCPV
> > > > * FDP1
> > > > * PWM
> > > > * DU, HDMI, LVDS
> > > > * Sound
> > > >
> > > > All the patches have been cherry picked from Linux kernel
> > > > v5.10-rc2.
> >
> > > > create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts
> > > >
> > >
> > > I reviewed this patch series. I commented to 17/17.
> > > I don't think this issue will affect our reference board, but it should be fixed.
> > >
> > > And looks good to me without 17/17.
> >
> > I don't see any problems with patches up-to 16, and our testing
> > passes, so I applied that.
> >
> Thank you.
>
> Cheers,
> Prabhakar
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^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support
2020-11-13 11:06 ` Nobuhiro Iwamatsu
@ 2020-11-13 18:10 ` Pavel Machek
0 siblings, 0 replies; 25+ messages in thread
From: Pavel Machek @ 2020-11-13 18:10 UTC (permalink / raw)
To: nobuhiro1.iwamatsu; +Cc: cip-dev, pavel, biju.das.jz
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Hi!
>
> Sorry, I noticed that the commits in this patch series did not have the signed-off-by tag by CIP kernel maintainers.
> I force-pushed with signed-off-by tag. Please note that the commit-hash of git tree will change and you
> will not be able to update it with 'git pull'. Please use 'git remote update' or other git command instead of.
>
This is my fault; thanks for fixing it up and sorry for the confusion.
Best regards,
Pavel
> Best regards,
> Nobuhiro
>
> > -----Original Message-----
> > From: cip-dev@lists.cip-project.org [mailto:cip-dev@lists.cip-project.org] On Behalf Of Lad Prabhakar
> > Sent: Wednesday, November 4, 2020 8:04 PM
> > To: Pavel Machek <pavel@denx.de>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>
> > Cc: cip-dev@lists.cip-project.org; Biju Das <biju.das.jz@bp.renesas.com>
> > Subject: Re: [cip-dev] [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound
> > support
> >
> > Hi Pavel, Nobuhiro,
> >
> > > -----Original Message-----
> > > From: Pavel Machek <pavel@denx.de>
> > > Sent: 04 November 2020 08:29
> > > To: nobuhiro1.iwamatsu@toshiba.co.jp
> > > Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org; pavel@denx.de;
> > Biju Das
> > > <biju.das.jz@bp.renesas.com>
> > > Subject: Re: [PATCH 4.19.y-cip 00/17] Renesas RZ/G2H add FCP{FV}, VSP, FDP1, DU, HDMI, LVDS, PWM and sound support
> > >
> > > Hi!
> > >
> > > > > This patch series adds support for following peripheral to Renesas
> > > > > RZ/G2H,
> > > > > * FCPF, FCPV
> > > > > * FDP1
> > > > > * PWM
> > > > > * DU, HDMI, LVDS
> > > > > * Sound
> > > > >
> > > > > All the patches have been cherry picked from Linux kernel
> > > > > v5.10-rc2.
> > >
> > > > > create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts
> > > > >
> > > >
> > > > I reviewed this patch series. I commented to 17/17.
> > > > I don't think this issue will affect our reference board, but it should be fixed.
> > > >
> > > > And looks good to me without 17/17.
> > >
> > > I don't see any problems with patches up-to 16, and our testing
> > > passes, so I applied that.
> > >
> > Thank you.
> >
> > Cheers,
> > Prabhakar
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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