From: Christophe Leroy <christophe.leroy@csgroup.eu>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
npiggin@gmail.com
Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH v2 03/43] powerpc/40x: Don't use SPRN_SPRG_SCRATCH0/1 in TLB miss handlers
Date: Tue, 9 Mar 2021 12:09:28 +0000 (UTC) [thread overview]
Message-ID: <d09c387cf0d70bc6ca2a560ac572d9bbaa68793a.1615291471.git.christophe.leroy@csgroup.eu> (raw)
In-Reply-To: <cover.1615291471.git.christophe.leroy@csgroup.eu>
SPRN_SPRG_SCRATCH5 is used to save SPRN_PID.
SPRN_SPRG_SCRATCH6 is already available.
SPRN_PID is only 8 bits. We have r12 that contains CR.
We only need to preserve CR0, so we have space available in r12
to save PID.
Keep PID in r12 and free up SPRN_SPRG_SCRATCH5.
Then In TLB miss handlers, instead of using SPRN_SPRG_SCRATCH0 and
SPRN_SPRG_SCRATCH1, use SPRN_SPRG_SCRATCH5 and SPRN_SPRG_SCRATCH6
to avoid future conflicts with normal exception prologs.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/kernel/head_40x.S | 39 ++++++++++++++++------------------
1 file changed, 18 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index 24724a7dad49..383238a98f77 100644
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -249,13 +249,13 @@ _ENTRY(saved_ksp_limit)
* load TLB entries from the page table if they exist.
*/
START_EXCEPTION(0x1100, DTLBMiss)
- mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
- mtspr SPRN_SPRG_SCRATCH1, r11
+ mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
+ mtspr SPRN_SPRG_SCRATCH6, r11
mtspr SPRN_SPRG_SCRATCH3, r12
mtspr SPRN_SPRG_SCRATCH4, r9
mfcr r12
mfspr r9, SPRN_PID
- mtspr SPRN_SPRG_SCRATCH5, r9
+ rlwimi r12, r9, 0, 0xff
mfspr r10, SPRN_DEAR /* Get faulting address */
/* If we are faulting a kernel address, we have to use the
@@ -316,13 +316,12 @@ _ENTRY(saved_ksp_limit)
/* The bailout. Restore registers to pre-exception conditions
* and call the heavyweights to help us out.
*/
- mfspr r9, SPRN_SPRG_SCRATCH5
- mtspr SPRN_PID, r9
- mtcr r12
+ mtspr SPRN_PID, r12
+ mtcrf 0x80, r12
mfspr r9, SPRN_SPRG_SCRATCH4
mfspr r12, SPRN_SPRG_SCRATCH3
- mfspr r11, SPRN_SPRG_SCRATCH1
- mfspr r10, SPRN_SPRG_SCRATCH0
+ mfspr r11, SPRN_SPRG_SCRATCH6
+ mfspr r10, SPRN_SPRG_SCRATCH5
b DataStorage
/* 0x1200 - Instruction TLB Miss Exception
@@ -330,13 +329,13 @@ _ENTRY(saved_ksp_limit)
* registers and bailout to a different point.
*/
START_EXCEPTION(0x1200, ITLBMiss)
- mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
- mtspr SPRN_SPRG_SCRATCH1, r11
+ mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
+ mtspr SPRN_SPRG_SCRATCH6, r11
mtspr SPRN_SPRG_SCRATCH3, r12
mtspr SPRN_SPRG_SCRATCH4, r9
mfcr r12
mfspr r9, SPRN_PID
- mtspr SPRN_SPRG_SCRATCH5, r9
+ rlwimi r12, r9, 0, 0xff
mfspr r10, SPRN_SRR0 /* Get faulting address */
/* If we are faulting a kernel address, we have to use the
@@ -397,13 +396,12 @@ _ENTRY(saved_ksp_limit)
/* The bailout. Restore registers to pre-exception conditions
* and call the heavyweights to help us out.
*/
- mfspr r9, SPRN_SPRG_SCRATCH5
- mtspr SPRN_PID, r9
- mtcr r12
+ mtspr SPRN_PID, r12
+ mtcrf 0x80, r12
mfspr r9, SPRN_SPRG_SCRATCH4
mfspr r12, SPRN_SPRG_SCRATCH3
- mfspr r11, SPRN_SPRG_SCRATCH1
- mfspr r10, SPRN_SPRG_SCRATCH0
+ mfspr r11, SPRN_SPRG_SCRATCH6
+ mfspr r10, SPRN_SPRG_SCRATCH5
b InstructionAccess
EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_STD)
@@ -543,13 +541,12 @@ finish_tlb_load:
/* Done...restore registers and get out of here.
*/
- mfspr r9, SPRN_SPRG_SCRATCH5
- mtspr SPRN_PID, r9
- mtcr r12
+ mtspr SPRN_PID, r12
+ mtcrf 0x80, r12
mfspr r9, SPRN_SPRG_SCRATCH4
mfspr r12, SPRN_SPRG_SCRATCH3
- mfspr r11, SPRN_SPRG_SCRATCH1
- mfspr r10, SPRN_SPRG_SCRATCH0
+ mfspr r11, SPRN_SPRG_SCRATCH6
+ mfspr r10, SPRN_SPRG_SCRATCH5
rfi /* Should sync shadow TLBs */
b . /* prevent prefetch past rfi */
--
2.25.0
WARNING: multiple messages have this Message-ID (diff)
From: Christophe Leroy <christophe.leroy@csgroup.eu>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
npiggin@gmail.com
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 03/43] powerpc/40x: Don't use SPRN_SPRG_SCRATCH0/1 in TLB miss handlers
Date: Tue, 9 Mar 2021 12:09:28 +0000 (UTC) [thread overview]
Message-ID: <d09c387cf0d70bc6ca2a560ac572d9bbaa68793a.1615291471.git.christophe.leroy@csgroup.eu> (raw)
In-Reply-To: <cover.1615291471.git.christophe.leroy@csgroup.eu>
SPRN_SPRG_SCRATCH5 is used to save SPRN_PID.
SPRN_SPRG_SCRATCH6 is already available.
SPRN_PID is only 8 bits. We have r12 that contains CR.
We only need to preserve CR0, so we have space available in r12
to save PID.
Keep PID in r12 and free up SPRN_SPRG_SCRATCH5.
Then In TLB miss handlers, instead of using SPRN_SPRG_SCRATCH0 and
SPRN_SPRG_SCRATCH1, use SPRN_SPRG_SCRATCH5 and SPRN_SPRG_SCRATCH6
to avoid future conflicts with normal exception prologs.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/kernel/head_40x.S | 39 ++++++++++++++++------------------
1 file changed, 18 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index 24724a7dad49..383238a98f77 100644
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -249,13 +249,13 @@ _ENTRY(saved_ksp_limit)
* load TLB entries from the page table if they exist.
*/
START_EXCEPTION(0x1100, DTLBMiss)
- mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
- mtspr SPRN_SPRG_SCRATCH1, r11
+ mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
+ mtspr SPRN_SPRG_SCRATCH6, r11
mtspr SPRN_SPRG_SCRATCH3, r12
mtspr SPRN_SPRG_SCRATCH4, r9
mfcr r12
mfspr r9, SPRN_PID
- mtspr SPRN_SPRG_SCRATCH5, r9
+ rlwimi r12, r9, 0, 0xff
mfspr r10, SPRN_DEAR /* Get faulting address */
/* If we are faulting a kernel address, we have to use the
@@ -316,13 +316,12 @@ _ENTRY(saved_ksp_limit)
/* The bailout. Restore registers to pre-exception conditions
* and call the heavyweights to help us out.
*/
- mfspr r9, SPRN_SPRG_SCRATCH5
- mtspr SPRN_PID, r9
- mtcr r12
+ mtspr SPRN_PID, r12
+ mtcrf 0x80, r12
mfspr r9, SPRN_SPRG_SCRATCH4
mfspr r12, SPRN_SPRG_SCRATCH3
- mfspr r11, SPRN_SPRG_SCRATCH1
- mfspr r10, SPRN_SPRG_SCRATCH0
+ mfspr r11, SPRN_SPRG_SCRATCH6
+ mfspr r10, SPRN_SPRG_SCRATCH5
b DataStorage
/* 0x1200 - Instruction TLB Miss Exception
@@ -330,13 +329,13 @@ _ENTRY(saved_ksp_limit)
* registers and bailout to a different point.
*/
START_EXCEPTION(0x1200, ITLBMiss)
- mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
- mtspr SPRN_SPRG_SCRATCH1, r11
+ mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
+ mtspr SPRN_SPRG_SCRATCH6, r11
mtspr SPRN_SPRG_SCRATCH3, r12
mtspr SPRN_SPRG_SCRATCH4, r9
mfcr r12
mfspr r9, SPRN_PID
- mtspr SPRN_SPRG_SCRATCH5, r9
+ rlwimi r12, r9, 0, 0xff
mfspr r10, SPRN_SRR0 /* Get faulting address */
/* If we are faulting a kernel address, we have to use the
@@ -397,13 +396,12 @@ _ENTRY(saved_ksp_limit)
/* The bailout. Restore registers to pre-exception conditions
* and call the heavyweights to help us out.
*/
- mfspr r9, SPRN_SPRG_SCRATCH5
- mtspr SPRN_PID, r9
- mtcr r12
+ mtspr SPRN_PID, r12
+ mtcrf 0x80, r12
mfspr r9, SPRN_SPRG_SCRATCH4
mfspr r12, SPRN_SPRG_SCRATCH3
- mfspr r11, SPRN_SPRG_SCRATCH1
- mfspr r10, SPRN_SPRG_SCRATCH0
+ mfspr r11, SPRN_SPRG_SCRATCH6
+ mfspr r10, SPRN_SPRG_SCRATCH5
b InstructionAccess
EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_STD)
@@ -543,13 +541,12 @@ finish_tlb_load:
/* Done...restore registers and get out of here.
*/
- mfspr r9, SPRN_SPRG_SCRATCH5
- mtspr SPRN_PID, r9
- mtcr r12
+ mtspr SPRN_PID, r12
+ mtcrf 0x80, r12
mfspr r9, SPRN_SPRG_SCRATCH4
mfspr r12, SPRN_SPRG_SCRATCH3
- mfspr r11, SPRN_SPRG_SCRATCH1
- mfspr r10, SPRN_SPRG_SCRATCH0
+ mfspr r11, SPRN_SPRG_SCRATCH6
+ mfspr r10, SPRN_SPRG_SCRATCH5
rfi /* Should sync shadow TLBs */
b . /* prevent prefetch past rfi */
--
2.25.0
next prev parent reply other threads:[~2021-03-09 12:10 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-09 12:09 [PATCH v2 00/43] powerpc/32: Switch to interrupt entry/exit in C Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 01/43] powerpc/traps: unrecoverable_exception() is not an interrupt handler Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-10 1:16 ` Nicholas Piggin
2021-03-10 1:16 ` Nicholas Piggin
2021-03-09 12:09 ` [PATCH v2 02/43] powerpc/traps: Declare unrecoverable_exception() as __noreturn Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-10 1:22 ` Nicholas Piggin
2021-03-10 1:22 ` Nicholas Piggin
2021-03-12 8:40 ` Christophe Leroy
2021-03-12 8:40 ` Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy [this message]
2021-03-09 12:09 ` [PATCH v2 03/43] powerpc/40x: Don't use SPRN_SPRG_SCRATCH0/1 in TLB miss handlers Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 04/43] powerpc/40x: Change CRITICAL_EXCEPTION_PROLOG macro to a gas macro Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 05/43] powerpc/40x: Save SRR0/SRR1 and r10/r11 earlier in critical exception Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 06/43] powerpc/40x: Reorder a few instructions in critical exception prolog Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 07/43] powerpc/40x: Prepare for enabling MMU " Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 08/43] powerpc/40x: Prepare normal exception handler for enabling MMU early Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 09/43] powerpc/32: Reconcile interrupts in C Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 10/43] powerpc/32: Entry cpu time accounting " Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 11/43] powerpc/32: Handle bookE debugging in C in exception entry Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 12/43] powerpc/32: Use fast instruction to set MSR RI in exception prolog on 8xx Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 13/43] powerpc/32: Remove ksp_limit Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 14/43] powerpc/32: Always enable data translation in exception prolog Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 15/43] powerpc/32: Tag DAR in EXCEPTION_PROLOG_2 for the 8xx Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 16/43] powerpc/32: Enable instruction translation at the same time as data translation Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 17/43] powerpc/32: Statically initialise first emergency context Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 18/43] powerpc/32: Add vmap_stack_overflow label inside the macro Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 19/43] powerpc/32: Use START_EXCEPTION() as much as possible Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 20/43] powerpc/32: Move exception prolog code into .text once MMU is back on Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 21/43] powerpc/32: Provide a name to exception prolog continuation in virtual mode Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 22/43] powerpc/32: Refactor booke critical registers saving Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 23/43] powerpc/32: Perform normal function call in exception entry Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 24/43] powerpc/32: Always save non volatile registers on " Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 25/43] powerpc/32: Replace ASM exception exit by C exception exit from ppc64 Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-11 13:46 ` Michael Ellerman
2021-03-11 13:46 ` Michael Ellerman
2021-03-11 19:39 ` Christophe Leroy
2021-03-11 19:39 ` Christophe Leroy
2021-03-11 23:26 ` Michael Ellerman
2021-03-11 23:26 ` Michael Ellerman
2021-03-12 8:28 ` Christophe Leroy
2021-03-12 8:28 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 26/43] powerpc/32: Set regs parameter in r3 in transfer_to_handler Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 27/43] powerpc/32: Call bad_page_fault() from do_page_fault() Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 28/43] powerpc/64e: " Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-10 1:29 ` Nicholas Piggin
2021-03-10 1:29 ` Nicholas Piggin
2021-03-12 8:39 ` Christophe Leroy
2021-03-12 8:39 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 29/43] powerpc/32: Save trap number on stack in exception prolog Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 30/43] powerpc/32: Add a prepare_transfer_to_handler macro for exception prologs Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 31/43] powerpc/32: Only restore non volatile registers when required Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 32/43] powerpc/32: Dismantle EXC_XFER_STD/LITE/TEMPLATE Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:09 ` [PATCH v2 33/43] powerpc/32: Remove the xfer parameter in EXCEPTION() macro Christophe Leroy
2021-03-09 12:09 ` Christophe Leroy
2021-03-09 12:10 ` [PATCH v2 34/43] powerpc/32: Refactor saving of volatile registers in exception prologs Christophe Leroy
2021-03-09 12:10 ` Christophe Leroy
2021-03-09 12:10 ` [PATCH v2 35/43] powerpc/32: Save remaining registers in exception prolog Christophe Leroy
2021-03-09 12:10 ` Christophe Leroy
2021-03-09 12:10 ` [PATCH v2 36/43] powerpc/32: Set current->thread.regs in C interrupt entry Christophe Leroy
2021-03-09 12:10 ` Christophe Leroy
2021-03-10 1:33 ` Nicholas Piggin
2021-03-10 1:33 ` Nicholas Piggin
2021-03-11 10:38 ` Christophe Leroy
2021-03-11 10:38 ` Christophe Leroy
2021-03-11 12:38 ` Christophe Leroy
2021-03-11 12:38 ` Christophe Leroy
2021-03-12 1:00 ` Nicholas Piggin
2021-03-12 1:00 ` Nicholas Piggin
2021-03-09 12:10 ` [PATCH v2 37/43] powerpc/32: Return directly from power_save_ppc32_restore() Christophe Leroy
2021-03-09 12:10 ` Christophe Leroy
2021-03-09 12:10 ` [PATCH v2 38/43] powerpc/32: Only use prepare_transfer_to_handler function on book3s/32 and e500 Christophe Leroy
2021-03-09 12:10 ` Christophe Leroy
2021-03-09 12:10 ` [PATCH v2 39/43] powerpc/32s: Move KUEP locking/unlocking in C Christophe Leroy
2021-03-09 12:10 ` Christophe Leroy
2021-03-09 12:10 ` [PATCH v2 40/43] powerpc/64s: Make kuap_check_amr() and kuap_get_and_check_amr() generic Christophe Leroy
2021-03-09 12:10 ` Christophe Leroy
2021-03-10 1:37 ` Nicholas Piggin
2021-03-10 1:37 ` Nicholas Piggin
2021-03-12 8:37 ` Christophe Leroy
2021-03-12 8:37 ` Christophe Leroy
2021-03-09 12:10 ` [PATCH v2 41/43] powerpc/32s: Create C version of kuap save/restore/check helpers Christophe Leroy
2021-03-09 12:10 ` Christophe Leroy
2021-03-09 12:10 ` [PATCH v2 42/43] powerpc/8xx: " Christophe Leroy
2021-03-09 12:10 ` Christophe Leroy
2021-03-09 12:10 ` [PATCH v2 43/43] powerpc/32: Manage KUAP in C Christophe Leroy
2021-03-09 12:10 ` Christophe Leroy
2021-03-14 10:01 ` [PATCH v2 00/43] powerpc/32: Switch to interrupt entry/exit " Michael Ellerman
2021-03-14 10:01 ` Michael Ellerman
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