From: Thomas Zimmermann <tzimmermann@suse.de> To: Jocelyn Falempe <jfalempe@redhat.com>, dri-devel@lists.freedesktop.org, airlied@redhat.com Cc: lyude@redhat.com, michel@daenzer.net, stable@vger.kernel.org Subject: Re: [PATCH] drm/mgag200: Fix PLL setup for G200_SE_A rev >=4 Date: Thu, 13 Oct 2022 11:05:19 +0200 [thread overview] Message-ID: <db634341-da68-e8a6-1143-445f17262c63@suse.de> (raw) In-Reply-To: <20221013082901.471417-1-jfalempe@redhat.com> [-- Attachment #1.1: Type: text/plain, Size: 1961 bytes --] Hi Am 13.10.22 um 10:29 schrieb Jocelyn Falempe: > For G200_SE_A, PLL M setting is wrong, which leads to blank screen, > or "signal out of range" on VGA display. > previous code had "m |= 0x80" which was changed to > m |= ((pixpllcn & BIT(8)) >> 1); > > Tested on G200_SE_A rev 42 > > This line of code was moved to another file with > commit 85397f6bc4ff ("drm/mgag200: Initialize each model in separate > function") but can be easily backported before this commit. > > Fixes: 2dd040946ecf ("drm/mgag200: Store values (not bits) in struct mgag200_pll_values") > Cc: stable@vger.kernel.org > Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com> > --- > drivers/gpu/drm/mgag200/mgag200_g200se.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mgag200/mgag200_g200se.c b/drivers/gpu/drm/mgag200/mgag200_g200se.c > index be389ed91cbd..4ec035029b8b 100644 > --- a/drivers/gpu/drm/mgag200/mgag200_g200se.c > +++ b/drivers/gpu/drm/mgag200/mgag200_g200se.c > @@ -284,7 +284,7 @@ static void mgag200_g200se_04_pixpllc_atomic_update(struct drm_crtc *crtc, > pixpllcp = pixpllc->p - 1; > pixpllcs = pixpllc->s; > > - xpixpllcm = pixpllcm | ((pixpllcn & BIT(8)) >> 1); > + xpixpllcm = pixpllcm | BIT(7); Thanks for figuring this out. G200SE apparently is special compared to the other models. The old MGA docs only list this bit as <reserved>. Really makes me wonder why this is different. Please write it as BIT(7) | pixpllcm so that bit settings are ordered MSB-to-LSB and include a one-line comment that says that G200SE needs to set this bit unconditionally. Best regards Thomas > xpixpllcn = pixpllcn; > xpixpllcp = (pixpllcs << 3) | pixpllcp; > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Ivo Totev [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 840 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Zimmermann <tzimmermann@suse.de> To: Jocelyn Falempe <jfalempe@redhat.com>, dri-devel@lists.freedesktop.org, airlied@redhat.com Cc: michel@daenzer.net, stable@vger.kernel.org Subject: Re: [PATCH] drm/mgag200: Fix PLL setup for G200_SE_A rev >=4 Date: Thu, 13 Oct 2022 11:05:19 +0200 [thread overview] Message-ID: <db634341-da68-e8a6-1143-445f17262c63@suse.de> (raw) In-Reply-To: <20221013082901.471417-1-jfalempe@redhat.com> [-- Attachment #1.1: Type: text/plain, Size: 1961 bytes --] Hi Am 13.10.22 um 10:29 schrieb Jocelyn Falempe: > For G200_SE_A, PLL M setting is wrong, which leads to blank screen, > or "signal out of range" on VGA display. > previous code had "m |= 0x80" which was changed to > m |= ((pixpllcn & BIT(8)) >> 1); > > Tested on G200_SE_A rev 42 > > This line of code was moved to another file with > commit 85397f6bc4ff ("drm/mgag200: Initialize each model in separate > function") but can be easily backported before this commit. > > Fixes: 2dd040946ecf ("drm/mgag200: Store values (not bits) in struct mgag200_pll_values") > Cc: stable@vger.kernel.org > Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com> > --- > drivers/gpu/drm/mgag200/mgag200_g200se.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mgag200/mgag200_g200se.c b/drivers/gpu/drm/mgag200/mgag200_g200se.c > index be389ed91cbd..4ec035029b8b 100644 > --- a/drivers/gpu/drm/mgag200/mgag200_g200se.c > +++ b/drivers/gpu/drm/mgag200/mgag200_g200se.c > @@ -284,7 +284,7 @@ static void mgag200_g200se_04_pixpllc_atomic_update(struct drm_crtc *crtc, > pixpllcp = pixpllc->p - 1; > pixpllcs = pixpllc->s; > > - xpixpllcm = pixpllcm | ((pixpllcn & BIT(8)) >> 1); > + xpixpllcm = pixpllcm | BIT(7); Thanks for figuring this out. G200SE apparently is special compared to the other models. The old MGA docs only list this bit as <reserved>. Really makes me wonder why this is different. Please write it as BIT(7) | pixpllcm so that bit settings are ordered MSB-to-LSB and include a one-line comment that says that G200SE needs to set this bit unconditionally. Best regards Thomas > xpixpllcn = pixpllcn; > xpixpllcp = (pixpllcs << 3) | pixpllcp; > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Ivo Totev [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 840 bytes --]
next prev parent reply other threads:[~2022-10-13 9:05 UTC|newest] Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-10-13 8:29 [PATCH] drm/mgag200: Fix PLL setup for G200_SE_A rev >=4 Jocelyn Falempe 2022-10-13 8:29 ` Jocelyn Falempe 2022-10-13 9:05 ` Thomas Zimmermann [this message] 2022-10-13 9:05 ` Thomas Zimmermann 2022-10-13 9:37 ` Jocelyn Falempe 2022-10-13 9:37 ` Jocelyn Falempe 2022-10-13 10:36 ` Ville Syrjälä 2022-10-13 10:36 ` Ville Syrjälä 2022-10-13 13:18 ` Jocelyn Falempe 2023-01-04 14:36 FAILED: patch "[PATCH] drm/mgag200: Fix PLL setup for G200_SE_A rev >=4" failed to apply to 6.0-stable tree gregkh 2023-01-04 16:27 ` [PATCH] drm/mgag200: Fix PLL setup for G200_SE_A rev >=4 Jocelyn Falempe 2023-01-10 17:30 ` Greg KH
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