* [PATCH v3 0/6] drm/rockchip: fixes and new features
@ 2015-07-21 8:20 Mark Yao
2015-07-21 8:20 ` [PATCH v3 1/6] drm/rockchip: vop: Fix virtual stride calculation Mark Yao
` (6 more replies)
0 siblings, 7 replies; 12+ messages in thread
From: Mark Yao @ 2015-07-21 8:20 UTC (permalink / raw)
To: dri-devel
Cc: zwl, linux-kernel, tfiga, linux-rockchip, xw, dkm, sandy.huang,
linux-arm-kernel
This series patches are used for yuv image overlay display.
Rockchip vop support NV11, NV16, NV24 yuv format,
and can scale the image scale 1/8 to 8.
Changes in v3:
- make code more readable
- fix some bugs
Changes in v2:
- Uv buffer not support odd offset, align it.
- Fix error display when move yuv image.
- Fix scale dest info.
Mark Yao (6):
drm/rockchip: vop: Fix virtual stride calculation
drm/rockchip: vop: Fix window dest start point
drm/rockchip: vop: Add yuv plane support
drm/rockchip: vop: Default enable win2/3 area0 bit
drm/rockchip: vop: restore vop registers when resume
drm/rockchip: vop: support plane scale
--
1.7.9.5
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v3 1/6] drm/rockchip: vop: Fix virtual stride calculation 2015-07-21 8:20 [PATCH v3 0/6] drm/rockchip: fixes and new features Mark Yao @ 2015-07-21 8:20 ` Mark Yao 2015-07-21 8:20 ` [PATCH v3 2/6] drm/rockchip: vop: Fix window dest start point Mark Yao ` (5 subsequent siblings) 6 siblings, 0 replies; 12+ messages in thread From: Mark Yao @ 2015-07-21 8:20 UTC (permalink / raw) To: dri-devel Cc: zwl, linux-kernel, tfiga, linux-rockchip, xw, dkm, sandy.huang, linux-arm-kernel vir_stride need number words of the virtual width, and fb->pitches save bytes_per_pixel, so just div 4 switch to stride. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- Changes in v3: Adviced by Tomasz Figa - use more suitable tile for this patch. Changes in v2: None drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 4557f33..3558acb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -644,7 +644,7 @@ static int vop_update_plane_event(struct drm_plane *plane, offset += (src.y1 >> 16) * fb->pitches[0]; yrgb_mst = rk_obj->dma_addr + offset; - y_vir_stride = fb->pitches[0] / (fb->bits_per_pixel >> 3); + y_vir_stride = fb->pitches[0] >> 2; /* * If this plane update changes the plane's framebuffer, (or more -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 2/6] drm/rockchip: vop: Fix window dest start point 2015-07-21 8:20 [PATCH v3 0/6] drm/rockchip: fixes and new features Mark Yao 2015-07-21 8:20 ` [PATCH v3 1/6] drm/rockchip: vop: Fix virtual stride calculation Mark Yao @ 2015-07-21 8:20 ` Mark Yao 2015-07-21 8:20 ` [PATCH v3 3/6] drm/rockchip: vop: Add yuv plane support Mark Yao ` (4 subsequent siblings) 6 siblings, 0 replies; 12+ messages in thread From: Mark Yao @ 2015-07-21 8:20 UTC (permalink / raw) To: dri-devel Cc: zwl, linux-kernel, tfiga, linux-rockchip, xw, dkm, sandy.huang, linux-arm-kernel Dest start point use crtc_x/y is wrong, crtc_x/y is not equal to dest.x1/y1 at plane scale. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 3558acb..c7e0283 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -634,11 +634,9 @@ static int vop_update_plane_event(struct drm_plane *plane, actual_w = (src.x2 - src.x1) >> 16; actual_h = (src.y2 - src.y1) >> 16; - crtc_x = max(0, crtc_x); - crtc_y = max(0, crtc_y); - dsp_stx = crtc_x + crtc->mode.htotal - crtc->mode.hsync_start; - dsp_sty = crtc_y + crtc->mode.vtotal - crtc->mode.vsync_start; + dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start; + dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start; offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3); offset += (src.y1 >> 16) * fb->pitches[0]; -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 3/6] drm/rockchip: vop: Add yuv plane support 2015-07-21 8:20 [PATCH v3 0/6] drm/rockchip: fixes and new features Mark Yao 2015-07-21 8:20 ` [PATCH v3 1/6] drm/rockchip: vop: Fix virtual stride calculation Mark Yao 2015-07-21 8:20 ` [PATCH v3 2/6] drm/rockchip: vop: Fix window dest start point Mark Yao @ 2015-07-21 8:20 ` Mark Yao 2015-07-22 21:51 ` Heiko Stübner 2015-07-21 8:25 ` [PATCH v3 4/6] drm/rockchip: vop: Default enable win2/3 area0 bit Mark Yao ` (3 subsequent siblings) 6 siblings, 1 reply; 12+ messages in thread From: Mark Yao @ 2015-07-21 8:20 UTC (permalink / raw) To: dri-devel Cc: zwl, linux-kernel, tfiga, linux-rockchip, xw, dkm, sandy.huang, linux-arm-kernel vop support yuv with NV12, NV16 and NV24, only 2 plane yuv. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- Changes in v3: Adviced by Tomasz Figa - separate dest calculate to another patch - fix src x1,x2 when do align, and remove unnecessary src.y1 align. Changes in v2: - Uv buffer not support odd offset, align it. - Fix error display when move yuv image. drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 56 ++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index c7e0283..47ce943 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -373,6 +373,18 @@ static enum vop_data_format vop_convert_format(uint32_t format) } } +static bool is_yuv_support(uint32_t format) +{ + switch (format) { + case DRM_FORMAT_NV12: + case DRM_FORMAT_NV16: + case DRM_FORMAT_NV24: + return true; + default: + return false; + } +} + static bool is_alpha_support(uint32_t format) { switch (format) { @@ -577,16 +589,21 @@ static int vop_update_plane_event(struct drm_plane *plane, struct vop *vop = to_vop(crtc); struct drm_gem_object *obj; struct rockchip_gem_object *rk_obj; + struct drm_gem_object *uv_obj; + struct rockchip_gem_object *rk_uv_obj; unsigned long offset; unsigned int actual_w; unsigned int actual_h; unsigned int dsp_stx; unsigned int dsp_sty; unsigned int y_vir_stride; + unsigned int uv_vir_stride = 0; dma_addr_t yrgb_mst; + dma_addr_t uv_mst = 0; enum vop_data_format format; uint32_t val; bool is_alpha; + bool is_yuv; bool visible; int ret; struct drm_rect dest = { @@ -620,6 +637,8 @@ static int vop_update_plane_event(struct drm_plane *plane, return 0; is_alpha = is_alpha_support(fb->pixel_format); + is_yuv = is_yuv_support(fb->pixel_format); + format = vop_convert_format(fb->pixel_format); if (format < 0) return format; @@ -632,18 +651,47 @@ static int vop_update_plane_event(struct drm_plane *plane, rk_obj = to_rockchip_obj(obj); + if (is_yuv) { + /* + * Src.x1 can be odd when do clip, but yuv plane start point + * need align with 2 pixel. + */ + val = (src.x1 >> 16) % 2; + src.x1 += val << 16; + src.x2 += val << 16; + } + actual_w = (src.x2 - src.x1) >> 16; actual_h = (src.y2 - src.y1) >> 16; dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start; dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start; - offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3); + offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); offset += (src.y1 >> 16) * fb->pitches[0]; - yrgb_mst = rk_obj->dma_addr + offset; + yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; y_vir_stride = fb->pitches[0] >> 2; + if (is_yuv) { + int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); + int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); + int bpp = drm_format_plane_cpp(fb->pixel_format, 1); + + uv_obj = rockchip_fb_get_gem_obj(fb, 1); + if (!uv_obj) { + DRM_ERROR("fail to get uv object from framebuffer\n"); + return -EINVAL; + } + rk_uv_obj = to_rockchip_obj(uv_obj); + uv_vir_stride = fb->pitches[1] >> 2; + + offset = (src.x1 >> 16) * bpp / hsub; + offset += (src.y1 >> 16) * fb->pitches[1] / vsub; + + uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1]; + } + /* * If this plane update changes the plane's framebuffer, (or more * precisely, if this update has a different framebuffer than the last @@ -679,6 +727,10 @@ static int vop_update_plane_event(struct drm_plane *plane, VOP_WIN_SET(vop, win, format, format); VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride); VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst); + if (is_yuv) { + VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride); + VOP_WIN_SET(vop, win, uv_mst, uv_mst); + } val = (actual_h - 1) << 16; val |= (actual_w - 1) & 0xffff; VOP_WIN_SET(vop, win, act_info, val); -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 3/6] drm/rockchip: vop: Add yuv plane support 2015-07-21 8:20 ` [PATCH v3 3/6] drm/rockchip: vop: Add yuv plane support Mark Yao @ 2015-07-22 21:51 ` Heiko Stübner 2015-07-23 2:01 ` Mark yao 0 siblings, 1 reply; 12+ messages in thread From: Heiko Stübner @ 2015-07-22 21:51 UTC (permalink / raw) To: Mark Yao Cc: zwl, linux-kernel, tfiga, linux-rockchip, dri-devel, xw, dkm, sandy.huang, linux-arm-kernel Am Dienstag, 21. Juli 2015, 16:20:04 schrieb Mark Yao: > vop support yuv with NV12, NV16 and NV24, only 2 plane yuv. > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > --- > Changes in v3: > Adviced by Tomasz Figa > - separate dest calculate to another patch > - fix src x1,x2 when do align, and remove unnecessary src.y1 align. > > Changes in v2: > - Uv buffer not support odd offset, align it. > - Fix error display when move yuv image. > > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 56 > ++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 2 > deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index c7e0283..47ce943 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > @@ -373,6 +373,18 @@ static enum vop_data_format vop_convert_format(uint32_t > format) } > } > > +static bool is_yuv_support(uint32_t format) > +{ > + switch (format) { > + case DRM_FORMAT_NV12: > + case DRM_FORMAT_NV16: > + case DRM_FORMAT_NV24: > + return true; > + default: > + return false; > + } > +} > + > static bool is_alpha_support(uint32_t format) > { > switch (format) { > @@ -577,16 +589,21 @@ static int vop_update_plane_event(struct drm_plane does not apply to what's in mainline, as this patch seems to ignore 85a359f25388 ("drm/rockchip: Add BGR formats to VOP") from Tomasz > *plane, struct vop *vop = to_vop(crtc); > struct drm_gem_object *obj; > struct rockchip_gem_object *rk_obj; > + struct drm_gem_object *uv_obj; > + struct rockchip_gem_object *rk_uv_obj; > unsigned long offset; > unsigned int actual_w; > unsigned int actual_h; > unsigned int dsp_stx; > unsigned int dsp_sty; > unsigned int y_vir_stride; > + unsigned int uv_vir_stride = 0; > dma_addr_t yrgb_mst; > + dma_addr_t uv_mst = 0; > enum vop_data_format format; > uint32_t val; > bool is_alpha; > + bool is_yuv; > bool visible; > int ret; > struct drm_rect dest = { > @@ -620,6 +637,8 @@ static int vop_update_plane_event(struct drm_plane > *plane, return 0; > > is_alpha = is_alpha_support(fb->pixel_format); > + is_yuv = is_yuv_support(fb->pixel_format); > + > format = vop_convert_format(fb->pixel_format); > if (format < 0) > return format; same as above Heiko _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 3/6] drm/rockchip: vop: Add yuv plane support 2015-07-22 21:51 ` Heiko Stübner @ 2015-07-23 2:01 ` Mark yao 0 siblings, 0 replies; 12+ messages in thread From: Mark yao @ 2015-07-23 2:01 UTC (permalink / raw) To: Heiko Stübner Cc: zwl, linux-kernel, tfiga, linux-rockchip, dri-devel, xw, dkm, sandy.huang, linux-arm-kernel On 2015年07月23日 05:51, Heiko Stübner wrote: > Am Dienstag, 21. Juli 2015, 16:20:04 schrieb Mark Yao: >> vop support yuv with NV12, NV16 and NV24, only 2 plane yuv. >> >> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> >> --- >> Changes in v3: >> Adviced by Tomasz Figa >> - separate dest calculate to another patch >> - fix src x1,x2 when do align, and remove unnecessary src.y1 align. >> >> Changes in v2: >> - Uv buffer not support odd offset, align it. >> - Fix error display when move yuv image. >> >> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 56 >> ++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 2 >> deletions(-) >> >> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c >> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index c7e0283..47ce943 100644 >> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c >> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c >> @@ -373,6 +373,18 @@ static enum vop_data_format vop_convert_format(uint32_t >> format) } >> } >> >> +static bool is_yuv_support(uint32_t format) >> +{ >> + switch (format) { >> + case DRM_FORMAT_NV12: >> + case DRM_FORMAT_NV16: >> + case DRM_FORMAT_NV24: >> + return true; >> + default: >> + return false; >> + } >> +} >> + >> static bool is_alpha_support(uint32_t format) >> { >> switch (format) { >> @@ -577,16 +589,21 @@ static int vop_update_plane_event(struct drm_plane > > does not apply to what's in mainline, as this patch seems to ignore > 85a359f25388 ("drm/rockchip: Add BGR formats to VOP") > from Tomasz > Hmm, I found the patch ("drm/rockchip: Add BGR formats to VOP") is on the drm-fixes branch, so I didn't resend the patch. Ok, I will rebase these patches top of the "Add BGR formats to VOP". >> *plane, struct vop *vop = to_vop(crtc); >> struct drm_gem_object *obj; >> struct rockchip_gem_object *rk_obj; >> + struct drm_gem_object *uv_obj; >> + struct rockchip_gem_object *rk_uv_obj; >> unsigned long offset; >> unsigned int actual_w; >> unsigned int actual_h; >> unsigned int dsp_stx; >> unsigned int dsp_sty; >> unsigned int y_vir_stride; >> + unsigned int uv_vir_stride = 0; >> dma_addr_t yrgb_mst; >> + dma_addr_t uv_mst = 0; >> enum vop_data_format format; >> uint32_t val; >> bool is_alpha; >> + bool is_yuv; >> bool visible; >> int ret; >> struct drm_rect dest = { >> @@ -620,6 +637,8 @@ static int vop_update_plane_event(struct drm_plane >> *plane, return 0; >> >> is_alpha = is_alpha_support(fb->pixel_format); >> + is_yuv = is_yuv_support(fb->pixel_format); >> + >> format = vop_convert_format(fb->pixel_format); >> if (format < 0) >> return format; > same as above > > > Heiko > > > -- Ｍark _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 4/6] drm/rockchip: vop: Default enable win2/3 area0 bit 2015-07-21 8:20 [PATCH v3 0/6] drm/rockchip: fixes and new features Mark Yao ` (2 preceding siblings ...) 2015-07-21 8:20 ` [PATCH v3 3/6] drm/rockchip: vop: Add yuv plane support Mark Yao @ 2015-07-21 8:25 ` Mark Yao 2015-07-22 21:50 ` Heiko Stübner 2015-07-21 8:27 ` [PATCH v3 5/6] drm/rockchip: vop: restore vop registers when resume Mark Yao ` (2 subsequent siblings) 6 siblings, 1 reply; 12+ messages in thread From: Mark Yao @ 2015-07-21 8:25 UTC (permalink / raw) To: dri-devel Cc: zwl, linux-kernel, tfiga, linux-rockchip, xw, dkm, sandy.huang, linux-arm-kernel Win2/3 support multiple area function, but we haven't found a suitable way to use it yet, so let's just use them as other windows with only area 0 enabled. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- Changes in v3: Adviced by Tomasz Figa - fix patch comments. Changes in v2: None drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 47ce943..e08f318 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -276,6 +276,12 @@ static const struct vop_reg_data vop_init_reg_table[] = { {DSP_CTRL0, 0x00000000}, {WIN0_CTRL0, 0x00000080}, {WIN1_CTRL0, 0x00000080}, + /* TODO: Win2/3 support multiple area function, but we haven't found + * a suitable way to use it yet, so let's just use them as other windows + * with only area 0 enabled. + */ + {WIN2_CTRL0, 0x00000010}, + {WIN3_CTRL0, 0x00000010}, }; /* -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 4/6] drm/rockchip: vop: Default enable win2/3 area0 bit 2015-07-21 8:25 ` [PATCH v3 4/6] drm/rockchip: vop: Default enable win2/3 area0 bit Mark Yao @ 2015-07-22 21:50 ` Heiko Stübner 0 siblings, 0 replies; 12+ messages in thread From: Heiko Stübner @ 2015-07-22 21:50 UTC (permalink / raw) To: Mark Yao Cc: zwl, linux-kernel, tfiga, linux-rockchip, dri-devel, xw, dkm, sandy.huang, linux-arm-kernel Am Dienstag, 21. Juli 2015, 16:25:40 schrieb Mark Yao: > Win2/3 support multiple area function, but we haven't found > a suitable way to use it yet, so let's just use them as other windows > with only area 0 enabled. > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> this could go as fix into 4.2 please. With what is currently in 4.2-rc3 I'm loosing the mouse cursor in my xf86- armsoc xserver [0]. Likely due to 0915da7dd75f ("drm/rockchip: vop: remove hardware cursor window"). The xserver then selects a window for the cursor itself, which seems to be one of the currently disabled ones. This patch fixes this and gives me back my cursor :-) Heiko [0] https://github.com/mmind/xf86-video-armsoc/tree/devel/rockchip > --- > Changes in v3: > Adviced by Tomasz Figa > - fix patch comments. > Changes in v2: None > > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 47ce943..e08f318 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > @@ -276,6 +276,12 @@ static const struct vop_reg_data vop_init_reg_table[] = > { {DSP_CTRL0, 0x00000000}, > {WIN0_CTRL0, 0x00000080}, > {WIN1_CTRL0, 0x00000080}, > + /* TODO: Win2/3 support multiple area function, but we haven't found > + * a suitable way to use it yet, so let's just use them as other windows > + * with only area 0 enabled. > + */ > + {WIN2_CTRL0, 0x00000010}, > + {WIN3_CTRL0, 0x00000010}, > }; > > /* _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 5/6] drm/rockchip: vop: restore vop registers when resume 2015-07-21 8:20 [PATCH v3 0/6] drm/rockchip: fixes and new features Mark Yao ` (3 preceding siblings ...) 2015-07-21 8:25 ` [PATCH v3 4/6] drm/rockchip: vop: Default enable win2/3 area0 bit Mark Yao @ 2015-07-21 8:27 ` Mark Yao 2015-07-21 8:28 ` [PATCH v3 6/6] drm/rockchip: vop: support plane scale Mark Yao 2015-07-22 21:55 ` [PATCH v3 0/6] drm/rockchip: fixes and new features Heiko Stübner 6 siblings, 0 replies; 12+ messages in thread From: Mark Yao @ 2015-07-21 8:27 UTC (permalink / raw) To: dri-devel Cc: zwl, linux-kernel, tfiga, linux-rockchip, xw, dkm, sandy.huang, linux-arm-kernel The registers will be reset to default values when whole power domain off, so restore registers from regsbak. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index e08f318..4dfad065 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -475,6 +475,7 @@ static void vop_enable(struct drm_crtc *crtc) goto err_disable_aclk; } + memcpy(vop->regs, vop->regsbak, vop->len); /* * At here, vop clock & iommu is enable, R/W vop regs would be safe. */ -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 6/6] drm/rockchip: vop: support plane scale 2015-07-21 8:20 [PATCH v3 0/6] drm/rockchip: fixes and new features Mark Yao ` (4 preceding siblings ...) 2015-07-21 8:27 ` [PATCH v3 5/6] drm/rockchip: vop: restore vop registers when resume Mark Yao @ 2015-07-21 8:28 ` Mark Yao 2015-07-22 21:50 ` Heiko Stübner 2015-07-22 21:55 ` [PATCH v3 0/6] drm/rockchip: fixes and new features Heiko Stübner 6 siblings, 1 reply; 12+ messages in thread From: Mark Yao @ 2015-07-21 8:28 UTC (permalink / raw) To: dri-devel Cc: zwl, linux-kernel, tfiga, linux-rockchip, xw, dkm, sandy.huang, linux-arm-kernel Win_full support 1/8 to 8 scale down/up engine, support all format scale. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- Changes in v3: Adviced by Tomasz Figa - remove unused code and unnecessary scale path. - use static inline funcion instead "#define", let gcc check the cast - move same call into helper, make code clean. Changes in v2: - Fix scale dest info. drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 196 ++++++++++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 87 ++++++++++++ 2 files changed, 281 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 4dfad065..8257e98 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -49,6 +49,8 @@ #define VOP_WIN_SET(x, win, name, v) \ REG_SET(x, win->base, win->phy->name, v, RELAXED) +#define VOP_SCL_SET(x, win, name, v) \ + REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) #define VOP_CTRL_SET(x, name, v) \ REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) @@ -163,7 +165,37 @@ struct vop_ctrl { struct vop_reg vpost_st_end; }; +struct vop_scl_regs { + struct vop_reg cbcr_vsd_mode; + struct vop_reg cbcr_vsu_mode; + struct vop_reg cbcr_hsd_mode; + struct vop_reg cbcr_ver_scl_mode; + struct vop_reg cbcr_hor_scl_mode; + struct vop_reg yrgb_vsd_mode; + struct vop_reg yrgb_vsu_mode; + struct vop_reg yrgb_hsd_mode; + struct vop_reg yrgb_ver_scl_mode; + struct vop_reg yrgb_hor_scl_mode; + struct vop_reg line_load_mode; + struct vop_reg cbcr_axi_gather_num; + struct vop_reg yrgb_axi_gather_num; + struct vop_reg vsd_cbcr_gt2; + struct vop_reg vsd_cbcr_gt4; + struct vop_reg vsd_yrgb_gt2; + struct vop_reg vsd_yrgb_gt4; + struct vop_reg bic_coe_sel; + struct vop_reg cbcr_axi_gather_en; + struct vop_reg yrgb_axi_gather_en; + + struct vop_reg lb_mode; + struct vop_reg scale_yrgb_x; + struct vop_reg scale_yrgb_y; + struct vop_reg scale_cbcr_x; + struct vop_reg scale_cbcr_y; +}; + struct vop_win_phy { + const struct vop_scl_regs *scl; const uint32_t *data_formats; uint32_t nformats; @@ -212,7 +244,36 @@ static const uint32_t formats_234[] = { DRM_FORMAT_RGB565, }; +static const struct vop_scl_regs win_full_scl = { + .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31), + .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30), + .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28), + .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26), + .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24), + .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23), + .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22), + .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20), + .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18), + .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16), + .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15), + .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12), + .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8), + .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7), + .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6), + .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5), + .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4), + .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2), + .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1), + .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0), + .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5), + .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + static const struct vop_win_phy win01_data = { + .scl = &win_full_scl, .data_formats = formats_01, .nformats = ARRAY_SIZE(formats_01), .enable = VOP_REG(WIN0_CTRL0, 0x1, 0), @@ -401,6 +462,126 @@ static bool is_alpha_support(uint32_t format) } } +static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, + uint32_t dst, int scan_type, + int vsu_mode, int *vskiplines) +{ + uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; + + if (scan_type == 0) { + if (mode == SCALE_UP) + val = GET_SCL_FT_BIC(src, dst); + else if (mode == SCALE_DOWN) + val = GET_SCL_FT_BILI_DN(src, dst); + } else { + if (mode == SCALE_UP) { + if (vsu_mode == SCALE_UP_BIL) + val = GET_SCL_FT_BILI_UP(src, dst); + else + val = GET_SCL_FT_BIC(src, dst); + } else if (mode == SCALE_DOWN) { + if (vskiplines) { + *vskiplines = scl_get_vskiplines(src, dst); + val = scl_get_bili_dn_vskip(src, dst, + *vskiplines); + } else { + val = GET_SCL_FT_BILI_DN(src, dst); + } + } + } + + return val; +} + +static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, + uint32_t src_w, uint32_t src_h, uint32_t dst_w, + uint32_t dst_h, uint32_t pixel_format) +{ + uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; + uint16_t cbcr_hor_scl_mode = SCALE_NONE; + uint16_t cbcr_ver_scl_mode = SCALE_NONE; + int hsub = drm_format_horz_chroma_subsampling(pixel_format); + int vsub = drm_format_vert_chroma_subsampling(pixel_format); + bool is_yuv = is_yuv_support(pixel_format); + uint16_t cbcr_src_w = src_w / hsub; + uint16_t cbcr_src_h = src_h / vsub; + uint16_t vsu_mode; + uint16_t lb_mode; + uint32_t val; + int vskiplines; + + if (dst_w > 3840) { + DRM_ERROR("yrgb scale exceed 8,src[%dx%d] dst[%dx%d]\n", + src_w, src_h, dst_w, dst_h); + return; + } + + yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); + yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); + + if (is_yuv) { + cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); + cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); + if (cbcr_hor_scl_mode == SCALE_DOWN) + lb_mode = scl_vop_cal_lb_mode(dst_w, true); + else + lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); + } else { + if (yrgb_hor_scl_mode == SCALE_DOWN) + lb_mode = scl_vop_cal_lb_mode(dst_w, false); + else + lb_mode = scl_vop_cal_lb_mode(src_w, false); + } + + VOP_SCL_SET(vop, win, lb_mode, lb_mode); + if (lb_mode == LB_RGB_3840X2) { + if (yrgb_ver_scl_mode != SCALE_NONE) { + DRM_ERROR("ERROR : not allow yrgb ver scale\n"); + return; + } + if (cbcr_ver_scl_mode != SCALE_NONE) { + DRM_ERROR("ERROR : not allow cbcr ver scale\n"); + return; + } + vsu_mode = SCALE_UP_BIL; + } else if (lb_mode == LB_RGB_2560X4) { + vsu_mode = SCALE_UP_BIL; + } else { + vsu_mode = SCALE_UP_BIC; + } + + val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 0, 0, NULL); + VOP_SCL_SET(vop, win, scale_yrgb_x, val); + val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, + 1, vsu_mode, &vskiplines); + VOP_SCL_SET(vop, win, scale_yrgb_y, val); + + VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4); + VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2); + + VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); + VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); + VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); + VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); + VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode); + if (is_yuv) { + val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, + dst_w, 0, 0, NULL); + VOP_SCL_SET(vop, win, scale_cbcr_x, val); + val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, + dst_h, 1, vsu_mode, &vskiplines); + VOP_SCL_SET(vop, win, scale_cbcr_y, val); + + VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4); + VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2); + VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); + VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); + VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); + VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); + VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode); + } +} + static void vop_dsp_hold_valid_irq_enable(struct vop *vop) { unsigned long flags; @@ -631,11 +812,13 @@ static int vop_update_plane_event(struct drm_plane *plane, .y2 = crtc->mode.vdisplay, }; bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY; + int min_scale = win->phy->scl ? 0x02000 : DRM_PLANE_HELPER_NO_SCALING; + int max_scale = win->phy->scl ? 0x80000 : DRM_PLANE_HELPER_NO_SCALING; ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, + min_scale, + max_scale, can_position, false, &visible); if (ret) return ret; @@ -738,9 +921,18 @@ static int vop_update_plane_event(struct drm_plane *plane, VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride); VOP_WIN_SET(vop, win, uv_mst, uv_mst); } + + if (win->phy->scl) + scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, + dest.x2 - dest.x1, dest.y2 - dest.y1, + fb->pixel_format); + val = (actual_h - 1) << 16; val |= (actual_w - 1) & 0xffff; VOP_WIN_SET(vop, win, act_info, val); + + val = (dest.y2 - dest.y1 - 1) << 16; + val |= (dest.x2 - dest.x1 - 1) & 0xffff; VOP_WIN_SET(vop, win, dsp_info, val); val = (dsp_sty - 1) << 16; val |= (dsp_stx - 1) & 0xffff; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 63e9b3a..78cd321 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -198,4 +198,91 @@ enum factor_mode { ALPHA_SRC_GLOBAL, }; +enum scale_mode { + SCALE_NONE = 0x0, + SCALE_UP = 0x1, + SCALE_DOWN = 0x2 +}; + +enum lb_mode { + LB_YUV_3840X5 = 0x0, + LB_YUV_2560X8 = 0x1, + LB_RGB_3840X2 = 0x2, + LB_RGB_2560X4 = 0x3, + LB_RGB_1920X5 = 0x4, + LB_RGB_1280X8 = 0x5 +}; + +enum sacle_up_mode { + SCALE_UP_BIL = 0x0, + SCALE_UP_BIC = 0x1 +}; + +enum scale_down_mode { + SCALE_DOWN_BIL = 0x0, + SCALE_DOWN_AVG = 0x1 +}; + +#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 +#define SCL_MAX_VSKIPLINES 4 +#define MIN_SCL_FT_AFTER_VSKIP 1 + +static inline uint16_t scl_cal_scale(int src, int dst, int shift) +{ + return ((src * 2 - 3) << (shift - 1)) / (dst - 1); +} + +#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) +#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) +#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) + +static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, + int vskiplines) +{ + int act_height; + + act_height = (src_h + vskiplines - 1) / vskiplines; + + return GET_SCL_FT_BILI_DN(act_height, dst_h); +} + +static inline enum scale_mode scl_get_scl_mode(int src, int dst) +{ + if (src < dst) + return SCALE_UP; + else if (src > dst) + return SCALE_DOWN; + + return SCALE_NONE; +} + +static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) +{ + uint32_t vskiplines; + + for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) + if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) + break; + + return vskiplines; +} + +static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) +{ + int lb_mode; + + if (width > 2560) + lb_mode = LB_RGB_3840X2; + else if (width > 1920) + lb_mode = LB_RGB_2560X4; + else if (!is_yuv) + lb_mode = LB_RGB_1920X5; + else if (width > 1280) + lb_mode = LB_YUV_3840X5; + else + lb_mode = LB_YUV_2560X8; + + return lb_mode; +} + #endif /* _ROCKCHIP_DRM_VOP_H */ -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 6/6] drm/rockchip: vop: support plane scale 2015-07-21 8:28 ` [PATCH v3 6/6] drm/rockchip: vop: support plane scale Mark Yao @ 2015-07-22 21:50 ` Heiko Stübner 0 siblings, 0 replies; 12+ messages in thread From: Heiko Stübner @ 2015-07-22 21:50 UTC (permalink / raw) To: Mark Yao Cc: zwl, linux-kernel, tfiga, linux-rockchip, dri-devel, xw, dkm, sandy.huang, linux-arm-kernel Am Dienstag, 21. Juli 2015, 16:28:52 schrieb Mark Yao: > Win_full support 1/8 to 8 scale down/up engine, support > all format scale. > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > --- > Changes in v3: > Adviced by Tomasz Figa > - remove unused code and unnecessary scale path. > - use static inline funcion instead "#define", let gcc check the cast > - move same call into helper, make code clean. > > Changes in v2: > - Fix scale dest info. > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 196 > ++++++++++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | > 87 ++++++++++++ > 2 files changed, 281 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 4dfad065..8257e98 > 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > @@ -49,6 +49,8 @@ > > #define VOP_WIN_SET(x, win, name, v) \ > REG_SET(x, win->base, win->phy->name, v, RELAXED) > +#define VOP_SCL_SET(x, win, name, v) \ > + REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) > #define VOP_CTRL_SET(x, name, v) \ > REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) > > @@ -163,7 +165,37 @@ struct vop_ctrl { > struct vop_reg vpost_st_end; > }; > > +struct vop_scl_regs { > + struct vop_reg cbcr_vsd_mode; > + struct vop_reg cbcr_vsu_mode; > + struct vop_reg cbcr_hsd_mode; > + struct vop_reg cbcr_ver_scl_mode; > + struct vop_reg cbcr_hor_scl_mode; > + struct vop_reg yrgb_vsd_mode; > + struct vop_reg yrgb_vsu_mode; > + struct vop_reg yrgb_hsd_mode; > + struct vop_reg yrgb_ver_scl_mode; > + struct vop_reg yrgb_hor_scl_mode; > + struct vop_reg line_load_mode; > + struct vop_reg cbcr_axi_gather_num; > + struct vop_reg yrgb_axi_gather_num; > + struct vop_reg vsd_cbcr_gt2; > + struct vop_reg vsd_cbcr_gt4; > + struct vop_reg vsd_yrgb_gt2; > + struct vop_reg vsd_yrgb_gt4; > + struct vop_reg bic_coe_sel; > + struct vop_reg cbcr_axi_gather_en; > + struct vop_reg yrgb_axi_gather_en; > + > + struct vop_reg lb_mode; > + struct vop_reg scale_yrgb_x; > + struct vop_reg scale_yrgb_y; > + struct vop_reg scale_cbcr_x; > + struct vop_reg scale_cbcr_y; > +}; > + > struct vop_win_phy { > + const struct vop_scl_regs *scl; > const uint32_t *data_formats; > uint32_t nformats; > > @@ -212,7 +244,36 @@ static const uint32_t formats_234[] = { > DRM_FORMAT_RGB565, > }; does not apply to what's in mainline, as this patch seems to ignore 85a359f25388 ("drm/rockchip: Add BGR formats to VOP") from Tomasz Heiko _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/6] drm/rockchip: fixes and new features 2015-07-21 8:20 [PATCH v3 0/6] drm/rockchip: fixes and new features Mark Yao ` (5 preceding siblings ...) 2015-07-21 8:28 ` [PATCH v3 6/6] drm/rockchip: vop: support plane scale Mark Yao @ 2015-07-22 21:55 ` Heiko Stübner 6 siblings, 0 replies; 12+ messages in thread From: Heiko Stübner @ 2015-07-22 21:55 UTC (permalink / raw) To: Mark Yao Cc: zwl, linux-kernel, tfiga, linux-rockchip, dri-devel, xw, dkm, sandy.huang, linux-arm-kernel Am Dienstag, 21. Juli 2015, 16:20:01 schrieb Mark Yao: > This series patches are used for yuv image overlay display. > > Rockchip vop support NV11, NV16, NV24 yuv format, > and can scale the image scale 1/8 to 8. I've tested this series on veyron-pinky on 4.2-rc3, as mentioned as response to patch 4/6, this actually brings back my x11 cursor that vanished after 4.2- rc1 :-) For the whole series Tested-by: Heiko Stuebner <heiko@sntech.de> _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2015-07-23 2:02 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-07-21 8:20 [PATCH v3 0/6] drm/rockchip: fixes and new features Mark Yao 2015-07-21 8:20 ` [PATCH v3 1/6] drm/rockchip: vop: Fix virtual stride calculation Mark Yao 2015-07-21 8:20 ` [PATCH v3 2/6] drm/rockchip: vop: Fix window dest start point Mark Yao 2015-07-21 8:20 ` [PATCH v3 3/6] drm/rockchip: vop: Add yuv plane support Mark Yao 2015-07-22 21:51 ` Heiko Stübner 2015-07-23 2:01 ` Mark yao 2015-07-21 8:25 ` [PATCH v3 4/6] drm/rockchip: vop: Default enable win2/3 area0 bit Mark Yao 2015-07-22 21:50 ` Heiko Stübner 2015-07-21 8:27 ` [PATCH v3 5/6] drm/rockchip: vop: restore vop registers when resume Mark Yao 2015-07-21 8:28 ` [PATCH v3 6/6] drm/rockchip: vop: support plane scale Mark Yao 2015-07-22 21:50 ` Heiko Stübner 2015-07-22 21:55 ` [PATCH v3 0/6] drm/rockchip: fixes and new features Heiko Stübner
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).