From: CK Hu <ck.hu@mediatek.com>
To: wangyan wang <wangyan.wang@mediatek.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
chunhui dai <chunhui.dai@mediatek.com>,
Colin Ian King <colin.king@canonical.com>,
Sean Wang <sean.wang@mediatek.com>,
Ryder Lee <ryder.lee@mediatek.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
dri-devel@lists.freedesktop.org, srv_heupstream@mediatek.com
Subject: Re: [PATCH V6 0/8] make mt7623 clock of hdmi stable
Date: Wed, 6 Mar 2019 09:52:21 +0800 [thread overview]
Message-ID: <1551837141.23995.13.camel@mtksdaap41> (raw)
In-Reply-To: <20190225020912.29120-1-wangyan.wang@mediatek.com>
On Mon, 2019-02-25 at 10:09 +0800, wangyan wang wrote:
> From: Wangyan Wang <wangyan.wang@mediatek.com>
>
> V6 adopt maintainer's suggestion.
> Here is the change list between V5 & V6
> 1. change "unsigned char mux_flags;" to "u8 mux_flags;" to
> match with the struct in " clk: mediatek: add MUX_GATE_FLAGS_2".
>
Hi, Wangyan:
I'm not familiar with this clock system, so I still have some question
about it, if you could describe more clear, it would help us to speed up
this review process.
In [1], I find the clock that dpi and hdmi_phy controls,
dpi0: dpi@14014000 {
clocks = <&mmsys CLK_MM_DPI1_DIGL>,
<&mmsys CLK_MM_DPI1_ENGINE>,
<&topckgen CLK_TOP_TVDPLL>;
clock-names = "pixel", "engine", "pll";
};
hdmi_phy: phy@10209100 {
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
clock-names = "pll_ref";
};
In [2], You say that to prevent changing tvdpll would let hdmi stable,
and this clock is controlled by dpi, why do you modify the control flow
in hdmi_phy? If these two have relationship, please describe more clear
because I'm not familiar with this clock system.
And I think that patch 'drm/mediatek: using new factor for tvdpll in
MT2701' is the major patch to prevent modifying tvdpll because it reduce
the factor case. Does MT8173 has the same problem? Just ask, I does not
require you to modify MT8173 part.
[1]
https://github.com/frank-w/BPI-R2-4.14/blob/663f7def421952eb49b2d698eadaff12d02622d2/arch/arm/boot/dts/mt7623.dtsi
[2]
http://lists.infradead.org/pipermail/linux-mediatek/2019-February/017693.html
Regards,
CK
>
> chunhui dai (8):
> drm/mediatek: recalculate hdmi phy clock of MT2701 by querying
> hardware
> drm/mediatek: move the setting of fixed divider
> drm/mediatek: using different flags of clk for HDMI phy
> drm/mediatek: fix the rate and divder of hdmi phy for MT2701
> clk: mediatek: add MUX_GATE_FLAGS_2
> clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
> drm/mediatek: using new factor for tvdpll in MT2701
> drm/mediatek: fix the rate of parent for hdmi phy in MT2701
>
> drivers/clk/mediatek/clk-mt2701.c | 4 +-
> drivers/clk/mediatek/clk-mtk.c | 2 +-
> drivers/clk/mediatek/clk-mtk.h | 20 ++++++---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++--
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 34 ++++------------
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 7 +---
> drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 56 +++++++++++++++++++++++---
> drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 +++++++++++
> 8 files changed, 102 insertions(+), 52 deletions(-)
>
next prev parent reply other threads:[~2019-03-06 1:52 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-25 2:09 [PATCH V6 0/8] make mt7623 clock of hdmi stable wangyan wang
2019-02-25 2:09 ` [PATCH v6 1/8] drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware wangyan wang
2019-03-06 10:07 ` CK Hu
2019-03-21 3:23 ` CK Hu
2019-03-22 6:02 ` CK Hu
2019-02-25 2:09 ` [PATCH V6 2/8] drm/mediatek: move the setting of fixed divider wangyan wang
2019-02-25 2:09 ` [PATCH V6 3/8] drm/mediatek: using different flags of clk for HDMI phy wangyan wang
2019-02-25 2:09 ` [PATCH V6 4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701 wangyan wang
2019-02-25 2:09 ` [PATCH V6 5/8] clk: mediatek: add MUX_GATE_FLAGS_2 wangyan wang
2019-02-25 17:19 ` Stephen Boyd
2019-02-25 2:09 ` [PATCH V6 6/8] clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel wangyan wang
2019-02-25 17:19 ` Stephen Boyd
2019-02-25 2:09 ` [PATCH V6 7/8] drm/mediatek: using new factor for tvdpll in MT2701 wangyan wang
2019-02-25 2:09 ` [PATCH V6 8/8] drm/mediatek: fix the rate of parent for hdmi phy " wangyan wang
2019-03-06 10:13 ` CK Hu
2019-03-21 5:32 ` CK Hu
2019-03-21 7:20 ` CK Hu
2019-03-06 1:52 ` CK Hu [this message]
2019-03-06 9:48 ` [PATCH V6 0/8] make mt7623 clock of hdmi stable CK Hu
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