From: wangyan wang <wangyan.wang@mediatek.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, CK Hu <ck.hu@mediatek.com>
Cc: wangyan wang <wangyan.wang@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
chunhui dai <chunhui.dai@mediatek.com>,
Colin Ian King <colin.king@canonical.com>,
Sean Wang <sean.wang@mediatek.com>,
Ryder Lee <ryder.lee@mediatek.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
dri-devel@lists.freedesktop.org, srv_heupstream@mediatek.com
Subject: [PATCH V6 8/8] drm/mediatek: fix the rate of parent for hdmi phy in MT2701
Date: Mon, 25 Feb 2019 10:09:12 +0800 [thread overview]
Message-ID: <20190225020912.29120-9-wangyan.wang@mediatek.com> (raw)
In-Reply-To: <20190225020912.29120-1-wangyan.wang@mediatek.com>
From: chunhui dai <chunhui.dai@mediatek.com>
We should not change the rate of parent for hdmi phy when
doing round_rate for this clock. The parent clock of hdmi
phy must be the same as it. We change it when doing set_rate
only.
Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
Signed-off-by: wangyan wang <wangyan.wang@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 14 --------------
drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 3 ---
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 11 +++++++++++
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 14 ++++++++++++++
4 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
index 370309d684ec..ca8bc1489f37 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
@@ -15,20 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = {
.owner = THIS_MODULE,
};
-long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
-{
- struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
-
- hdmi_phy->pll_rate = rate;
- if (rate <= 74250000)
- *parent_rate = rate;
- else
- *parent_rate = rate / 2;
-
- return rate;
-}
-
u32 mtk_hdmi_phy_read(struct mtk_hdmi_phy *hdmi_phy, u32 offset)
{
return readl(hdmi_phy->regs + offset);
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
index 446e2acd1926..c6061ad15ff0 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
@@ -50,9 +50,6 @@ void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
u32 val, u32 mask);
struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
-long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate);
-
extern struct platform_driver mtk_hdmi_phy_driver;
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
index 88dd9e812ca0..33893a180c2e 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
@@ -152,6 +152,17 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
RG_HDMITX_DRV_IBIAS_MASK);
return 0;
}
+
+static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+
+ hdmi_phy->pll_rate = rate;
+
+ return rate;
+}
+
static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
index 63dde42521b8..3a339f516613 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
@@ -285,6 +285,20 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
+static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+
+ hdmi_phy->pll_rate = rate;
+ if (rate <= 74250000)
+ *parent_rate = rate;
+ else
+ *parent_rate = rate / 2;
+
+ return rate;
+}
+
static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
--
2.14.1
next prev parent reply other threads:[~2019-02-25 2:09 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-25 2:09 [PATCH V6 0/8] make mt7623 clock of hdmi stable wangyan wang
2019-02-25 2:09 ` [PATCH v6 1/8] drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware wangyan wang
2019-03-06 10:07 ` CK Hu
2019-03-21 3:23 ` CK Hu
2019-03-22 6:02 ` CK Hu
2019-02-25 2:09 ` [PATCH V6 2/8] drm/mediatek: move the setting of fixed divider wangyan wang
2019-02-25 2:09 ` [PATCH V6 3/8] drm/mediatek: using different flags of clk for HDMI phy wangyan wang
2019-02-25 2:09 ` [PATCH V6 4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701 wangyan wang
2019-02-25 2:09 ` [PATCH V6 5/8] clk: mediatek: add MUX_GATE_FLAGS_2 wangyan wang
2019-02-25 17:19 ` Stephen Boyd
2019-02-25 2:09 ` [PATCH V6 6/8] clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel wangyan wang
2019-02-25 17:19 ` Stephen Boyd
2019-02-25 2:09 ` [PATCH V6 7/8] drm/mediatek: using new factor for tvdpll in MT2701 wangyan wang
2019-02-25 2:09 ` wangyan wang [this message]
2019-03-06 10:13 ` [PATCH V6 8/8] drm/mediatek: fix the rate of parent for hdmi phy " CK Hu
2019-03-21 5:32 ` CK Hu
2019-03-21 7:20 ` CK Hu
2019-03-06 1:52 ` [PATCH V6 0/8] make mt7623 clock of hdmi stable CK Hu
2019-03-06 9:48 ` CK Hu
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