Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183

From: CK Hu <ck.hu@mediatek.com>
To: Hsin-Yi Wang <hsinyi@chromium.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, David Airlie <airlied@linux.ie>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	Project_Global_Chrome_Upstream_Group@mediatek.com,
	linux-mediatek@lists.infradead.org,
	Matthias Brugger <matthias.bgg@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183
Date: Thu, 28 Jan 2021 14:19:51 +0800	[thread overview]
Message-ID: <1611814791.28312.12.camel@mtksdaap41> (raw)
In-Reply-To: <1611814421.28312.9.camel@mtksdaap41>

On Thu, 2021-01-28 at 14:13 +0800, CK Hu wrote:
> Hi, Hsin-Yi:
> 
> Modify the title's prefix to 'soc: mediatek:'

Modify more, the title should be 'soc: mediatek: add mtk mutex support
for MT8183'

> 
> On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > From: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > 
> > Add DDP support for MT8183 SoC.
> > 
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > ---
> >  drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++
> >  1 file changed, 50 insertions(+)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> > index f531b119da7a9..f64e9c33e85ad 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -14,6 +14,8 @@
> >  
> >  #define MT2701_MUTEX0_MOD0			0x2c
> >  #define MT2701_MUTEX0_SOF0			0x30
> > +#define MT8183_DISP_MUTEX0_MOD0			0x30
> > +#define MT8183_DISP_MUTEX0_SOF0			0x2c
> 
> Modify 'DISP_MUTEX' to 'MUTEX'
> 
> >  
> >  #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
> >  #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
> > @@ -37,6 +39,18 @@
> >  #define MT8167_MUTEX_MOD_DISP_DITHER		15
> >  #define MT8167_MUTEX_MOD_DISP_UFOE		16
> >  
> > +#define MT8183_MUTEX_MOD_DISP_RDMA0		0
> > +#define MT8183_MUTEX_MOD_DISP_RDMA1		1
> > +#define MT8183_MUTEX_MOD_DISP_OVL0		9
> > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L		10
> > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L		11
> > +#define MT8183_MUTEX_MOD_DISP_WDMA0		12
> > +#define MT8183_MUTEX_MOD_DISP_COLOR0		13
> > +#define MT8183_MUTEX_MOD_DISP_CCORR0		14
> > +#define MT8183_MUTEX_MOD_DISP_AAL0		15
> > +#define MT8183_MUTEX_MOD_DISP_GAMMA0		16
> > +#define MT8183_MUTEX_MOD_DISP_DITHER0		17
> > +
> >  #define MT8173_MUTEX_MOD_DISP_OVL0		11
> >  #define MT8173_MUTEX_MOD_DISP_OVL1		12
> >  #define MT8173_MUTEX_MOD_DISP_RDMA0		13
> > @@ -87,6 +101,12 @@
> >  #define MT2712_MUTEX_SOF_DSI3			6
> >  #define MT8167_MUTEX_SOF_DPI0			2
> >  #define MT8167_MUTEX_SOF_DPI1			3
> > +#define MT8183_MUTEX_SOF_DSI0			1
> > +#define MT8183_MUTEX_SOF_DPI0			2
> > +
> > +/* Add EOF setting so overlay hardware can receive frame done irq */
> > +#define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
> > +#define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
> >  
> >  struct mtk_mutex {
> >  	int id;
> > @@ -181,6 +201,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> >  	[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> >  };
> >  
> > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > +	[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> > +	[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> > +	[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> > +	[DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> > +	[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> > +	[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> > +	[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> > +	[DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> > +	[DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> > +	[DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> > +	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> > +};
> > +
> >  static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> >  	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> >  	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> > @@ -198,6 +232,12 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> >  	[MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> >  };
> >  
> > +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > +	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > +	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> > +	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> 
> According to discussion in [1], add comment for the odd EOF setting.
> 
> [1]
> https://patchwork.kernel.org/project/linux-mediatek/patch/1595469798-3824-8-git-send-email-yongqiang.niu@mediatek.com/
> 
> Regards,
> CK.
> 
> 
> > +};
> > +
> >  static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> >  	.mutex_mod = mt2701_mutex_mod,
> >  	.mutex_sof = mt2712_mutex_sof,
> > @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = {
> >  	.mutex_sof_reg = MT2701_MUTEX0_SOF0,
> >  };
> >  
> > +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> > +	.mutex_mod = mt8183_mutex_mod,
> > +	.mutex_sof = mt8183_mutex_sof,
> > +	.mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
> > +	.mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
> > +	.no_clk = true,
> > +};
> > +
> >  struct mtk_mutex *mtk_mutex_get(struct device *dev)
> >  {
> >  	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> > @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> >  	  .data = &mt8167_mutex_driver_data},
> >  	{ .compatible = "mediatek,mt8173-disp-mutex",
> >  	  .data = &mt8173_mutex_driver_data},
> > +	{ .compatible = "mediatek,mt8183-disp-mutex",
> > +	  .data = &mt8183_mutex_driver_data},
> >  	{},
> >  };
> >  MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
> 

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