From: Andrzej Hajda <a.hajda@samsung.com>
To: Inki Dae <inki.dae@samsung.com>
Cc: linux-samsung-soc@vger.kernel.org,
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
dri-devel@lists.freedesktop.org,
Marek Szyprowski <m.szyprowski@samsung.com>
Subject: [PATCH v2 RESEND 24/24] drm/exynos/gscaler: fix handling YVU420 pixel format
Date: Wed, 20 Mar 2019 14:07:07 +0100 [thread overview]
Message-ID: <20190320130707.25161-25-a.hajda@samsung.com> (raw)
In-Reply-To: <20190320130707.25161-1-a.hajda@samsung.com>
YVU420 requires swapping addresses of U and V planes.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
drivers/gpu/drm/exynos/exynos_drm_gsc.c | 52 ++++++++++++++++++-------
1 file changed, 37 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
index c7a97d053ab1..f75739e8bc55 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -535,10 +535,8 @@ static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
cfg |= GSC_IN_YUV422_3P;
break;
case DRM_FORMAT_YUV420:
- cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
- break;
case DRM_FORMAT_YVU420:
- cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
+ cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
break;
case DRM_FORMAT_NV12:
cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
@@ -658,13 +656,32 @@ static void gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
}
+/* returns HW plane index based on pixel format */
+static int gsc_hw_plane_index(int index, u32 format)
+{
+ switch (format) {
+ case DRM_FORMAT_YVU420:
+ switch (index) {
+ case 0: return 0;
+ case 1: return 2;
+ case 2: return 1;
+ }
+ default:
+ return index;
+ }
+}
+
static void gsc_src_set_addr(struct gsc_context *ctx, u32 buf_id,
struct exynos_drm_ipp_buffer *buf)
{
+ int idx;
+
/* address register set */
gsc_write(buf->dma_addr[0], GSC_IN_BASE_ADDR_Y(buf_id));
- gsc_write(buf->dma_addr[1], GSC_IN_BASE_ADDR_CB(buf_id));
- gsc_write(buf->dma_addr[2], GSC_IN_BASE_ADDR_CR(buf_id));
+ idx = gsc_hw_plane_index(1, buf->format->format);
+ gsc_write(buf->dma_addr[idx], GSC_IN_BASE_ADDR_CB(buf_id));
+ idx = gsc_hw_plane_index(2, buf->format->format);
+ gsc_write(buf->dma_addr[idx], GSC_IN_BASE_ADDR_CR(buf_id));
gsc_src_set_buf_seq(ctx, buf_id, true);
}
@@ -722,10 +739,8 @@ static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
cfg |= GSC_OUT_YUV422_3P;
break;
case DRM_FORMAT_YUV420:
- cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
- break;
case DRM_FORMAT_YVU420:
- cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
+ cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
break;
case DRM_FORMAT_NV12:
cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
@@ -985,10 +1000,13 @@ static void gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
static void gsc_dst_set_addr(struct gsc_context *ctx,
u32 buf_id, struct exynos_drm_ipp_buffer *buf)
{
- /* address register set */
+ int i;
+
gsc_write(buf->dma_addr[0], GSC_OUT_BASE_ADDR_Y(buf_id));
- gsc_write(buf->dma_addr[1], GSC_OUT_BASE_ADDR_CB(buf_id));
- gsc_write(buf->dma_addr[2], GSC_OUT_BASE_ADDR_CR(buf_id));
+ i = gsc_hw_plane_index(1, buf->format->format);
+ gsc_write(buf->dma_addr[i], GSC_OUT_BASE_ADDR_CB(buf_id));
+ i = gsc_hw_plane_index(2, buf->format->format);
+ gsc_write(buf->dma_addr[i], GSC_OUT_BASE_ADDR_CR(buf_id));
gsc_dst_set_buf_seq(ctx, buf_id, true);
}
@@ -1238,10 +1256,14 @@ static void gsc_update_plane(struct exynos_drm_plane *plane)
gsc_write(BIT(16) * cropped_w / scaled_w, GSC_MAIN_H_RATIO);
gsc_write(BIT(16) * cropped_h / scaled_h, GSC_MAIN_V_RATIO);
gsc_write(exynos_drm_fb_dma_addr(fb, 0), GSC_IN_BASE_ADDR_Y(0));
- if (fb->format->num_planes > 1)
- gsc_write(exynos_drm_fb_dma_addr(fb, 1), GSC_IN_BASE_ADDR_CB(0));
- if (fb->format->num_planes > 2)
- gsc_write(exynos_drm_fb_dma_addr(fb, 2), GSC_IN_BASE_ADDR_CR(0));
+ if (fb->format->num_planes > 1) {
+ i = gsc_hw_plane_index(1, fb->format->format);
+ gsc_write(exynos_drm_fb_dma_addr(fb, i), GSC_IN_BASE_ADDR_CB(0));
+ }
+ if (fb->format->num_planes > 2) {
+ i = gsc_hw_plane_index(2, fb->format->format);
+ gsc_write(exynos_drm_fb_dma_addr(fb, i), GSC_IN_BASE_ADDR_CR(0));
+ }
gsc_src_set_fmt(ctx, fb->format->format, fb->modifier);
gsc_write(scaled_w * scaled_h, GSC_SMART_IF_PIXEL_NUM);
gsc_write(GSC_ENABLE_SFR_UPDATE | GSC_ENABLE_ON, GSC_ENABLE);
--
2.17.1
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next prev parent reply other threads:[~2019-03-20 13:07 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190320130711eucas1p2b9f18d009647652b4bb912fdd40c9f74@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 00/24] drm/exynos: add support for GSCALER planes on Exynos5433 Andrzej Hajda
[not found] ` <CGME20190320130712eucas1p2c98ef5f0f42d422dc711c222fa4da11b@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 01/24] drm/exynos: remove exynos_drm_plane.h header Andrzej Hajda
[not found] ` <CGME20190320130712eucas1p2f3735c6c5afd7117f297ce7f495e4479@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 02/24] drm/exynos: remove spare macro Andrzej Hajda
[not found] ` <CGME20190320130713eucas1p137746c8fcdf13bbe1c897c27a245b22a@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 03/24] drm/exynos: drop exynos_drm_plane_config structure Andrzej Hajda
[not found] ` <CGME20190320130713eucas1p2dd57732ea0135355863ba26424a8bacf@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 04/24] drm/exynos: add exynos_drm_crtc_init function Andrzej Hajda
[not found] ` <CGME20190320130714eucas1p1c0b414ed76d7d0d78da56c9c0a6c8973@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 05/24] drm/exynos/decon5433: embed exynos_drm_crtc directly into context Andrzej Hajda
[not found] ` <CGME20190320130714eucas1p2e4f96fe67486283560c7b6a8627b769c@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 06/24] drm/exynos/decon7: " Andrzej Hajda
[not found] ` <CGME20190320130714eucas1p1d3ab6fceec849f22bab69df1e46b972d@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 07/24] drm/exynos/fimd: " Andrzej Hajda
[not found] ` <CGME20190320130715eucas1p250b6b902360896cd36bff8536b6292bf@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 08/24] drm/exynos/mixer: " Andrzej Hajda
[not found] ` <CGME20190320130715eucas1p2ab0449e8b243fcfa2d63524363eb8544@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 09/24] drm/exynos/vidi: " Andrzej Hajda
[not found] ` <CGME20190320130715eucas1p1cc35aa50021848a6f3d5459bb0c6d1bf@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 10/24] drm/exynos: remove standalone exynos_drm_crtc leftovers Andrzej Hajda
[not found] ` <CGME20190320130716eucas1p2fa37979f7715c411e079d146b96628cb@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 11/24] drm/exynos/vidi: remove encoder_to_vidi helper Andrzej Hajda
[not found] ` <CGME20190320130716eucas1p121bc6480ad28d1c0c79c195ae943ee55@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 12/24] drm/exynos: unify plane type assignment Andrzej Hajda
[not found] ` <CGME20190320130717eucas1p2a2a480a8c5d71fc66741410829a0d016@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 13/24] drm/exynos: set primary plane in exynos_drm_crtc_init Andrzej Hajda
[not found] ` <CGME20190320130717eucas1p2c75749455fa4b34b4d21f9873b3d9cb6@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 14/24] drm/exynos: set cursor " Andrzej Hajda
[not found] ` <CGME20190320130718eucas1p15d440d88365fa5ea213f592b97e6f226@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 15/24] drm/exynos: add plane update/disable callbacks for planes Andrzej Hajda
[not found] ` <CGME20190320130718eucas1p1e42feb422bda24a2db733d50eb41ea47@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 16/24] drm/exynos: add GSCALER plane capability Andrzej Hajda
[not found] ` <CGME20190320130719eucas1p1b411bcd1e32a500202a19a24a4ba92a6@eucas1p1.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 17/24] drm/exynos/gscaler: fix id assignement Andrzej Hajda
[not found] ` <CGME20190320130719eucas1p274be59cfcd798d21ea583bc22f218ff7@eucas1p2.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 18/24] arm64: dts: exynos: configure GSCALER related clocks Andrzej Hajda
[not found] ` <CGME20190320130719eucas1p2e59268e628f6c88db6b632abb153313a@eucas1p2.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 19/24] arm64: dts: exynos: add DSD/GSD clocks to DECONs and GSCALERs Andrzej Hajda
[not found] ` <CGME20190320130720eucas1p1b6f2351c2262d2c89a464fdc10a6a607@eucas1p1.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 20/24] drm/exynos/gscaler: add local path support Andrzej Hajda
[not found] ` <CGME20190320130720eucas1p1f2b27e5d340a50dc710155b37e7b173b@eucas1p1.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 21/24] drm/exynos/decon5433: " Andrzej Hajda
[not found] ` <CGME20190320130721eucas1p2097f22c60919e45a10f9dff6dd678c99@eucas1p2.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 22/24] drm/exynos/decon5433: wait for finish previous update Andrzej Hajda
[not found] ` <CGME20190320130721eucas1p258d3ace8294e90446d369c1d45941dc9@eucas1p2.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 23/24] drm/exynos/gscaler: change supported color format BGRX8888 to XBGR8888 Andrzej Hajda
[not found] ` <CGME20190320130722eucas1p201e6452c3329fdbbc651051da9b14155@eucas1p2.samsung.com>
2019-03-20 13:07 ` Andrzej Hajda [this message]
2019-03-25 3:12 ` [PATCH v2 RESEND 00/24] drm/exynos: add support for GSCALER planes on Exynos5433 Inki Dae
2019-03-25 7:21 ` Andrzej Hajda
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