From: Andrzej Hajda <a.hajda@samsung.com>
To: Inki Dae <inki.dae@samsung.com>
Cc: linux-samsung-soc@vger.kernel.org,
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
dri-devel@lists.freedesktop.org,
Marek Szyprowski <m.szyprowski@samsung.com>
Subject: [PATCH v2 RESEND 03/24] drm/exynos: drop exynos_drm_plane_config structure
Date: Wed, 20 Mar 2019 14:06:46 +0100 [thread overview]
Message-ID: <20190320130707.25161-4-a.hajda@samsung.com> (raw)
In-Reply-To: <20190320130707.25161-1-a.hajda@samsung.com>
exynos_drm_plane_config must be present for every plane, and most fields
are redundant with exynos_drm_plane:
- pixel_formats, num_pixel_formats are stored in plane.base.format_*,
- type is stored in plane.base.type,
- zpos is always equal to plane.index.
The only non-redundant field capabilities can be moved to exynos_drm_plane.
As consequence of removing the structure some code should be refactored.
The patch should not have functional changes.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 18 +++---
drivers/gpu/drm/exynos/exynos7_drm_decon.c | 11 +---
drivers/gpu/drm/exynos/exynos_drm_drv.h | 39 ++++---------
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 17 ++----
drivers/gpu/drm/exynos/exynos_drm_plane.c | 56 +++++++++---------
drivers/gpu/drm/exynos/exynos_drm_vidi.c | 11 +---
drivers/gpu/drm/exynos/exynos_mixer.c | 58 +++++++------------
7 files changed, 76 insertions(+), 134 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 24df0b307b2f..ae0f475eb633 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -56,7 +56,6 @@ struct decon_context {
struct drm_device *drm_dev;
struct exynos_drm_crtc *crtc;
struct exynos_drm_plane planes[WINDOWS_NR];
- struct exynos_drm_plane_config configs[WINDOWS_NR];
void __iomem *addr;
struct regmap *sysreg;
struct clk *clks[ARRAY_SIZE(decon_clks_name)];
@@ -608,22 +607,19 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
struct drm_device *drm_dev = data;
struct exynos_drm_plane *exynos_plane;
enum exynos_drm_output_type out_type;
- unsigned int win;
+ unsigned int i;
int ret;
ctx->drm_dev = drm_dev;
- for (win = ctx->first_win; win < WINDOWS_NR; win++) {
- ctx->configs[win].pixel_formats = decon_formats;
- ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
- ctx->configs[win].zpos = win - ctx->first_win;
- ctx->configs[win].type = decon_win_types[win];
- ctx->configs[win].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS
+ for (i = ctx->first_win; i < WINDOWS_NR; i++) {
+ ctx->planes[i].index = i - ctx->first_win;
+ ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS
| EXYNOS_DRM_PLANE_CAP_WIN_BLEND
| EXYNOS_DRM_PLANE_CAP_PIX_BLEND;
-
- ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
- &ctx->configs[win]);
+ ret = exynos_plane_init(drm_dev, &ctx->planes[i],
+ decon_formats, ARRAY_SIZE(decon_formats),
+ decon_win_types[i]);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
index 812941b84287..6d462f057531 100644
--- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
@@ -44,7 +44,6 @@ struct decon_context {
struct drm_device *drm_dev;
struct exynos_drm_crtc *crtc;
struct exynos_drm_plane planes[WINDOWS_NR];
- struct exynos_drm_plane_config configs[WINDOWS_NR];
struct clk *pclk;
struct clk *aclk;
struct clk *eclk;
@@ -626,13 +625,9 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
}
for (i = 0; i < WINDOWS_NR; i++) {
- ctx->configs[i].pixel_formats = decon_formats;
- ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
- ctx->configs[i].zpos = i;
- ctx->configs[i].type = decon_win_types[i];
-
- ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
- &ctx->configs[i]);
+ ctx->planes[i].index = i;
+ ret = exynos_plane_init(drm_dev, &ctx->planes[i], decon_formats,
+ ARRAY_SIZE(decon_formats), decon_win_types[i]);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 1f6bb5516170..1d4ef0245958 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -71,11 +71,19 @@ to_exynos_plane_state(struct drm_plane_state *state)
return container_of(state, struct exynos_drm_plane_state, base);
}
+#define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0)
+#define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1)
+#define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2)
+#define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3)
+#define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4)
+#define EXYNOS_DRM_PLANE_CAP_WIN_BLEND (1 << 5)
+
/*
* Exynos drm common overlay structure.
*
* @base: plane object
* @index: hardware index of the overlay layer
+ * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*)
*
* this structure is common to exynos SoC and its contents would be copied
* to hardware specific overlay info.
@@ -83,38 +91,13 @@ to_exynos_plane_state(struct drm_plane_state *state)
struct exynos_drm_plane {
struct drm_plane base;
- const struct exynos_drm_plane_config *config;
unsigned int index;
-};
-
-#define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0)
-#define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1)
-#define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2)
-#define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3)
-#define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4)
-#define EXYNOS_DRM_PLANE_CAP_WIN_BLEND (1 << 5)
-
-/*
- * Exynos DRM plane configuration structure.
- *
- * @zpos: initial z-position of the plane.
- * @type: type of the plane (primary, cursor or overlay).
- * @pixel_formats: supported pixel formats.
- * @num_pixel_formats: number of elements in 'pixel_formats'.
- * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*)
- */
-
-struct exynos_drm_plane_config {
- unsigned int zpos;
- enum drm_plane_type type;
- const uint32_t *pixel_formats;
- unsigned int num_pixel_formats;
unsigned int capabilities;
};
-int exynos_plane_init(struct drm_device *dev,
- struct exynos_drm_plane *exynos_plane, unsigned int index,
- const struct exynos_drm_plane_config *config);
+int exynos_plane_init(struct drm_device *dev, struct exynos_drm_plane *plane,
+ const uint32_t *pixel_formats, int num_pixel_formats,
+ enum drm_plane_type type);
/*
* Exynos drm crtc ops
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index b1a9502a4140..2d34ca375ee1 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -171,7 +171,6 @@ struct fimd_context {
struct drm_device *drm_dev;
struct exynos_drm_crtc *crtc;
struct exynos_drm_plane planes[WINDOWS_NR];
- struct exynos_drm_plane_config configs[WINDOWS_NR];
struct clk *bus_clk;
struct clk *lcd_clk;
void __iomem *regs;
@@ -1044,16 +1043,12 @@ static int fimd_bind(struct device *dev, struct device *master, void *data)
ctx->drm_dev = drm_dev;
for (i = 0; i < WINDOWS_NR; i++) {
- ctx->configs[i].pixel_formats = fimd_formats;
- ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
- ctx->configs[i].zpos = i;
- ctx->configs[i].type = fimd_win_types[i];
- ctx->configs[i].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS
- | EXYNOS_DRM_PLANE_CAP_WIN_BLEND
- | EXYNOS_DRM_PLANE_CAP_PIX_BLEND;
-
- ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
- &ctx->configs[i]);
+ ctx->planes[i].index = i;
+ ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS
+ | EXYNOS_DRM_PLANE_CAP_WIN_BLEND
+ | EXYNOS_DRM_PLANE_CAP_PIX_BLEND;
+ ret = exynos_plane_init(drm_dev, &ctx->planes[i], fimd_formats,
+ ARRAY_SIZE(fimd_formats), fimd_win_types[i]);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index 8af0eba3f362..e1aa504539fa 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -138,7 +138,7 @@ static void exynos_drm_plane_reset(struct drm_plane *plane)
exynos_state = kzalloc(sizeof(*exynos_state), GFP_KERNEL);
if (exynos_state) {
__drm_atomic_helper_plane_reset(plane, &exynos_state->base);
- plane->state->zpos = exynos_plane->config->zpos;
+ plane->state->zpos = exynos_plane->index;
}
}
@@ -176,14 +176,14 @@ static struct drm_plane_funcs exynos_plane_funcs = {
};
static int
-exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config,
- struct exynos_drm_plane_state *state)
+exynos_drm_plane_check_format(struct exynos_drm_plane_state *state)
{
+ struct exynos_drm_plane *plane = to_exynos_plane(state->base.plane);
struct drm_framebuffer *fb = state->base.fb;
switch (fb->modifier) {
case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE:
- if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_TILE))
+ if (!(plane->capabilities & EXYNOS_DRM_PLANE_CAP_TILE))
return -ENOTSUPP;
break;
@@ -199,12 +199,12 @@ exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config,
}
static int
-exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config,
- struct exynos_drm_plane_state *state)
+exynos_drm_plane_check_size(struct exynos_drm_plane_state *state)
{
+ struct exynos_drm_plane *plane = to_exynos_plane(state->base.plane);
bool width_ok = false, height_ok = false;
- if (config->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE)
+ if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE)
return 0;
if (state->src.w == state->crtc.w)
@@ -213,11 +213,11 @@ exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config,
if (state->src.h == state->crtc.h)
height_ok = true;
- if ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) &&
+ if ((plane->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) &&
state->h_ratio == (1 << 15))
width_ok = true;
- if ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) &&
+ if ((plane->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) &&
state->v_ratio == (1 << 15))
height_ok = true;
@@ -231,7 +231,6 @@ exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config,
static int exynos_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
- struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
struct exynos_drm_plane_state *exynos_state =
to_exynos_plane_state(state);
int ret = 0;
@@ -242,11 +241,11 @@ static int exynos_plane_atomic_check(struct drm_plane *plane,
/* translate state into exynos_state */
exynos_plane_mode_set(exynos_state);
- ret = exynos_drm_plane_check_format(exynos_plane->config, exynos_state);
+ ret = exynos_drm_plane_check_format(exynos_state);
if (ret)
return ret;
- ret = exynos_drm_plane_check_size(exynos_plane->config, exynos_state);
+ ret = exynos_drm_plane_check_size(exynos_state);
return ret;
}
@@ -292,40 +291,37 @@ static void exynos_plane_attach_zpos_property(struct drm_plane *plane,
drm_plane_create_zpos_property(plane, zpos, 0, MAX_PLANE - 1);
}
-int exynos_plane_init(struct drm_device *dev,
- struct exynos_drm_plane *exynos_plane, unsigned int index,
- const struct exynos_drm_plane_config *config)
+int exynos_plane_init(struct drm_device *dev, struct exynos_drm_plane *plane,
+ const uint32_t *pixel_formats, int num_pixel_formats,
+ enum drm_plane_type type)
{
int err;
unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
BIT(DRM_MODE_BLEND_PREMULTI) |
BIT(DRM_MODE_BLEND_COVERAGE);
- struct drm_plane *plane = &exynos_plane->base;
+ struct drm_plane *bplane = &plane->base;
- err = drm_universal_plane_init(dev, &exynos_plane->base,
+ err = drm_universal_plane_init(dev, bplane,
1 << dev->mode_config.num_crtc,
&exynos_plane_funcs,
- config->pixel_formats,
- config->num_pixel_formats,
- NULL, config->type, NULL);
+ pixel_formats,
+ num_pixel_formats,
+ NULL, type, NULL);
if (err) {
DRM_ERROR("failed to initialize plane\n");
return err;
}
- drm_plane_helper_add(&exynos_plane->base, &plane_helper_funcs);
-
- exynos_plane->index = index;
- exynos_plane->config = config;
+ drm_plane_helper_add(bplane, &plane_helper_funcs);
- exynos_plane_attach_zpos_property(&exynos_plane->base, config->zpos,
- !(config->capabilities & EXYNOS_DRM_PLANE_CAP_ZPOS));
+ exynos_plane_attach_zpos_property(bplane, plane->index,
+ !(plane->capabilities & EXYNOS_DRM_PLANE_CAP_ZPOS));
- if (config->capabilities & EXYNOS_DRM_PLANE_CAP_PIX_BLEND)
- drm_plane_create_blend_mode_property(plane, supported_modes);
+ if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_PIX_BLEND)
+ drm_plane_create_blend_mode_property(bplane, supported_modes);
- if (config->capabilities & EXYNOS_DRM_PLANE_CAP_WIN_BLEND)
- drm_plane_create_alpha_property(plane);
+ if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_WIN_BLEND)
+ drm_plane_create_alpha_property(bplane);
return 0;
}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index ec30d5aca9aa..b61ae3415b8c 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -378,21 +378,14 @@ static int vidi_bind(struct device *dev, struct device *master, void *data)
struct drm_device *drm_dev = data;
struct drm_encoder *encoder = &ctx->encoder;
struct exynos_drm_plane *exynos_plane;
- struct exynos_drm_plane_config plane_config = { 0 };
unsigned int i;
int ret;
ctx->drm_dev = drm_dev;
- plane_config.pixel_formats = formats;
- plane_config.num_pixel_formats = ARRAY_SIZE(formats);
-
for (i = 0; i < WINDOWS_NR; i++) {
- plane_config.zpos = i;
- plane_config.type = vidi_win_types[i];
-
- ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
- &plane_config);
+ ret = exynos_plane_init(drm_dev, &ctx->planes[i], formats,
+ ARRAY_SIZE(formats), vidi_win_types[i]);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 1faa67fa7e5c..750f682e9c31 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -122,37 +122,6 @@ struct mixer_drv_data {
bool has_sclk;
};
-static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = {
- {
- .zpos = 0,
- .type = DRM_PLANE_TYPE_PRIMARY,
- .pixel_formats = mixer_formats,
- .num_pixel_formats = ARRAY_SIZE(mixer_formats),
- .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
- EXYNOS_DRM_PLANE_CAP_ZPOS |
- EXYNOS_DRM_PLANE_CAP_PIX_BLEND |
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
- }, {
- .zpos = 1,
- .type = DRM_PLANE_TYPE_CURSOR,
- .pixel_formats = mixer_formats,
- .num_pixel_formats = ARRAY_SIZE(mixer_formats),
- .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
- EXYNOS_DRM_PLANE_CAP_ZPOS |
- EXYNOS_DRM_PLANE_CAP_PIX_BLEND |
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
- }, {
- .zpos = 2,
- .type = DRM_PLANE_TYPE_OVERLAY,
- .pixel_formats = vp_formats,
- .num_pixel_formats = ARRAY_SIZE(vp_formats),
- .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE |
- EXYNOS_DRM_PLANE_CAP_ZPOS |
- EXYNOS_DRM_PLANE_CAP_TILE |
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
- },
-};
-
static const u8 filter_y_horiz_tap8[] = {
0, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, 0, 0, 0,
@@ -1151,18 +1120,33 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data)
struct exynos_drm_plane *exynos_plane;
unsigned int i;
int ret;
+ static enum drm_plane_type types[] = { DRM_PLANE_TYPE_PRIMARY,
+ DRM_PLANE_TYPE_CURSOR, DRM_PLANE_TYPE_OVERLAY };
ret = mixer_initialize(ctx, drm_dev);
if (ret)
return ret;
- for (i = 0; i < MIXER_WIN_NR; i++) {
- if (i == VP_DEFAULT_WIN && !test_bit(MXR_BIT_VP_ENABLED,
- &ctx->flags))
- continue;
+ for (i = 0; i < VP_DEFAULT_WIN; i++) {
+ ctx->planes[i].index = i;
+ ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
+ EXYNOS_DRM_PLANE_CAP_ZPOS |
+ EXYNOS_DRM_PLANE_CAP_PIX_BLEND |
+ EXYNOS_DRM_PLANE_CAP_WIN_BLEND;
+ ret = exynos_plane_init(drm_dev, &ctx->planes[i], mixer_formats,
+ ARRAY_SIZE(mixer_formats), types[i]);
+ if (ret)
+ return ret;
+ }
- ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
- &plane_configs[i]);
+ if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
+ ctx->planes[i].index = i;
+ ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_SCALE |
+ EXYNOS_DRM_PLANE_CAP_ZPOS |
+ EXYNOS_DRM_PLANE_CAP_TILE |
+ EXYNOS_DRM_PLANE_CAP_WIN_BLEND;
+ ret = exynos_plane_init(drm_dev, &ctx->planes[i], vp_formats,
+ ARRAY_SIZE(vp_formats), types[i]);
if (ret)
return ret;
}
--
2.17.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2019-03-20 13:07 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190320130711eucas1p2b9f18d009647652b4bb912fdd40c9f74@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 00/24] drm/exynos: add support for GSCALER planes on Exynos5433 Andrzej Hajda
[not found] ` <CGME20190320130712eucas1p2c98ef5f0f42d422dc711c222fa4da11b@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 01/24] drm/exynos: remove exynos_drm_plane.h header Andrzej Hajda
[not found] ` <CGME20190320130712eucas1p2f3735c6c5afd7117f297ce7f495e4479@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 02/24] drm/exynos: remove spare macro Andrzej Hajda
[not found] ` <CGME20190320130713eucas1p137746c8fcdf13bbe1c897c27a245b22a@eucas1p1.samsung.com>
2019-03-20 13:06 ` Andrzej Hajda [this message]
[not found] ` <CGME20190320130713eucas1p2dd57732ea0135355863ba26424a8bacf@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 04/24] drm/exynos: add exynos_drm_crtc_init function Andrzej Hajda
[not found] ` <CGME20190320130714eucas1p1c0b414ed76d7d0d78da56c9c0a6c8973@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 05/24] drm/exynos/decon5433: embed exynos_drm_crtc directly into context Andrzej Hajda
[not found] ` <CGME20190320130714eucas1p2e4f96fe67486283560c7b6a8627b769c@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 06/24] drm/exynos/decon7: " Andrzej Hajda
[not found] ` <CGME20190320130714eucas1p1d3ab6fceec849f22bab69df1e46b972d@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 07/24] drm/exynos/fimd: " Andrzej Hajda
[not found] ` <CGME20190320130715eucas1p250b6b902360896cd36bff8536b6292bf@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 08/24] drm/exynos/mixer: " Andrzej Hajda
[not found] ` <CGME20190320130715eucas1p2ab0449e8b243fcfa2d63524363eb8544@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 09/24] drm/exynos/vidi: " Andrzej Hajda
[not found] ` <CGME20190320130715eucas1p1cc35aa50021848a6f3d5459bb0c6d1bf@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 10/24] drm/exynos: remove standalone exynos_drm_crtc leftovers Andrzej Hajda
[not found] ` <CGME20190320130716eucas1p2fa37979f7715c411e079d146b96628cb@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 11/24] drm/exynos/vidi: remove encoder_to_vidi helper Andrzej Hajda
[not found] ` <CGME20190320130716eucas1p121bc6480ad28d1c0c79c195ae943ee55@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 12/24] drm/exynos: unify plane type assignment Andrzej Hajda
[not found] ` <CGME20190320130717eucas1p2a2a480a8c5d71fc66741410829a0d016@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 13/24] drm/exynos: set primary plane in exynos_drm_crtc_init Andrzej Hajda
[not found] ` <CGME20190320130717eucas1p2c75749455fa4b34b4d21f9873b3d9cb6@eucas1p2.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 14/24] drm/exynos: set cursor " Andrzej Hajda
[not found] ` <CGME20190320130718eucas1p15d440d88365fa5ea213f592b97e6f226@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 15/24] drm/exynos: add plane update/disable callbacks for planes Andrzej Hajda
[not found] ` <CGME20190320130718eucas1p1e42feb422bda24a2db733d50eb41ea47@eucas1p1.samsung.com>
2019-03-20 13:06 ` [PATCH v2 RESEND 16/24] drm/exynos: add GSCALER plane capability Andrzej Hajda
[not found] ` <CGME20190320130719eucas1p1b411bcd1e32a500202a19a24a4ba92a6@eucas1p1.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 17/24] drm/exynos/gscaler: fix id assignement Andrzej Hajda
[not found] ` <CGME20190320130719eucas1p274be59cfcd798d21ea583bc22f218ff7@eucas1p2.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 18/24] arm64: dts: exynos: configure GSCALER related clocks Andrzej Hajda
[not found] ` <CGME20190320130719eucas1p2e59268e628f6c88db6b632abb153313a@eucas1p2.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 19/24] arm64: dts: exynos: add DSD/GSD clocks to DECONs and GSCALERs Andrzej Hajda
[not found] ` <CGME20190320130720eucas1p1b6f2351c2262d2c89a464fdc10a6a607@eucas1p1.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 20/24] drm/exynos/gscaler: add local path support Andrzej Hajda
[not found] ` <CGME20190320130720eucas1p1f2b27e5d340a50dc710155b37e7b173b@eucas1p1.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 21/24] drm/exynos/decon5433: " Andrzej Hajda
[not found] ` <CGME20190320130721eucas1p2097f22c60919e45a10f9dff6dd678c99@eucas1p2.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 22/24] drm/exynos/decon5433: wait for finish previous update Andrzej Hajda
[not found] ` <CGME20190320130721eucas1p258d3ace8294e90446d369c1d45941dc9@eucas1p2.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 23/24] drm/exynos/gscaler: change supported color format BGRX8888 to XBGR8888 Andrzej Hajda
[not found] ` <CGME20190320130722eucas1p201e6452c3329fdbbc651051da9b14155@eucas1p2.samsung.com>
2019-03-20 13:07 ` [PATCH v2 RESEND 24/24] drm/exynos/gscaler: fix handling YVU420 pixel format Andrzej Hajda
2019-03-25 3:12 ` [PATCH v2 RESEND 00/24] drm/exynos: add support for GSCALER planes on Exynos5433 Inki Dae
2019-03-25 7:21 ` Andrzej Hajda
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190320130707.25161-4-a.hajda@samsung.com \
--to=a.hajda@samsung.com \
--cc=b.zolnierkie@samsung.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=inki.dae@samsung.com \
--cc=krzk@kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=m.szyprowski@samsung.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).