From: Matthew Brost <matthew.brost@intel.com>
To: John Harrison <john.c.harrison@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
daniel.vetter@ffwll.ch, tony.ye@intel.com, zhengguo.xu@intel.com
Subject: Re: [Intel-gfx] [PATCH 13/27] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts
Date: Wed, 15 Sep 2021 12:34:43 -0700 [thread overview]
Message-ID: <20210915193443.GA16098@jons-linux-dev-box> (raw)
In-Reply-To: <bc782f52-a19a-0a2e-a472-fb469858135b@intel.com>
On Wed, Sep 15, 2021 at 12:24:41PM -0700, John Harrison wrote:
> On 8/20/2021 15:44, Matthew Brost wrote:
> > In GuC parent-child contexts the parent context controls the scheduling,
> > ensure only the parent does the scheduling operations.
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 24 ++++++++++++++-----
> > 1 file changed, 18 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index dbcb9ab28a9a..00d54bb00bfb 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -320,6 +320,12 @@ static void decr_context_committed_requests(struct intel_context *ce)
> > GEM_BUG_ON(ce->guc_state.number_committed_requests < 0);
> > }
> > +static struct intel_context *
> > +request_to_scheduling_context(struct i915_request *rq)
> > +{
> > + return intel_context_to_parent(rq->context);
> > +}
> > +
> > static bool context_guc_id_invalid(struct intel_context *ce)
> > {
> > return ce->guc_id.id == GUC_INVALID_LRC_ID;
> > @@ -1684,6 +1690,7 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
> > GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
> > + GEM_BUG_ON(intel_context_is_child(ce));
> > trace_intel_context_sched_disable(ce);
> > guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
> > @@ -1898,6 +1905,8 @@ static void guc_context_sched_disable(struct intel_context *ce)
> > u16 guc_id;
> > bool enabled;
> > + GEM_BUG_ON(intel_context_is_child(ce));
> > +
> > if (submission_disabled(guc) || context_guc_id_invalid(ce) ||
> > !lrc_desc_registered(guc, ce->guc_id.id)) {
> > spin_lock_irqsave(&ce->guc_state.lock, flags);
> > @@ -2286,6 +2295,8 @@ static void guc_signal_context_fence(struct intel_context *ce)
> > {
> > unsigned long flags;
> > + GEM_BUG_ON(intel_context_is_child(ce));
> > +
> > spin_lock_irqsave(&ce->guc_state.lock, flags);
> > clr_context_wait_for_deregister_to_register(ce);
> > __guc_signal_context_fence(ce);
> > @@ -2315,7 +2326,7 @@ static void guc_context_init(struct intel_context *ce)
> > static int guc_request_alloc(struct i915_request *rq)
> > {
> > - struct intel_context *ce = rq->context;
> > + struct intel_context *ce = request_to_scheduling_context(rq);
> > struct intel_guc *guc = ce_to_guc(ce);
> > unsigned long flags;
> > int ret;
> > @@ -2358,11 +2369,12 @@ static int guc_request_alloc(struct i915_request *rq)
> > * exhausted and return -EAGAIN to the user indicating that they can try
> > * again in the future.
> > *
> > - * There is no need for a lock here as the timeline mutex ensures at
> > - * most one context can be executing this code path at once. The
> > - * guc_id_ref is incremented once for every request in flight and
> > - * decremented on each retire. When it is zero, a lock around the
> > - * increment (in pin_guc_id) is needed to seal a race with unpin_guc_id.
> > + * There is no need for a lock here as the timeline mutex (or
> > + * parallel_submit mutex in the case of multi-lrc) ensures at most one
> > + * context can be executing this code path at once. The guc_id_ref is
> Isn't that now two? One uni-LRC holding the timeline mutex and one multi-LRC
> holding the parallel submit mutex?
>
This is actually a stale comment and need scrub this. The
parallel_submit mutex is gone, now we grab the ce->timeline locks
starting at the parent and then all children in a loop. I think the
original comment is sufficient.
Matt
> John.
>
> > + * incremented once for every request in flight and decremented on each
> > + * retire. When it is zero, a lock around the increment (in pin_guc_id)
> > + * is needed to seal a race with unpin_guc_id.
> > */
> > if (atomic_add_unless(&ce->guc_id.ref, 1, 0))
> > goto out;
>
next prev parent reply other threads:[~2021-09-15 19:39 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 22:44 [PATCH 00/27] Parallel submission aka multi-bb execbuf Matthew Brost
2021-08-20 22:44 ` [PATCH 01/27] drm/i915/guc: Squash Clean up GuC CI failures, simplify locking, and kernel DOC Matthew Brost
2021-08-20 22:44 ` [PATCH 02/27] drm/i915/guc: Allow flexible number of context ids Matthew Brost
2021-09-09 22:13 ` [Intel-gfx] " John Harrison
2021-09-10 0:14 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 03/27] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost
2021-09-09 22:16 ` [Intel-gfx] " John Harrison
2021-09-10 0:16 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 04/27] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-09-09 22:28 ` [Intel-gfx] " John Harrison
2021-09-10 0:21 ` Matthew Brost
2021-09-13 9:55 ` Tvrtko Ursulin
2021-09-13 17:12 ` Matthew Brost
2021-09-14 8:41 ` Tvrtko Ursulin
2021-08-20 22:44 ` [PATCH 05/27] drm/i915: Add GT PM unpark worker Matthew Brost
2021-09-09 22:36 ` [Intel-gfx] " John Harrison
2021-09-10 0:34 ` Matthew Brost
2021-09-10 8:36 ` Tvrtko Ursulin
2021-09-10 20:09 ` Matthew Brost
2021-09-13 10:33 ` Tvrtko Ursulin
2021-09-13 17:20 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 06/27] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost
2021-09-09 22:46 ` [Intel-gfx] " John Harrison
2021-09-10 0:41 ` Matthew Brost
2021-09-13 22:26 ` John Harrison
2021-09-14 1:12 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 07/27] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost
2021-09-09 22:51 ` [Intel-gfx] " John Harrison
2021-09-13 16:54 ` Matthew Brost
2021-09-13 22:38 ` John Harrison
2021-09-14 5:02 ` Matthew Brost
2021-09-13 16:55 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 08/27] drm/i915: Add logical engine mapping Matthew Brost
2021-09-10 11:12 ` [Intel-gfx] " Tvrtko Ursulin
2021-09-10 19:49 ` Matthew Brost
2021-09-13 9:24 ` Tvrtko Ursulin
2021-09-13 16:50 ` Matthew Brost
2021-09-14 8:34 ` Tvrtko Ursulin
2021-09-14 18:04 ` Matthew Brost
2021-09-15 8:24 ` Tvrtko Ursulin
2021-09-15 16:58 ` Matthew Brost
2021-09-16 8:31 ` Tvrtko Ursulin
2021-08-20 22:44 ` [PATCH 09/27] drm/i915: Expose logical engine instance to user Matthew Brost
2021-09-13 23:06 ` [Intel-gfx] " John Harrison
2021-09-14 1:08 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 10/27] drm/i915/guc: Introduce context parent-child relationship Matthew Brost
2021-09-13 23:19 ` [Intel-gfx] " John Harrison
2021-09-14 1:18 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 11/27] drm/i915/guc: Implement parallel context pin / unpin functions Matthew Brost
2021-08-20 22:44 ` [PATCH 12/27] drm/i915/guc: Add multi-lrc context registration Matthew Brost
2021-09-15 19:21 ` [Intel-gfx] " John Harrison
2021-09-15 19:31 ` Matthew Brost
2021-09-15 20:23 ` John Harrison
2021-09-15 20:33 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 13/27] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts Matthew Brost
2021-09-15 19:24 ` [Intel-gfx] " John Harrison
2021-09-15 19:34 ` Matthew Brost [this message]
2021-08-20 22:44 ` [PATCH 14/27] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids Matthew Brost
2021-09-15 20:04 ` [Intel-gfx] " John Harrison
2021-09-15 20:55 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 15/27] drm/i915/guc: Implement multi-lrc submission Matthew Brost
2021-08-21 14:04 ` kernel test robot
2021-08-22 2:18 ` kernel test robot
2021-09-20 21:48 ` [Intel-gfx] " John Harrison
2021-09-22 16:25 ` Matthew Brost
2021-09-22 20:15 ` John Harrison
2021-09-23 2:44 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 16/27] drm/i915/guc: Insert submit fences between requests in parent-child relationship Matthew Brost
2021-09-20 21:57 ` [Intel-gfx] " John Harrison
2021-08-20 22:44 ` [PATCH 17/27] drm/i915/guc: Implement multi-lrc reset Matthew Brost
2021-09-20 22:44 ` [Intel-gfx] " John Harrison
2021-09-22 16:16 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 18/27] drm/i915/guc: Update debugfs for GuC multi-lrc Matthew Brost
2021-09-20 22:48 ` [Intel-gfx] " John Harrison
2021-09-21 19:13 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 19/27] drm/i915: Fix bug in user proto-context creation that leaked contexts Matthew Brost
2021-09-20 22:57 ` [Intel-gfx] " John Harrison
2021-09-21 14:49 ` Tvrtko Ursulin
2021-09-21 19:28 ` Matthew Brost
2021-09-21 19:28 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 20/27] drm/i915/guc: Connect UAPI to GuC multi-lrc interface Matthew Brost
2021-08-29 4:00 ` [Intel-gfx] " kernel test robot
2021-08-29 19:59 ` kernel test robot
2021-09-21 0:09 ` John Harrison
2021-09-22 16:38 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 21/27] drm/i915/doc: Update parallel submit doc to point to i915_drm.h Matthew Brost
2021-09-21 0:12 ` [Intel-gfx] " John Harrison
2021-08-20 22:44 ` [PATCH 22/27] drm/i915/guc: Add basic GuC multi-lrc selftest Matthew Brost
2021-09-28 20:47 ` [Intel-gfx] " John Harrison
2021-08-20 22:44 ` [PATCH 23/27] drm/i915/guc: Implement no mid batch preemption for multi-lrc Matthew Brost
2021-09-10 11:25 ` [Intel-gfx] " Tvrtko Ursulin
2021-09-10 20:49 ` Matthew Brost
2021-09-13 10:52 ` Tvrtko Ursulin
2021-09-28 22:20 ` John Harrison
2021-09-28 22:33 ` Matthew Brost
2021-09-28 23:33 ` John Harrison
2021-09-29 0:22 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 24/27] drm/i915: Multi-BB execbuf Matthew Brost
2021-08-21 19:01 ` [Intel-gfx] " kernel test robot
2021-08-30 3:46 ` kernel test robot
2021-09-30 22:16 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 25/27] drm/i915/guc: Handle errors in multi-lrc requests Matthew Brost
2021-09-29 20:44 ` [Intel-gfx] " John Harrison
2021-09-29 20:58 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 26/27] drm/i915: Enable multi-bb execbuf Matthew Brost
2021-08-20 22:44 ` [PATCH 27/27] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost
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