From: John Harrison <john.c.harrison@intel.com>
To: Matthew Brost <matthew.brost@intel.com>,
<intel-gfx@lists.freedesktop.org>,
<dri-devel@lists.freedesktop.org>
Cc: <daniel.vetter@ffwll.ch>, <tony.ye@intel.com>, <zhengguo.xu@intel.com>
Subject: Re: [Intel-gfx] [PATCH 21/27] drm/i915/doc: Update parallel submit doc to point to i915_drm.h
Date: Mon, 20 Sep 2021 17:12:51 -0700 [thread overview]
Message-ID: <f0cb41ed-c69e-0aaa-68a7-4253b134d81a@intel.com> (raw)
In-Reply-To: <20210820224446.30620-22-matthew.brost@intel.com>
On 8/20/2021 15:44, Matthew Brost wrote:
> Update parallel submit doc to point to i915_drm.h
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> Documentation/gpu/rfc/i915_parallel_execbuf.h | 122 ------------------
> Documentation/gpu/rfc/i915_scheduler.rst | 4 +-
> 2 files changed, 2 insertions(+), 124 deletions(-)
> delete mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>
> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> deleted file mode 100644
> index 8cbe2c4e0172..000000000000
> --- a/Documentation/gpu/rfc/i915_parallel_execbuf.h
> +++ /dev/null
> @@ -1,122 +0,0 @@
> -/* SPDX-License-Identifier: MIT */
> -/*
> - * Copyright © 2021 Intel Corporation
> - */
> -
> -#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> -
> -/**
> - * struct drm_i915_context_engines_parallel_submit - Configure engine for
> - * parallel submission.
> - *
> - * Setup a slot in the context engine map to allow multiple BBs to be submitted
> - * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU
> - * in parallel. Multiple hardware contexts are created internally in the i915
> - * run these BBs. Once a slot is configured for N BBs only N BBs can be
> - * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user
> - * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how
> - * many BBs there are based on the slot's configuration. The N BBs are the last
> - * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
> - *
> - * The default placement behavior is to create implicit bonds between each
> - * context if each context maps to more than 1 physical engine (e.g. context is
> - * a virtual engine). Also we only allow contexts of same engine class and these
> - * contexts must be in logically contiguous order. Examples of the placement
> - * behavior described below. Lastly, the default is to not allow BBs to
> - * preempted mid BB rather insert coordinated preemption on all hardware
> - * contexts between each set of BBs. Flags may be added in the future to change
> - * both of these default behaviors.
> - *
> - * Returns -EINVAL if hardware context placement configuration is invalid or if
> - * the placement configuration isn't supported on the platform / submission
> - * interface.
> - * Returns -ENODEV if extension isn't supported on the platform / submission
> - * interface.
> - *
> - * .. code-block:: none
> - *
> - * Example 1 pseudo code:
> - * CS[X] = generic engine of same class, logical instance X
> - * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> - * set_engines(INVALID)
> - * set_parallel(engine_index=0, width=2, num_siblings=1,
> - * engines=CS[0],CS[1])
> - *
> - * Results in the following valid placement:
> - * CS[0], CS[1]
> - *
> - * Example 2 pseudo code:
> - * CS[X] = generic engine of same class, logical instance X
> - * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> - * set_engines(INVALID)
> - * set_parallel(engine_index=0, width=2, num_siblings=2,
> - * engines=CS[0],CS[2],CS[1],CS[3])
> - *
> - * Results in the following valid placements:
> - * CS[0], CS[1]
> - * CS[2], CS[3]
> - *
> - * This can also be thought of as 2 virtual engines described by 2-D array
> - * in the engines the field with bonds placed between each index of the
> - * virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to
> - * CS[3].
> - * VE[0] = CS[0], CS[2]
> - * VE[1] = CS[1], CS[3]
> - *
> - * Example 3 pseudo code:
> - * CS[X] = generic engine of same class, logical instance X
> - * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> - * set_engines(INVALID)
> - * set_parallel(engine_index=0, width=2, num_siblings=2,
> - * engines=CS[0],CS[1],CS[1],CS[3])
> - *
> - * Results in the following valid and invalid placements:
> - * CS[0], CS[1]
> - * CS[1], CS[3] - Not logical contiguous, return -EINVAL
> - */
> -struct drm_i915_context_engines_parallel_submit {
> - /**
> - * @base: base user extension.
> - */
> - struct i915_user_extension base;
> -
> - /**
> - * @engine_index: slot for parallel engine
> - */
> - __u16 engine_index;
> -
> - /**
> - * @width: number of contexts per parallel engine
> - */
> - __u16 width;
> -
> - /**
> - * @num_siblings: number of siblings per context
> - */
> - __u16 num_siblings;
> -
> - /**
> - * @mbz16: reserved for future use; must be zero
> - */
> - __u16 mbz16;
> -
> - /**
> - * @flags: all undefined flags must be zero, currently not defined flags
> - */
> - __u64 flags;
> -
> - /**
> - * @mbz64: reserved for future use; must be zero
> - */
> - __u64 mbz64[3];
> -
> - /**
> - * @engines: 2-d array of engine instances to configure parallel engine
> - *
> - * length = width (i) * num_siblings (j)
> - * index = j + i * num_siblings
> - */
> - struct i915_engine_class_instance engines[0];
> -
> -} __packed;
> -
> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> index cbda75065dad..d630f15ab795 100644
> --- a/Documentation/gpu/rfc/i915_scheduler.rst
> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> @@ -135,8 +135,8 @@ Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> drm_i915_context_engines_parallel_submit to the uAPI to implement this
> extension.
>
> -.. kernel-doc:: Documentation/gpu/rfc/i915_parallel_execbuf.h
> - :functions: drm_i915_context_engines_parallel_submit
> +.. kernel-doc:: include/uapi/drm/i915_drm.h
> + :functions: i915_context_engines_parallel_submit
>
> Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> -------------------------------------------------------------------
next prev parent reply other threads:[~2021-09-21 0:14 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 22:44 [PATCH 00/27] Parallel submission aka multi-bb execbuf Matthew Brost
2021-08-20 22:44 ` [PATCH 01/27] drm/i915/guc: Squash Clean up GuC CI failures, simplify locking, and kernel DOC Matthew Brost
2021-08-20 22:44 ` [PATCH 02/27] drm/i915/guc: Allow flexible number of context ids Matthew Brost
2021-09-09 22:13 ` [Intel-gfx] " John Harrison
2021-09-10 0:14 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 03/27] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost
2021-09-09 22:16 ` [Intel-gfx] " John Harrison
2021-09-10 0:16 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 04/27] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-09-09 22:28 ` [Intel-gfx] " John Harrison
2021-09-10 0:21 ` Matthew Brost
2021-09-13 9:55 ` Tvrtko Ursulin
2021-09-13 17:12 ` Matthew Brost
2021-09-14 8:41 ` Tvrtko Ursulin
2021-08-20 22:44 ` [PATCH 05/27] drm/i915: Add GT PM unpark worker Matthew Brost
2021-09-09 22:36 ` [Intel-gfx] " John Harrison
2021-09-10 0:34 ` Matthew Brost
2021-09-10 8:36 ` Tvrtko Ursulin
2021-09-10 20:09 ` Matthew Brost
2021-09-13 10:33 ` Tvrtko Ursulin
2021-09-13 17:20 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 06/27] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost
2021-09-09 22:46 ` [Intel-gfx] " John Harrison
2021-09-10 0:41 ` Matthew Brost
2021-09-13 22:26 ` John Harrison
2021-09-14 1:12 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 07/27] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost
2021-09-09 22:51 ` [Intel-gfx] " John Harrison
2021-09-13 16:54 ` Matthew Brost
2021-09-13 22:38 ` John Harrison
2021-09-14 5:02 ` Matthew Brost
2021-09-13 16:55 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 08/27] drm/i915: Add logical engine mapping Matthew Brost
2021-09-10 11:12 ` [Intel-gfx] " Tvrtko Ursulin
2021-09-10 19:49 ` Matthew Brost
2021-09-13 9:24 ` Tvrtko Ursulin
2021-09-13 16:50 ` Matthew Brost
2021-09-14 8:34 ` Tvrtko Ursulin
2021-09-14 18:04 ` Matthew Brost
2021-09-15 8:24 ` Tvrtko Ursulin
2021-09-15 16:58 ` Matthew Brost
2021-09-16 8:31 ` Tvrtko Ursulin
2021-08-20 22:44 ` [PATCH 09/27] drm/i915: Expose logical engine instance to user Matthew Brost
2021-09-13 23:06 ` [Intel-gfx] " John Harrison
2021-09-14 1:08 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 10/27] drm/i915/guc: Introduce context parent-child relationship Matthew Brost
2021-09-13 23:19 ` [Intel-gfx] " John Harrison
2021-09-14 1:18 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 11/27] drm/i915/guc: Implement parallel context pin / unpin functions Matthew Brost
2021-08-20 22:44 ` [PATCH 12/27] drm/i915/guc: Add multi-lrc context registration Matthew Brost
2021-09-15 19:21 ` [Intel-gfx] " John Harrison
2021-09-15 19:31 ` Matthew Brost
2021-09-15 20:23 ` John Harrison
2021-09-15 20:33 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 13/27] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts Matthew Brost
2021-09-15 19:24 ` [Intel-gfx] " John Harrison
2021-09-15 19:34 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 14/27] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids Matthew Brost
2021-09-15 20:04 ` [Intel-gfx] " John Harrison
2021-09-15 20:55 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 15/27] drm/i915/guc: Implement multi-lrc submission Matthew Brost
2021-08-21 14:04 ` kernel test robot
2021-08-22 2:18 ` kernel test robot
2021-09-20 21:48 ` [Intel-gfx] " John Harrison
2021-09-22 16:25 ` Matthew Brost
2021-09-22 20:15 ` John Harrison
2021-09-23 2:44 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 16/27] drm/i915/guc: Insert submit fences between requests in parent-child relationship Matthew Brost
2021-09-20 21:57 ` [Intel-gfx] " John Harrison
2021-08-20 22:44 ` [PATCH 17/27] drm/i915/guc: Implement multi-lrc reset Matthew Brost
2021-09-20 22:44 ` [Intel-gfx] " John Harrison
2021-09-22 16:16 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 18/27] drm/i915/guc: Update debugfs for GuC multi-lrc Matthew Brost
2021-09-20 22:48 ` [Intel-gfx] " John Harrison
2021-09-21 19:13 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 19/27] drm/i915: Fix bug in user proto-context creation that leaked contexts Matthew Brost
2021-09-20 22:57 ` [Intel-gfx] " John Harrison
2021-09-21 14:49 ` Tvrtko Ursulin
2021-09-21 19:28 ` Matthew Brost
2021-09-21 19:28 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 20/27] drm/i915/guc: Connect UAPI to GuC multi-lrc interface Matthew Brost
2021-08-29 4:00 ` [Intel-gfx] " kernel test robot
2021-08-29 19:59 ` kernel test robot
2021-09-21 0:09 ` John Harrison
2021-09-22 16:38 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 21/27] drm/i915/doc: Update parallel submit doc to point to i915_drm.h Matthew Brost
2021-09-21 0:12 ` John Harrison [this message]
2021-08-20 22:44 ` [PATCH 22/27] drm/i915/guc: Add basic GuC multi-lrc selftest Matthew Brost
2021-09-28 20:47 ` [Intel-gfx] " John Harrison
2021-08-20 22:44 ` [PATCH 23/27] drm/i915/guc: Implement no mid batch preemption for multi-lrc Matthew Brost
2021-09-10 11:25 ` [Intel-gfx] " Tvrtko Ursulin
2021-09-10 20:49 ` Matthew Brost
2021-09-13 10:52 ` Tvrtko Ursulin
2021-09-28 22:20 ` John Harrison
2021-09-28 22:33 ` Matthew Brost
2021-09-28 23:33 ` John Harrison
2021-09-29 0:22 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 24/27] drm/i915: Multi-BB execbuf Matthew Brost
2021-08-21 19:01 ` [Intel-gfx] " kernel test robot
2021-08-30 3:46 ` kernel test robot
2021-09-30 22:16 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 25/27] drm/i915/guc: Handle errors in multi-lrc requests Matthew Brost
2021-09-29 20:44 ` [Intel-gfx] " John Harrison
2021-09-29 20:58 ` Matthew Brost
2021-08-20 22:44 ` [PATCH 26/27] drm/i915: Enable multi-bb execbuf Matthew Brost
2021-08-20 22:44 ` [PATCH 27/27] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost
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