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* [PATCH] drm/meson: Fix OSD1 RGB to YCbCr coefficient
@ 2022-09-08 15:52 Stuart Menefy
  2022-09-09 11:30 ` Neil Armstrong
  2022-09-09 11:36 ` Neil Armstrong
  0 siblings, 2 replies; 3+ messages in thread
From: Stuart Menefy @ 2022-09-08 15:52 UTC (permalink / raw)
  To: Neil Armstrong, dri-devel, linux-amlogic; +Cc: Stuart Menefy

VPP_WRAP_OSD1_MATRIX_COEF22.Coeff22 is documented as being bits 0-12,
not 16-28.

Without this the output tends to have a pink hue, changing it results
in better color accuracy.

The vendor kernel doesn't use this register. However the code which
sets VIU2_OSD1_MATRIX_COEF22 also uses bits 0-12. There is a slightly
different style of registers for configuring some of the other matrices,
which do use bits 16-28 for this coefficient, but those have names
ending in MATRIX_COEF22_30, and this is not one of those.

Signed-off-by: Stuart Menefy <stuart.menefy@mathembedded.com>
---
 drivers/gpu/drm/meson/meson_viu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index 51df4de..876ffe0 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -94,7 +94,7 @@ static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv,
 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12));
 	writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21));
-	writel((m[11] & 0x1fff) << 16,
+	writel((m[11] & 0x1fff),
 		priv->io_base +	_REG(VPP_WRAP_OSD1_MATRIX_COEF22));
 
 	writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
-- 
2.7.4


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2022-09-08 15:52 [PATCH] drm/meson: Fix OSD1 RGB to YCbCr coefficient Stuart Menefy
2022-09-09 11:30 ` Neil Armstrong
2022-09-09 11:36 ` Neil Armstrong

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