* [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
2022-11-08 17:46 ` Matthias Brugger
2022-11-23 16:06 ` Krzysztof Kozlowski
2022-11-07 7:22 ` [PATCH v28 02/11] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
` (9 subsequent siblings)
10 siblings, 2 replies; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
Add vdosys1 mmsys compatible for MT8195 platform.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 0711f1834fbd..aaabe2196185 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -48,7 +48,9 @@ properties:
- const: syscon
- items:
- - const: mediatek,mt8195-vdosys0
+ - enum:
+ - mediatek,mt8195-vdosys0
+ - mediatek,mt8195-vdosys1
- const: mediatek,mt8195-mmsys
- const: syscon
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
2022-11-07 7:22 ` [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195 Nancy.Lin
@ 2022-11-08 17:46 ` Matthias Brugger
2022-11-09 5:10 ` Jason-JH Lin (林睿祥)
2022-11-23 16:06 ` Krzysztof Kozlowski
1 sibling, 1 reply; 30+ messages in thread
From: Matthias Brugger @ 2022-11-08 17:46 UTC (permalink / raw)
To: Nancy.Lin, Rob Herring, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, David Airlie,
jason-jh . lin, singo.chang, llvm, Nick Desaulniers,
linux-kernel, dri-devel, Nathan Chancellor, linux-mediatek,
Yongqiang Niu, linux-arm-kernel
On 07/11/2022 08:22, Nancy.Lin wrote:
> Add vdosys1 mmsys compatible for MT8195 platform.
>
> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
> 2 different power domains, different clock drivers and different
> mediatek-drm drivers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
> .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index 0711f1834fbd..aaabe2196185 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -48,7 +48,9 @@ properties:
> - const: syscon
>
> - items:
> - - const: mediatek,mt8195-vdosys0
> + - enum:
> + - mediatek,mt8195-vdosys0
> + - mediatek,mt8195-vdosys1
> - const: mediatek,mt8195-mmsys
> - const: syscon
>
I think we had that several times already:
https://lore.kernel.org/all/6bbe9527-ae48-30e0-fb45-519223a744d7@linaro.org/
We will something like this, but please check that this does not give any
errors/warnings:
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index eb451bec23d3d..8e9c4f4d7c389 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -32,13 +32,22 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
- - mediatek,mt8195-mmsys
- mediatek,mt8365-mmsys
- const: syscon
- items:
- const: mediatek,mt7623-mmsys
- const: mediatek,mt2701-mmsys
- const: syscon
+ - items:
+ - const: mediatek,mt8195-vdosys0
+ - const: syscon
+ - items:
+ - const: mediatek,mt8195-vdosys1
+ - const: syscon
+ - items:
+ - const: mediatek,mt8195-mmsys
+ - const: syscon
+ deprecated: true
reg:
maxItems: 1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
2022-11-08 17:46 ` Matthias Brugger
@ 2022-11-09 5:10 ` Jason-JH Lin (林睿祥)
2022-11-10 13:10 ` Matthias Brugger
0 siblings, 1 reply; 30+ messages in thread
From: Jason-JH Lin (林睿祥) @ 2022-11-09 5:10 UTC (permalink / raw)
To: robh+dt, chunkuang.hu, linux,
Nancy Lin (林欣螢),
p.zabel, wim, matthias.bgg, angelogioacchino.delregno, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, airlied,
Singo Chang (張興國),
llvm, ndesaulniers, linux-kernel, dri-devel, nathan,
linux-mediatek, Yongqiang Niu (牛永强),
linux-arm-kernel
[-- Attachment #1: Type: text/html, Size: 7057 bytes --]
[-- Attachment #2: Type: text/plain, Size: 3202 bytes --]
On Tue, 2022-11-08 at 18:46 +0100, Matthias Brugger wrote:
>
> On 07/11/2022 08:22, Nancy.Lin wrote:
> > Add vdosys1 mmsys compatible for MT8195 platform.
> >
> > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
> > to
> > 2 different power domains, different clock drivers and different
> > mediatek-drm drivers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > ---
> > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4
> > +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > index 0711f1834fbd..aaabe2196185 100644
> > ---
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > @@ -48,7 +48,9 @@ properties:
> > - const: syscon
> >
> > - items:
> > - - const: mediatek,mt8195-vdosys0
> > + - enum:
> > + - mediatek,mt8195-vdosys0
> > + - mediatek,mt8195-vdosys1
> > - const: mediatek,mt8195-mmsys
> > - const: syscon
> >
>
> I think we had that several times already:
>
https://lore.kernel.org/all/6bbe9527-ae48-30e0-fb45-519223a744d7@linaro.org/
>
> We will something like this, but please check that this does not give
> any
> errors/warnings:
>
> diff --git
> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index eb451bec23d3d..8e9c4f4d7c389 100644
> ---
> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++
> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -32,13 +32,22 @@ properties:
> - mediatek,mt8183-mmsys
> - mediatek,mt8186-mmsys
> - mediatek,mt8192-mmsys
> - - mediatek,mt8195-mmsys
> - mediatek,mt8365-mmsys
> - const: syscon
> - items:
> - const: mediatek,mt7623-mmsys
> - const: mediatek,mt2701-mmsys
> - const: syscon
> + - items:
> + - const: mediatek,mt8195-vdosys0
> + - const: syscon
> + - items:
> + - const: mediatek,mt8195-vdosys1
> + - const: syscon
> + - items:
> + - const: mediatek,mt8195-mmsys
> + - const: syscon
> + deprecated: true
>
> reg:
> maxItems: 1
Hi Matthias,
As the vdosys0 previous reviewed patch:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220927152704.12018-2-jason-jh.lin@mediatek.com/
Should I modify the vdosys0 items format like your example?
Or should vdosys1 add items format like vdosys0's previous patch?
- items:
- const: mediatek,mt8195-vdosys1
- const: mediatek,mt8195-mmsys
- const: syscon
Regards,
Jason-JH.Lin
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
2022-11-09 5:10 ` Jason-JH Lin (林睿祥)
@ 2022-11-10 13:10 ` Matthias Brugger
2022-11-22 10:51 ` Nancy Lin (林欣螢)
0 siblings, 1 reply; 30+ messages in thread
From: Matthias Brugger @ 2022-11-10 13:10 UTC (permalink / raw)
To: Jason-JH Lin (林睿祥),
robh+dt, chunkuang.hu, linux,
Nancy Lin (林欣螢),
p.zabel, wim, angelogioacchino.delregno, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, airlied,
Singo Chang (張興國),
llvm, ndesaulniers, linux-kernel, dri-devel, nathan,
linux-mediatek, Yongqiang Niu (牛永强),
linux-arm-kernel
On 09/11/2022 06:10, Jason-JH Lin (林睿祥) wrote:
> On Tue, 2022-11-08 at 18:46 +0100, Matthias Brugger wrote:
>>
>> On 07/11/2022 08:22, Nancy.Lin wrote:
>> > Add vdosys1 mmsys compatible for MT8195 platform.
>> >
>> > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
>> > to
>> > 2 different power domains, different clock drivers and different
>> > mediatek-drm drivers.
>> >
>> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
>> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>> > ---
>> > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4
>> > +++-
>> > 1 file changed, 3 insertions(+), 1 deletion(-)
>> >
>> > diff --git
>> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
>> > l
>> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
>> > l
>> > index 0711f1834fbd..aaabe2196185 100644
>> > ---
>> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
>> > l
>> > +++
>> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
>> > l
>> > @@ -48,7 +48,9 @@ properties:
>> > - const: syscon
>> >
>> > - items:
>> > - - const: mediatek,mt8195-vdosys0
>> > + - enum:
>> > + - mediatek,mt8195-vdosys0
>> > + - mediatek,mt8195-vdosys1
>> > - const: mediatek,mt8195-mmsys
>> > - const: syscon
>> >
>>
>> I think we had that several times already:
>>
> https://lore.kernel.org/all/6bbe9527-ae48-30e0-fb45-519223a744d7@linaro.org/
>>
>> We will something like this, but please check that this does not give
>> any
>> errors/warnings:
>>
>> diff --git
>> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
>> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
>> index eb451bec23d3d..8e9c4f4d7c389 100644
>> ---
>> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
>> +++
>> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
>> @@ -32,13 +32,22 @@ properties:
>> - mediatek,mt8183-mmsys
>> - mediatek,mt8186-mmsys
>> - mediatek,mt8192-mmsys
>> - - mediatek,mt8195-mmsys
>> - mediatek,mt8365-mmsys
>> - const: syscon
>> - items:
>> - const: mediatek,mt7623-mmsys
>> - const: mediatek,mt2701-mmsys
>> - const: syscon
>> + - items:
>> + - const: mediatek,mt8195-vdosys0
>> + - const: syscon
>> + - items:
>> + - const: mediatek,mt8195-vdosys1
>> + - const: syscon
>> + - items:
>> + - const: mediatek,mt8195-mmsys
>> + - const: syscon
>> + deprecated: true
>>
>> reg:
>> maxItems: 1
>
> Hi Matthias,
>
> As the vdosys0 previous reviewed patch:
>
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220927152704.12018-2-jason-jh.lin@mediatek.com/
> Should I modify the vdosys0 items format like your example?
>
> Or should vdosys1 add items format like vdosys0's previous patch?
> - items:
> - const: mediatek,mt8195-vdosys1
> - const: mediatek,mt8195-mmsys
> - const: syscon
>
No, vdosys1 must not have mediatek,mt8195-mmsys fallback.
Regards,
Matthias
> Regards,
> Jason-JH.Lin
>
>
>
> ************* MEDIATEK Confidentiality Notice
> ********************
> The information contained in this e-mail message (including any
> attachments) may be confidential, proprietary, privileged, or otherwise
> exempt from disclosure under applicable laws. It is intended to be
> conveyed only to the designated recipient(s). Any use, dissemination,
> distribution, printing, retaining or copying of this e-mail (including its
> attachments) by unintended recipient(s) is strictly prohibited and may
> be unlawful. If you are not an intended recipient of this e-mail, or believe
>
> that you have received this e-mail in error, please notify the sender
> immediately (by replying to this e-mail), delete any and all copies of
> this e-mail (including any attachments) from your system, and do not
> disclose the content of this e-mail to any other person. Thank you!
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
2022-11-10 13:10 ` Matthias Brugger
@ 2022-11-22 10:51 ` Nancy Lin (林欣螢)
2022-11-22 15:48 ` Matthias Brugger
0 siblings, 1 reply; 30+ messages in thread
From: Nancy Lin (林欣螢) @ 2022-11-22 10:51 UTC (permalink / raw)
To: robh+dt, Jason-JH Lin (林睿祥),
chunkuang.hu, linux, p.zabel, wim, matthias.bgg,
angelogioacchino.delregno, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, airlied,
Singo Chang (張興國),
llvm, ndesaulniers, linux-kernel, dri-devel, nathan,
linux-mediatek, Yongqiang Niu (牛永强),
linux-arm-kernel
[-- Attachment #1: Type: text/html, Size: 13312 bytes --]
[-- Attachment #2: Type: text/plain, Size: 5955 bytes --]
Dear Matthias,
Thanks for the review.
On Thu, 2022-11-10 at 14:10 +0100, Matthias Brugger wrote:
>
> On 09/11/2022 06:10, Jason-JH Lin (林睿祥) wrote:
> > On Tue, 2022-11-08 at 18:46 +0100, Matthias Brugger wrote:
> > >
> > > On 07/11/2022 08:22, Nancy.Lin wrote:
> > > > Add vdosys1 mmsys compatible for MT8195 platform.
> > > >
> > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines
> > > > binding
> > > > to
> > > > 2 different power domains, different clock drivers and
> > > > different
> > > > mediatek-drm drivers.
> > > >
> > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > > > ---
> > > >
> > > > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml |
> > > > 4
> > > > +++-
> > > > 1 file changed, 3 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > index 0711f1834fbd..aaabe2196185 100644
> > > > ---
> > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > +++
> > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > @@ -48,7 +48,9 @@ properties:
> > > > - const: syscon
> > > >
> > > > - items:
> > > > - - const: mediatek,mt8195-vdosys0
> > > > + - enum:
> > > > + - mediatek,mt8195-vdosys0
> > > > + - mediatek,mt8195-vdosys1
> > > > - const: mediatek,mt8195-mmsys
> > > > - const: syscon
> > > >
> > >
> > > I think we had that several times already:
> > >
> >
> >
https://lore.kernel.org/all/6bbe9527-ae48-30e0-fb45-519223a744d7@linaro.org/
> > >
> > > We will something like this, but please check that this does not
> > > give
> > > any
> > > errors/warnings:
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y
> > > aml
> > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y
> > > aml
> > > index eb451bec23d3d..8e9c4f4d7c389 100644
> > > ---
> > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y
> > > aml
> > > +++
> > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y
> > > aml
> > > @@ -32,13 +32,22 @@ properties:
> > > - mediatek,mt8183-mmsys
> > > - mediatek,mt8186-mmsys
> > > - mediatek,mt8192-mmsys
> > > - - mediatek,mt8195-mmsys
> > > - mediatek,mt8365-mmsys
> > > - const: syscon
> > > - items:
> > > - const: mediatek,mt7623-mmsys
> > > - const: mediatek,mt2701-mmsys
> > > - const: syscon
> > > + - items:
> > > + - const: mediatek,mt8195-vdosys0
> > > + - const: syscon
> > > + - items:
> > > + - const: mediatek,mt8195-vdosys1
> > > + - const: syscon
> > > + - items:
> > > + - const: mediatek,mt8195-mmsys
> > > + - const: syscon
> > > + deprecated: true
> > >
> > > reg:
> > > maxItems: 1
> >
> > Hi Matthias,
> >
> > As the vdosys0 previous reviewed patch:
> >
> >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220927152704.12018-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zRdbIyyAsfqob2kapMAcKYATAguhEV0x0qE5cTOAcWUNhzeAbMHzZoos_2QzUCxS$
> >
> > Should I modify the vdosys0 items format like your example?
> >
> > Or should vdosys1 add items format like vdosys0's previous patch?
> > - items:
> > - const: mediatek,mt8195-vdosys1
> > - const: mediatek,mt8195-mmsys
> > - const: syscon
> >
>
> No, vdosys1 must not have mediatek,mt8195-mmsys fallback.
>
> Regards,
> Matthias
>
I will fix it and add the following vdosys1 binding base on [1].
- description: vdosys0 and vdosys1 are 2 display HW pipelines,
so mt8195 binding should be deprecated.
deprecated: true
items:
- const: mediatek,mt8195-mmsys
- const: syscon
- items:
- const: mediatek,mt7623-mmsys
- const: mediatek,mt2701-mmsys
- const: syscon
- items:
- const: mediatek,mt8195-vdosys0
- const: mediatek,mt8195-mmsys
- const: syscon
+ - items:
+ - const: mediatek,mt8195-vdosys1
+ - const: syscon
[1]
https://kernel.googlesource.com/pub/scm/linux/kernel/git/matthias.bgg/linux/+/b237efd47df7d25b78c306e90b97c5aa0ff4c4fc/Documentation/devicetree/bindings/arm/mediatek/mediatek%2Cmmsys.yaml
Regards,
Nancy
> > Regards,
> > Jason-JH.Lin
> >
> >
> >
> > ************* MEDIATEK Confidentiality Notice
> > ********************
> > The information contained in this e-mail message (including any
> > attachments) may be confidential, proprietary, privileged, or
> > otherwise
> > exempt from disclosure under applicable laws. It is intended to be
> > conveyed only to the designated recipient(s). Any use,
> > dissemination,
> > distribution, printing, retaining or copying of this e-mail
> > (including its
> > attachments) by unintended recipient(s) is strictly prohibited and
> > may
> > be unlawful. If you are not an intended recipient of this e-mail,
> > or believe
> >
> > that you have received this e-mail in error, please notify the
> > sender
> > immediately (by replying to this e-mail), delete any and all copies
> > of
> > this e-mail (including any attachments) from your system, and do
> > not
> > disclose the content of this e-mail to any other person. Thank you!
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
2022-11-22 10:51 ` Nancy Lin (林欣螢)
@ 2022-11-22 15:48 ` Matthias Brugger
0 siblings, 0 replies; 30+ messages in thread
From: Matthias Brugger @ 2022-11-22 15:48 UTC (permalink / raw)
To: Nancy Lin (林欣螢),
robh+dt, Jason-JH Lin (林睿祥),
chunkuang.hu, linux, p.zabel, wim, angelogioacchino.delregno,
nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, airlied,
Singo Chang (張興國),
llvm, ndesaulniers, linux-kernel, dri-devel, nathan,
linux-mediatek, Yongqiang Niu (牛永强),
linux-arm-kernel
On 22/11/2022 11:51, Nancy Lin (林欣螢) wrote:
> Dear Matthias,
>
> Thanks for the review.
>
> On Thu, 2022-11-10 at 14:10 +0100, Matthias Brugger wrote:
>>
>> On 09/11/2022 06:10, Jason-JH Lin (林睿祥) wrote:
>> > On Tue, 2022-11-08 at 18:46 +0100, Matthias Brugger wrote:
>> > >
>> > > On 07/11/2022 08:22, Nancy.Lin wrote:
>> > > > Add vdosys1 mmsys compatible for MT8195 platform.
>> > > >
>> > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines
>> > > > binding
>> > > > to
>> > > > 2 different power domains, different clock drivers and
>> > > > different
>> > > > mediatek-drm drivers.
>> > > >
>> > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
>> > > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>> > > > ---
>> > > >
>> > > > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml |
>> > > > 4
>> > > > +++-
>> > > > 1 file changed, 3 insertions(+), 1 deletion(-)
>> > > >
>> > > > diff --git
>> > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
>> > > > .yam
>> > > > l
>> > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
>> > > > .yam
>> > > > l
>> > > > index 0711f1834fbd..aaabe2196185 100644
>> > > > ---
>> > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
>> > > > .yam
>> > > > l
>> > > > +++
>> > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
>> > > > .yam
>> > > > l
>> > > > @@ -48,7 +48,9 @@ properties:
>> > > > - const: syscon
>> > > >
>> > > > - items:
>> > > > - - const: mediatek,mt8195-vdosys0
>> > > > + - enum:
>> > > > + - mediatek,mt8195-vdosys0
>> > > > + - mediatek,mt8195-vdosys1
>> > > > - const: mediatek,mt8195-mmsys
>> > > > - const: syscon
>> > > >
>> > >
>> > > I think we had that several times already:
>> > >
>> >
>> >
> https://lore.kernel.org/all/6bbe9527-ae48-30e0-fb45-519223a744d7@linaro.org/
>> > >
>> > > We will something like this, but please check that this does not
>> > > give
>> > > any
>> > > errors/warnings:
>> > >
>> > > diff --git
>> > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y
>> > > aml
>> > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y
>> > > aml
>> > > index eb451bec23d3d..8e9c4f4d7c389 100644
>> > > ---
>> > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y
>> > > aml
>> > > +++
>> > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y
>> > > aml
>> > > @@ -32,13 +32,22 @@ properties:
>> > > - mediatek,mt8183-mmsys
>> > > - mediatek,mt8186-mmsys
>> > > - mediatek,mt8192-mmsys
>> > > - - mediatek,mt8195-mmsys
>> > > - mediatek,mt8365-mmsys
>> > > - const: syscon
>> > > - items:
>> > > - const: mediatek,mt7623-mmsys
>> > > - const: mediatek,mt2701-mmsys
>> > > - const: syscon
>> > > + - items:
>> > > + - const: mediatek,mt8195-vdosys0
>> > > + - const: syscon
>> > > + - items:
>> > > + - const: mediatek,mt8195-vdosys1
>> > > + - const: syscon
>> > > + - items:
>> > > + - const: mediatek,mt8195-mmsys
>> > > + - const: syscon
>> > > + deprecated: true
>> > >
>> > > reg:
>> > > maxItems: 1
>> >
>> > Hi Matthias,
>> >
>> > As the vdosys0 previous reviewed patch:
>> >
>> >
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220927152704.12018-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zRdbIyyAsfqob2kapMAcKYATAguhEV0x0qE5cTOAcWUNhzeAbMHzZoos_2QzUCxS$
>> >
>> > Should I modify the vdosys0 items format like your example?
>> >
>> > Or should vdosys1 add items format like vdosys0's previous patch?
>> > - items:
>> > - const: mediatek,mt8195-vdosys1
>> > - const: mediatek,mt8195-mmsys
>> > - const: syscon
>> >
>>
>> No, vdosys1 must not have mediatek,mt8195-mmsys fallback.
>>
>> Regards,
>> Matthias
>>
>
> I will fix it and add the following vdosys1 binding base on [1].
>
> - description: vdosys0 and vdosys1 are 2 display HW pipelines,
> so mt8195 binding should be deprecated.
> deprecated: true
> items:
> - const: mediatek,mt8195-mmsys
> - const: syscon
> - items:
> - const: mediatek,mt7623-mmsys
> - const: mediatek,mt2701-mmsys
> - const: syscon
> - items:
> - const: mediatek,mt8195-vdosys0
> - const: mediatek,mt8195-mmsys
> - const: syscon
> + - items:
> + - const: mediatek,mt8195-vdosys1
> + - const: syscon
>
Looks good, thanks
Matthias
> [1]
> https://kernel.googlesource.com/pub/scm/linux/kernel/git/matthias.bgg/linux/+/b237efd47df7d25b78c306e90b97c5aa0ff4c4fc/Documentation/devicetree/bindings/arm/mediatek/mediatek%2Cmmsys.yaml
>
> Regards,
> Nancy
>
>
>> > Regards,
>> > Jason-JH.Lin
>> >
>> >
>> >
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
2022-11-07 7:22 ` [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195 Nancy.Lin
2022-11-08 17:46 ` Matthias Brugger
@ 2022-11-23 16:06 ` Krzysztof Kozlowski
2022-11-24 7:34 ` Nancy Lin (林欣螢)
1 sibling, 1 reply; 30+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-23 16:06 UTC (permalink / raw)
To: Nancy.Lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
Philipp Zabel, wim, AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, David Airlie,
jason-jh . lin, singo.chang, llvm, Nick Desaulniers,
linux-kernel, dri-devel, Nathan Chancellor, linux-mediatek,
Yongqiang Niu, linux-arm-kernel
On 07/11/2022 08:22, Nancy.Lin wrote:
> Add vdosys1 mmsys compatible for MT8195 platform.
>
> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
> 2 different power domains, different clock drivers and different
> mediatek-drm drivers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Any reason for not CC-ing maintainers pointed out by get_maintainers.pl?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
2022-11-23 16:06 ` Krzysztof Kozlowski
@ 2022-11-24 7:34 ` Nancy Lin (林欣螢)
0 siblings, 0 replies; 30+ messages in thread
From: Nancy Lin (林欣螢) @ 2022-11-24 7:34 UTC (permalink / raw)
To: robh+dt, krzk, chunkuang.hu, linux, p.zabel, wim, matthias.bgg,
angelogioacchino.delregno, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, airlied,
Jason-JH Lin (林睿祥),
Singo Chang (張興國),
llvm, ndesaulniers, linux-kernel, dri-devel, nathan,
linux-mediatek, Yongqiang Niu (牛永强),
linux-arm-kernel
[-- Attachment #1: Type: text/html, Size: 2301 bytes --]
[-- Attachment #2: Type: text/plain, Size: 835 bytes --]
Dear Krzysztof,
Thanks for the review.
On Wed, 2022-11-23 at 17:06 +0100, Krzysztof Kozlowski wrote:
> On 07/11/2022 08:22, Nancy.Lin wrote:
> > Add vdosys1 mmsys compatible for MT8195 platform.
> >
> > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
> > to
> > 2 different power domains, different clock drivers and different
> > mediatek-drm drivers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>
> Any reason for not CC-ing maintainers pointed out by
> get_maintainers.pl?
>
> Best regards,
> Krzysztof
>
> I used the recorded maintainer list, instead of executing the
> maintainer.pl every time. I will update maintainer in the next
> revision soon. Sorry for the inconvinence.
Regards,
Nancy
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v28 02/11] dt-bindings: reset: mt8195: add vdosys1 reset control bit
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195 Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 03/11] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components Nancy.Lin
` (8 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
include/dt-bindings/reset/mt8195-resets.h | 45 +++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index 24ab3631dcea..e61660438d61 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -35,4 +35,49 @@
#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4
#define MT8195_INFRA_RST2_USBSIF_P1_SWRST 5
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0
+#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 1
+#define MT8195_VDOSYS1_SW0_RST_B_GALS 2
+#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 3
+#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 4
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 5
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 6
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 7
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 8
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 9
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 10
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 11
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 12
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 13
+#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC 14
+#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC 15
+#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX 16
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 17
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 18
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 19
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 20
+#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 21
+#define MT8195_VDOSYS1_SW0_RST_B_DPI0 22
+#define MT8195_VDOSYS1_SW0_RST_B_DPI1 23
+#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR 24
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC 30
+#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC 31
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 32
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 33
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE 34
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 48
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 49
+#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER 50
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v28 03/11] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195 Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 02/11] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
` (7 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
Add new mmsys component: ethdr_mixer and mdp_rdma. These components will
use in mt8195 vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 16ac0e5847f0..127f1b888ace 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -28,7 +28,16 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
DDP_COMPONENT_DSI3,
+ DDP_COMPONENT_ETHDR_MIXER,
DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_MDP_RDMA0,
+ DDP_COMPONENT_MDP_RDMA1,
+ DDP_COMPONENT_MDP_RDMA2,
+ DDP_COMPONENT_MDP_RDMA3,
+ DDP_COMPONENT_MDP_RDMA4,
+ DDP_COMPONENT_MDP_RDMA5,
+ DDP_COMPONENT_MDP_RDMA6,
+ DDP_COMPONENT_MDP_RDMA7,
DDP_COMPONENT_MERGE0,
DDP_COMPONENT_MERGE1,
DDP_COMPONENT_MERGE2,
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
` (2 preceding siblings ...)
2022-11-07 7:22 ` [PATCH v28 03/11] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
2022-11-08 17:46 ` Matthias Brugger
2022-11-07 7:22 ` [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API Nancy.Lin
` (6 subsequent siblings)
10 siblings, 1 reply; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
Add mt8195 vdosys1 routing table to the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 139 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 10 ++
2 files changed, 149 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index abfe94a30248..fd7b455bd675 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -75,6 +75,70 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2
+#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8195_SOUT_TO_MIXER_IN1_SEL 1
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8195_SOUT_TO_MIXER_IN2_SEL 1
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8195_SOUT_TO_MIXER_IN3_SEL 1
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8195_SOUT_TO_MIXER_IN4_SEL 1
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -367,4 +431,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
+ {
+ DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN1_SEL
+ }, {
+ DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN2_SEL
+ }, {
+ DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN3_SEL
+ }, {
+ DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN4_SEL
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+ MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ }, {
+ DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+ MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+ MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DPI1_SEL
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
+ }
+};
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 146a78ba06c1..9a327eb5d9d7 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -80,6 +80,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_vdo1_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
@@ -292,6 +298,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2022-11-07 7:22 ` [PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
@ 2022-11-08 17:46 ` Matthias Brugger
2022-11-08 19:10 ` Nícolas F. R. A. Prado
0 siblings, 1 reply; 30+ messages in thread
From: Matthias Brugger @ 2022-11-08 17:46 UTC (permalink / raw)
To: Nancy.Lin, Rob Herring, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, David Airlie,
jason-jh . lin, singo.chang, llvm, Nick Desaulniers,
linux-kernel, dri-devel, Nathan Chancellor, linux-mediatek,
Yongqiang Niu, linux-arm-kernel
On 07/11/2022 08:22, Nancy.Lin wrote:
> Add mt8195 vdosys1 routing table to the driver data of mtk-mmsys.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 139 ++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 10 ++
> 2 files changed, 149 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index abfe94a30248..fd7b455bd675 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -75,6 +75,70 @@
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
>
> +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> +#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
> +
> +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
> +#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1
> +
> +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
> +#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
> +
> +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
> +#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
> +
> +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> +#define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2
> +#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3
> +
> +#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
> +#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1
> +
> +#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
> +#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1
> +
> +#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
> +#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1
> +
> +#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
> +#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1
> +
> +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> +#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1
> +
> +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
> +#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1
> +
> +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> +#define MT8195_SOUT_TO_MIXER_IN1_SEL 1
> +
> +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> +#define MT8195_SOUT_TO_MIXER_IN2_SEL 1
> +
> +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> +#define MT8195_SOUT_TO_MIXER_IN3_SEL 1
> +
> +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> +#define MT8195_SOUT_TO_MIXER_IN4_SEL 1
> +
> +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
> +#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1
> +
> +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> +#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0
> +
> +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
> +#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0
> +
> +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
> +#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0
> +
> +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
> +#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0
> +
> +#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
> +#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
> +
> static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -367,4 +431,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> }
> };
>
> +static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
> + {
> + DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
> + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
> + MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> + }, {
> + DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
> + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
> + MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> + }, {
> + DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
> + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
> + MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> + }, {
> + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN1_SEL
> + }, {
> + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN2_SEL
> + }, {
> + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN3_SEL
> + }, {
> + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
> + MT8195_SOUT_TO_MIXER_IN4_SEL
> + }, {
> + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
> + MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> + }, {
> + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> + MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
> + MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> + }, {
> + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
> + MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> + }, {
> + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
> + MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
> + MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> + MT8195_MERGE4_SOUT_TO_DPI1_SEL
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
> + MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> + MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
> + }
> +};
> #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 146a78ba06c1..9a327eb5d9d7 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -80,6 +80,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .clk_driver = "clk-mt8195-vdo1",
> + .routes = mmsys_mt8195_vdo1_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> @@ -292,6 +298,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8195-vdosys0",
> .data = &mt8195_vdosys0_driver_data,
It seems we are missing a patch in the series. vdosys0 also correct was never
introduced in the driver...
> },
> + {
> + .compatible = "mediatek,mt8195-vdosys1",
> + .data = &mt8195_vdosys1_driver_data,
> + },
> {
> .compatible = "mediatek,mt8365-mmsys",
> .data = &mt8365_mmsys_driver_data,
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2022-11-08 17:46 ` Matthias Brugger
@ 2022-11-08 19:10 ` Nícolas F. R. A. Prado
2022-11-09 11:18 ` Matthias Brugger
0 siblings, 1 reply; 30+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-11-08 19:10 UTC (permalink / raw)
To: Matthias Brugger
Cc: Chun-Kuang Hu, Project_Global_Chrome_Upstream_Group, devicetree,
David Airlie, jason-jh . lin, dri-devel, llvm, Nick Desaulniers,
linux-kernel, Rob Herring, Yongqiang Niu, Nathan Chancellor,
Nancy.Lin, linux-mediatek, linux-arm-kernel, wim, singo.chang,
linux, AngeloGioacchino Del Regno
On Tue, Nov 08, 2022 at 06:46:54PM +0100, Matthias Brugger wrote:
> On 07/11/2022 08:22, Nancy.Lin wrote:
[..]
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -80,6 +80,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > };
> > +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> > + .clk_driver = "clk-mt8195-vdo1",
> > + .routes = mmsys_mt8195_vdo1_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
> > +};
> > +
> > static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > @@ -292,6 +298,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> > .compatible = "mediatek,mt8195-vdosys0",
> > .data = &mt8195_vdosys0_driver_data,
>
> It seems we are missing a patch in the series. vdosys0 also correct was
> never introduced in the driver...
Hi Matthias,
as mentioned in the cover letter, this series is based on the series "Change
mmsys compatible for mt8195 mediatek-drm" [1], which introduces vdosys0. This
compatible entry specifically is added on patch 3 of that series [2].
[1] https://lore.kernel.org/all/20220927152704.12018-1-jason-jh.lin@mediatek.com/
[2] https://lore.kernel.org/all/20220927152704.12018-4-jason-jh.lin@mediatek.com/
Thanks,
Nícolas
>
> > },
> > + {
> > + .compatible = "mediatek,mt8195-vdosys1",
> > + .data = &mt8195_vdosys1_driver_data,
> > + },
> > {
> > .compatible = "mediatek,mt8365-mmsys",
> > .data = &mt8365_mmsys_driver_data,
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2022-11-08 19:10 ` Nícolas F. R. A. Prado
@ 2022-11-09 11:18 ` Matthias Brugger
0 siblings, 0 replies; 30+ messages in thread
From: Matthias Brugger @ 2022-11-09 11:18 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Chun-Kuang Hu, Project_Global_Chrome_Upstream_Group, devicetree,
David Airlie, jason-jh . lin, dri-devel, llvm, Nick Desaulniers,
linux-kernel, Rob Herring, Yongqiang Niu, Nathan Chancellor,
Nancy.Lin, linux-mediatek, linux-arm-kernel, wim, singo.chang,
linux, AngeloGioacchino Del Regno
On 08/11/2022 20:10, Nícolas F. R. A. Prado wrote:
> On Tue, Nov 08, 2022 at 06:46:54PM +0100, Matthias Brugger wrote:
>> On 07/11/2022 08:22, Nancy.Lin wrote:
> [..]
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -80,6 +80,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
>>> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>>> };
>>> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
>>> + .clk_driver = "clk-mt8195-vdo1",
>>> + .routes = mmsys_mt8195_vdo1_routing_table,
>>> + .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
>>> +};
>>> +
>>> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
>>> .clk_driver = "clk-mt8365-mm",
>>> .routes = mt8365_mmsys_routing_table,
>>> @@ -292,6 +298,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
>>> .compatible = "mediatek,mt8195-vdosys0",
>>> .data = &mt8195_vdosys0_driver_data,
>>
>> It seems we are missing a patch in the series. vdosys0 also correct was
>> never introduced in the driver...
>
> Hi Matthias,
>
> as mentioned in the cover letter, this series is based on the series "Change
> mmsys compatible for mt8195 mediatek-drm" [1], which introduces vdosys0. This
> compatible entry specifically is added on patch 3 of that series [2].
>
> [1] https://lore.kernel.org/all/20220927152704.12018-1-jason-jh.lin@mediatek.com/
My bad. Thanks for the link. I realized that yesterday but had to leave
urgently. I'll have a look on this series now.
Regards,
Matthias
> [2] https://lore.kernel.org/all/20220927152704.12018-4-jason-jh.lin@mediatek.com/
>
> Thanks,
> Nícolas
>
>>
>>> },
>>> + {
>>> + .compatible = "mediatek,mt8195-vdosys1",
>>> + .data = &mt8195_vdosys1_driver_data,
>>> + },
>>> {
>>> .compatible = "mediatek,mt8365-mmsys",
>>> .data = &mt8365_mmsys_driver_data,
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
` (3 preceding siblings ...)
2022-11-07 7:22 ` [PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
2022-11-08 17:37 ` Matthias Brugger
2022-12-01 11:44 ` Chen-Yu Tsai
2022-11-07 7:22 ` [PATCH v28 06/11] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Nancy.Lin
` (5 subsequent siblings)
10 siblings, 2 replies; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
Simplify code for update mmsys reg.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 45 ++++++++++++--------------------
1 file changed, 16 insertions(+), 29 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9a327eb5d9d7..73c8bd27e6ae 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -99,22 +99,27 @@ struct mtk_mmsys {
struct reset_controller_dev rcdev;
};
+static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ tmp = readl_relaxed(mmsys->regs + offset);
+ tmp = (tmp & ~mask) | (val & mask);
+ writel_relaxed(tmp, mmsys->regs + offset);
+}
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_routes *routes = mmsys->data->routes;
- u32 reg;
int i;
for (i = 0; i < mmsys->data->num_routes; i++)
- if (cur == routes[i].from_comp && next == routes[i].to_comp) {
- reg = readl_relaxed(mmsys->regs + routes[i].addr);
- reg &= ~routes[i].mask;
- reg |= routes[i].val;
- writel_relaxed(reg, mmsys->regs + routes[i].addr);
- }
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask,
+ routes[i].val);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -124,27 +129,14 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_routes *routes = mmsys->data->routes;
- u32 reg;
int i;
for (i = 0; i < mmsys->data->num_routes; i++)
- if (cur == routes[i].from_comp && next == routes[i].to_comp) {
- reg = readl_relaxed(mmsys->regs + routes[i].addr);
- reg &= ~routes[i].mask;
- writel_relaxed(reg, mmsys->regs + routes[i].addr);
- }
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
-static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
-{
- u32 tmp;
-
- tmp = readl_relaxed(mmsys->regs + offset);
- tmp = (tmp & ~mask) | val;
- writel_relaxed(tmp, mmsys->regs + offset);
-}
-
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
{
if (val)
@@ -161,18 +153,13 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
{
struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
unsigned long flags;
- u32 reg;
spin_lock_irqsave(&mmsys->lock, flags);
- reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
-
if (assert)
- reg &= ~BIT(id);
+ mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0);
else
- reg |= BIT(id);
-
- writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
+ mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id));
spin_unlock_irqrestore(&mmsys->lock, flags);
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API
2022-11-07 7:22 ` [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API Nancy.Lin
@ 2022-11-08 17:37 ` Matthias Brugger
2022-11-08 19:43 ` Nícolas F. R. A. Prado
2022-12-01 11:44 ` Chen-Yu Tsai
1 sibling, 1 reply; 30+ messages in thread
From: Matthias Brugger @ 2022-11-08 17:37 UTC (permalink / raw)
To: Nancy.Lin, Rob Herring, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, David Airlie,
jason-jh . lin, singo.chang, llvm, Nick Desaulniers,
linux-kernel, dri-devel, Nathan Chancellor, linux-mediatek,
Yongqiang Niu, linux-arm-kernel
On 07/11/2022 08:22, Nancy.Lin wrote:
> Simplify code for update mmsys reg.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
> drivers/soc/mediatek/mtk-mmsys.c | 45 ++++++++++++--------------------
> 1 file changed, 16 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 9a327eb5d9d7..73c8bd27e6ae 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -99,22 +99,27 @@ struct mtk_mmsys {
> struct reset_controller_dev rcdev;
> };
>
> +static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
> +{
> + u32 tmp;
> +
> + tmp = readl_relaxed(mmsys->regs + offset);
> + tmp = (tmp & ~mask) | (val & mask);
I'm not sure about the change in the implementation of mtk_mmsys_update_bits().
Nicolas tried to explain it to me on IRC but I wasn't totally convincing. As we
have to go for at least another round of this patches, I'd like to get a clear
understanding while it is needed that val bits are set to 1 in the mask.
Regards,
Matthias
> + writel_relaxed(tmp, mmsys->regs + offset);
> +}
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> const struct mtk_mmsys_routes *routes = mmsys->data->routes;
> - u32 reg;
> int i;
>
> for (i = 0; i < mmsys->data->num_routes; i++)
> - if (cur == routes[i].from_comp && next == routes[i].to_comp) {
> - reg = readl_relaxed(mmsys->regs + routes[i].addr);
> - reg &= ~routes[i].mask;
> - reg |= routes[i].val;
> - writel_relaxed(reg, mmsys->regs + routes[i].addr);
> - }
> + if (cur == routes[i].from_comp && next == routes[i].to_comp)
> + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask,
> + routes[i].val);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>
> @@ -124,27 +129,14 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> const struct mtk_mmsys_routes *routes = mmsys->data->routes;
> - u32 reg;
> int i;
>
> for (i = 0; i < mmsys->data->num_routes; i++)
> - if (cur == routes[i].from_comp && next == routes[i].to_comp) {
> - reg = readl_relaxed(mmsys->regs + routes[i].addr);
> - reg &= ~routes[i].mask;
> - writel_relaxed(reg, mmsys->regs + routes[i].addr);
> - }
> + if (cur == routes[i].from_comp && next == routes[i].to_comp)
> + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
> -{
> - u32 tmp;
> -
> - tmp = readl_relaxed(mmsys->regs + offset);
> - tmp = (tmp & ~mask) | val;
> - writel_relaxed(tmp, mmsys->regs + offset);
> -}
> -
> void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
> {
> if (val)
> @@ -161,18 +153,13 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
> {
> struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
> unsigned long flags;
> - u32 reg;
>
> spin_lock_irqsave(&mmsys->lock, flags);
>
> - reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
> -
> if (assert)
> - reg &= ~BIT(id);
> + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0);
> else
> - reg |= BIT(id);
> -
> - writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
> + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id));
>
> spin_unlock_irqrestore(&mmsys->lock, flags);
>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API
2022-11-08 17:37 ` Matthias Brugger
@ 2022-11-08 19:43 ` Nícolas F. R. A. Prado
2022-11-10 13:12 ` Matthias Brugger
0 siblings, 1 reply; 30+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-11-08 19:43 UTC (permalink / raw)
To: Matthias Brugger
Cc: Chun-Kuang Hu, Project_Global_Chrome_Upstream_Group, devicetree,
David Airlie, jason-jh . lin, dri-devel, llvm, Nick Desaulniers,
linux-kernel, Rob Herring, Yongqiang Niu, Nathan Chancellor,
Nancy.Lin, linux-mediatek, linux-arm-kernel, wim, singo.chang,
linux, AngeloGioacchino Del Regno
On Tue, Nov 08, 2022 at 06:37:19PM +0100, Matthias Brugger wrote:
>
>
> On 07/11/2022 08:22, Nancy.Lin wrote:
> > Simplify code for update mmsys reg.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > ---
> > drivers/soc/mediatek/mtk-mmsys.c | 45 ++++++++++++--------------------
> > 1 file changed, 16 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> > index 9a327eb5d9d7..73c8bd27e6ae 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -99,22 +99,27 @@ struct mtk_mmsys {
> > struct reset_controller_dev rcdev;
> > };
> > +static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
> > +{
> > + u32 tmp;
> > +
> > + tmp = readl_relaxed(mmsys->regs + offset);
> > + tmp = (tmp & ~mask) | (val & mask);
>
> I'm not sure about the change in the implementation of
> mtk_mmsys_update_bits(). Nicolas tried to explain it to me on IRC but I
> wasn't totally convincing. As we have to go for at least another round of
> this patches, I'd like to get a clear understanding while it is needed that
> val bits are set to 1 in the mask.
The point here was to make sure that mtk_mmsys_update_bits() didn't allow
setting bits outside of the mask, since that's never what you want: the entire
point of having a mask is to specify the bits that should be updated (and the
ones that should be kept unchanged). So for example if you had
mask = 0x0ff0
val = 0x00ff
the previous implementation would happily overwrite the 4 least significant bits
on the destination register, despite them not being present in the mask, which
is wrong.
This wrong behavior could easily lead to hard to trace bugs as soon as a badly
formatted/wrong val is passed and an unrelated bit updated due to the mask being
ignored.
For reference, _regmap_update_bits() does the same masking of the value [1].
That said, given that this function already existed and was just being moved,
it would've been cleaner to make this change in a separate commit.
[1] https://elixir.bootlin.com/linux/latest/source/drivers/base/regmap/regmap.c#L3122
Thanks,
Nícolas
>
> Regards,
> Matthias
>
> > + writel_relaxed(tmp, mmsys->regs + offset);
> > +}
[..]
> > -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
> > -{
> > - u32 tmp;
> > -
> > - tmp = readl_relaxed(mmsys->regs + offset);
> > - tmp = (tmp & ~mask) | val;
> > - writel_relaxed(tmp, mmsys->regs + offset);
> > -}
> > -
[..]
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API
2022-11-08 19:43 ` Nícolas F. R. A. Prado
@ 2022-11-10 13:12 ` Matthias Brugger
2022-11-24 9:38 ` Nancy Lin (林欣螢)
0 siblings, 1 reply; 30+ messages in thread
From: Matthias Brugger @ 2022-11-10 13:12 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Chun-Kuang Hu, Project_Global_Chrome_Upstream_Group, devicetree,
David Airlie, jason-jh . lin, dri-devel, llvm, Nick Desaulniers,
linux-kernel, Rob Herring, Yongqiang Niu, Nathan Chancellor,
Nancy.Lin, linux-mediatek, linux-arm-kernel, wim, singo.chang,
linux, AngeloGioacchino Del Regno
On 08/11/2022 20:43, Nícolas F. R. A. Prado wrote:
> On Tue, Nov 08, 2022 at 06:37:19PM +0100, Matthias Brugger wrote:
>>
>>
>> On 07/11/2022 08:22, Nancy.Lin wrote:
>>> Simplify code for update mmsys reg.
>>>
>>> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>> Reviewed-by: CK Hu <ck.hu@mediatek.com>
>>> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
>>> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>>> ---
>>> drivers/soc/mediatek/mtk-mmsys.c | 45 ++++++++++++--------------------
>>> 1 file changed, 16 insertions(+), 29 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
>>> index 9a327eb5d9d7..73c8bd27e6ae 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -99,22 +99,27 @@ struct mtk_mmsys {
>>> struct reset_controller_dev rcdev;
>>> };
>>> +static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
>>> +{
>>> + u32 tmp;
>>> +
>>> + tmp = readl_relaxed(mmsys->regs + offset);
>>> + tmp = (tmp & ~mask) | (val & mask);
>>
>> I'm not sure about the change in the implementation of
>> mtk_mmsys_update_bits(). Nicolas tried to explain it to me on IRC but I
>> wasn't totally convincing. As we have to go for at least another round of
>> this patches, I'd like to get a clear understanding while it is needed that
>> val bits are set to 1 in the mask.
>
> The point here was to make sure that mtk_mmsys_update_bits() didn't allow
> setting bits outside of the mask, since that's never what you want: the entire
> point of having a mask is to specify the bits that should be updated (and the
> ones that should be kept unchanged). So for example if you had
>
> mask = 0x0ff0
> val = 0x00ff
>
> the previous implementation would happily overwrite the 4 least significant bits
> on the destination register, despite them not being present in the mask, which
> is wrong.
>
> This wrong behavior could easily lead to hard to trace bugs as soon as a badly
> formatted/wrong val is passed and an unrelated bit updated due to the mask being
> ignored.
>
> For reference, _regmap_update_bits() does the same masking of the value [1].
>
> That said, given that this function already existed and was just being moved,
> it would've been cleaner to make this change in a separate commit.
>
Would have been better, but we can leave it as it.
Regards,
Matthias
> [1] https://elixir.bootlin.com/linux/latest/source/drivers/base/regmap/regmap.c#L3122
>
> Thanks,
> Nícolas
>
>>
>> Regards,
>> Matthias
>>
>>> + writel_relaxed(tmp, mmsys->regs + offset);
>>> +}
> [..]
>>> -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
>>> -{
>>> - u32 tmp;
>>> -
>>> - tmp = readl_relaxed(mmsys->regs + offset);
>>> - tmp = (tmp & ~mask) | val;
>>> - writel_relaxed(tmp, mmsys->regs + offset);
>>> -}
>>> -
> [..]
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API
2022-11-10 13:12 ` Matthias Brugger
@ 2022-11-24 9:38 ` Nancy Lin (林欣螢)
0 siblings, 0 replies; 30+ messages in thread
From: Nancy Lin (林欣螢) @ 2022-11-24 9:38 UTC (permalink / raw)
To: matthias.bgg, nfraprado
Cc: chunkuang.hu, Project_Global_Chrome_Upstream_Group, devicetree,
airlied, Jason-JH Lin (林睿祥),
Singo Chang (張興國),
llvm, ndesaulniers, linux-kernel, dri-devel, nathan, robh+dt,
linux-mediatek, linux-arm-kernel,
Yongqiang Niu (牛永强),
wim, linux, angelogioacchino.delregno
[-- Attachment #1: Type: text/html, Size: 8693 bytes --]
[-- Attachment #2: Type: text/plain, Size: 3983 bytes --]
Dear Matthias,
Thanks for the review.
On Thu, 2022-11-10 at 14:12 +0100, Matthias Brugger wrote:
>
> On 08/11/2022 20:43, Nícolas F. R. A. Prado wrote:
> > On Tue, Nov 08, 2022 at 06:37:19PM +0100, Matthias Brugger wrote:
> > >
> > >
> > > On 07/11/2022 08:22, Nancy.Lin wrote:
> > > > Simplify code for update mmsys reg.
> > > >
> > > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > > > Tested-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > > > ---
> > > > drivers/soc/mediatek/mtk-mmsys.c | 45 ++++++++++++--------
> > > > ------------
> > > > 1 file changed, 16 insertions(+), 29 deletions(-)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > > index 9a327eb5d9d7..73c8bd27e6ae 100644
> > > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > > @@ -99,22 +99,27 @@ struct mtk_mmsys {
> > > > struct reset_controller_dev rcdev;
> > > > };
> > > > +static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32
> > > > offset, u32 mask, u32 val)
> > > > +{
> > > > + u32 tmp;
> > > > +
> > > > + tmp = readl_relaxed(mmsys->regs + offset);
> > > > + tmp = (tmp & ~mask) | (val & mask);
> > >
> > > I'm not sure about the change in the implementation of
> > > mtk_mmsys_update_bits(). Nicolas tried to explain it to me on IRC
> > > but I
> > > wasn't totally convincing. As we have to go for at least another
> > > round of
> > > this patches, I'd like to get a clear understanding while it is
> > > needed that
> > > val bits are set to 1 in the mask.
> >
> > The point here was to make sure that mtk_mmsys_update_bits() didn't
> > allow
> > setting bits outside of the mask, since that's never what you want:
> > the entire
> > point of having a mask is to specify the bits that should be
> > updated (and the
> > ones that should be kept unchanged). So for example if you had
> >
> > mask = 0x0ff0
> > val = 0x00ff
> >
> > the previous implementation would happily overwrite the 4 least
> > significant bits
> > on the destination register, despite them not being present in the
> > mask, which
> > is wrong.
> >
> > This wrong behavior could easily lead to hard to trace bugs as soon
> > as a badly
> > formatted/wrong val is passed and an unrelated bit updated due to
> > the mask being
> > ignored.
> >
> > For reference, _regmap_update_bits() does the same masking of the
> > value [1].
> >
> > That said, given that this function already existed and was just
> > being moved,
> > it would've been cleaner to make this change in a separate commit.
> >
>
> Would have been better, but we can leave it as it.
>
> Regards,
> Matthias
>
Do you mean to keep original one (1), or keep this (2) ?
1. tmp = (tmp & ~mask) | val;
2. tmp = (tmp & ~mask) | (val & mask);
Regards,
Nancy
> > [1]
> > https://urldefense.com/v3/__https://elixir.bootlin.com/linux/latest/source/drivers/base/regmap/regmap.c*L3122__;Iw!!CTRNKA9wMg0ARbw!xSv5xbY6cv-Mg-1xDGOf3oVZ93uyrcv4tt87DKlx5emjmwufjf2DjION7GiNAaJB$
> >
> >
> > Thanks,
> > Nícolas
> >
> > >
> > > Regards,
> > > Matthias
> > >
> > > > + writel_relaxed(tmp, mmsys->regs + offset);
> > > > +}
> >
> > [..]
> > > > -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32
> > > > offset, u32 mask, u32 val)
> > > > -{
> > > > - u32 tmp;
> > > > -
> > > > - tmp = readl_relaxed(mmsys->regs + offset);
> > > > - tmp = (tmp & ~mask) | val;
> > > > - writel_relaxed(tmp, mmsys->regs + offset);
> > > > -}
> > > > -
> >
> > [..]
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API
2022-11-07 7:22 ` [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API Nancy.Lin
2022-11-08 17:37 ` Matthias Brugger
@ 2022-12-01 11:44 ` Chen-Yu Tsai
2022-12-27 7:54 ` Nancy Lin (林欣螢)
1 sibling, 1 reply; 30+ messages in thread
From: Chen-Yu Tsai @ 2022-12-01 11:44 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Yongqiang Niu, nfraprado, devicetree,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Rob Herring,
linux-mediatek, linux-arm-kernel, Matthias Brugger,
Nathan Chancellor, wim, linux, AngeloGioacchino Del Regno
On Mon, Nov 7, 2022 at 3:23 PM Nancy.Lin <nancy.lin@mediatek.com> wrote:
>
> Simplify code for update mmsys reg.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
> drivers/soc/mediatek/mtk-mmsys.c | 45 ++++++++++++--------------------
> 1 file changed, 16 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 9a327eb5d9d7..73c8bd27e6ae 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
[...]
> @@ -124,27 +129,14 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> const struct mtk_mmsys_routes *routes = mmsys->data->routes;
> - u32 reg;
> int i;
>
> for (i = 0; i < mmsys->data->num_routes; i++)
> - if (cur == routes[i].from_comp && next == routes[i].to_comp) {
> - reg = readl_relaxed(mmsys->regs + routes[i].addr);
> - reg &= ~routes[i].mask;
> - writel_relaxed(reg, mmsys->regs + routes[i].addr);
> - }
> + if (cur == routes[i].from_comp && next == routes[i].to_comp)
> + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
> -{
> - u32 tmp;
> -
> - tmp = readl_relaxed(mmsys->regs + offset);
> - tmp = (tmp & ~mask) | val;
> - writel_relaxed(tmp, mmsys->regs + offset);
> -}
> -
> void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
> {
> if (val)
This hunk now doesn't apply due to
soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config func
touching mtk_mmsys_ddp_dpi_fmt_config() as well. It's trivial to resolve
though.
ChenYu
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API
2022-12-01 11:44 ` Chen-Yu Tsai
@ 2022-12-27 7:54 ` Nancy Lin (林欣螢)
0 siblings, 0 replies; 30+ messages in thread
From: Nancy Lin (林欣螢) @ 2022-12-27 7:54 UTC (permalink / raw)
To: wenst
Cc: chunkuang.hu, Project_Global_Chrome_Upstream_Group, nfraprado,
devicetree, airlied, Jason-JH Lin (林睿祥),
Singo Chang (張興國),
llvm, ndesaulniers, linux-kernel, dri-devel, nathan, robh+dt,
linux-mediatek, linux-arm-kernel,
Yongqiang Niu (牛永强),
matthias.bgg, wim, linux, angelogioacchino.delregno
[-- Attachment #1: Type: text/html, Size: 6296 bytes --]
[-- Attachment #2: Type: text/plain, Size: 2736 bytes --]
Dear Chen-Yu,
Sorry for late response and thanks for the review.
On Thu, 2022-12-01 at 19:44 +0800, Chen-Yu Tsai wrote:
> On Mon, Nov 7, 2022 at 3:23 PM Nancy.Lin <nancy.lin@mediatek.com>
> wrote:
> >
> > Simplify code for update mmsys reg.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > Tested-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > ---
> > drivers/soc/mediatek/mtk-mmsys.c | 45 ++++++++++++--------------
> > ------
> > 1 file changed, 16 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 9a327eb5d9d7..73c8bd27e6ae 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
>
> [...]
>
> > @@ -124,27 +129,14 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> > {
> > struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > const struct mtk_mmsys_routes *routes = mmsys->data-
> > >routes;
> > - u32 reg;
> > int i;
> >
> > for (i = 0; i < mmsys->data->num_routes; i++)
> > - if (cur == routes[i].from_comp && next ==
> > routes[i].to_comp) {
> > - reg = readl_relaxed(mmsys->regs +
> > routes[i].addr);
> > - reg &= ~routes[i].mask;
> > - writel_relaxed(reg, mmsys->regs +
> > routes[i].addr);
> > - }
> > + if (cur == routes[i].from_comp && next ==
> > routes[i].to_comp)
> > + mtk_mmsys_update_bits(mmsys,
> > routes[i].addr, routes[i].mask, 0);
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32
> > offset, u32 mask, u32 val)
> > -{
> > - u32 tmp;
> > -
> > - tmp = readl_relaxed(mmsys->regs + offset);
> > - tmp = (tmp & ~mask) | val;
> > - writel_relaxed(tmp, mmsys->regs + offset);
> > -}
> > -
> > void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
> > {
> > if (val)
>
> This hunk now doesn't apply due to
>
> soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config
> func
>
> touching mtk_mmsys_ddp_dpi_fmt_config() as well. It's trivial to
> resolve
> though.
>
> ChenYu
I will update next revision base on next-20221226 which include the
patch you mentioned.
Regards,
Nancy
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v28 06/11] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
` (4 preceding siblings ...)
2022-11-07 7:22 ` [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
2022-11-08 17:46 ` Matthias Brugger
2022-11-07 7:22 ` [PATCH v28 07/11] soc: mediatek: add cmdq support of " Nancy.Lin
` (4 subsequent siblings)
10 siblings, 1 reply; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
Add four mmsys config APIs. The config APIs are used for config
mmsys reg. Some mmsys regs need to be set according to the
HW engine binding to the mmsys simultaneously.
1. mtk_mmsys_merge_async_config: config merge async width/height.
async is used for cross-clock domain synchronization.
2. mtk_mmsys_hdr_confing: config hdr backend async width/height.
3. mtk_mmsys_mixer_in_config and mtk_mmsys_mixer_in_config:
config mixer related settings.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 6 +++++
drivers/soc/mediatek/mtk-mmsys.c | 35 ++++++++++++++++++++++++++
include/linux/soc/mediatek/mtk-mmsys.h | 9 +++++++
3 files changed, 50 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index fd7b455bd675..454944a9409c 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -75,6 +75,12 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG 0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
+
#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 73c8bd27e6ae..6040a3cff6f8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -137,6 +137,41 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height)
+{
+ mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
+ ~0, height << 16 | width);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
+
+void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height)
+{
+ mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
+ be_height << 16 | be_width);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);
+
+void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
+ u8 mode, u32 biwidth)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+
+ mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0,
+ alpha << 16 | alpha);
+ mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),
+ alpha_sel << (19 + idx));
+ mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
+ GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
+
+void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap)
+{
+ mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
+ BIT(4), channel_swap << 4);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
+
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
{
if (val)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 127f1b888ace..a4708859c188 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -75,4 +75,13 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
+void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height);
+
+void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height);
+
+void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
+ u8 mode, u32 biwidth);
+
+void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v28 06/11] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
2022-11-07 7:22 ` [PATCH v28 06/11] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Nancy.Lin
@ 2022-11-08 17:46 ` Matthias Brugger
2022-11-28 7:38 ` Nancy Lin (林欣螢)
0 siblings, 1 reply; 30+ messages in thread
From: Matthias Brugger @ 2022-11-08 17:46 UTC (permalink / raw)
To: Nancy.Lin, Rob Herring, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, David Airlie,
jason-jh . lin, singo.chang, llvm, Nick Desaulniers,
linux-kernel, dri-devel, Nathan Chancellor, linux-mediatek,
Yongqiang Niu, linux-arm-kernel
On 07/11/2022 08:22, Nancy.Lin wrote:
> Add four mmsys config APIs. The config APIs are used for config
> mmsys reg. Some mmsys regs need to be set according to the
> HW engine binding to the mmsys simultaneously.
>
> 1. mtk_mmsys_merge_async_config: config merge async width/height.
> async is used for cross-clock domain synchronization.
> 2. mtk_mmsys_hdr_confing: config hdr backend async width/height.
> 3. mtk_mmsys_mixer_in_config and mtk_mmsys_mixer_in_config:
> config mixer related settings.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Not something we need to fix in this series, but it would make sense instead of
adding all the EXPORTS to pass the functions as callbacks in the
platform_device_register_data. But I realize you don't pass the VDOSYS number to
the DRM driver to distinguish between the different MMSYS devices that created
the platform device. I hadn't had a deep look on the DRM implementation but I
suppose it will be challenge...
Regards,
Matthias
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 6 +++++
> drivers/soc/mediatek/mtk-mmsys.c | 35 ++++++++++++++++++++++++++
> include/linux/soc/mediatek/mtk-mmsys.h | 9 +++++++
> 3 files changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index fd7b455bd675..454944a9409c 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -75,6 +75,12 @@
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
>
> +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
> +#define MT8195_VDO1_HDR_TOP_CFG 0xd00
> +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
> +#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
> +
> #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> #define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 73c8bd27e6ae..6040a3cff6f8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -137,6 +137,41 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height)
> +{
> + mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
> + ~0, height << 16 | width);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
> +
> +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height)
> +{
> + mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
> + be_height << 16 | be_width);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);
> +
> +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
> + u8 mode, u32 biwidth)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> +
> + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0,
> + alpha << 16 | alpha);
> + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),
> + alpha_sel << (19 + idx));
> + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
> + GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
> +
> +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap)
> +{
> + mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
> + BIT(4), channel_swap << 4);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
> +
> void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
> {
> if (val)
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 127f1b888ace..a4708859c188 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -75,4 +75,13 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>
> void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
>
> +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height);
> +
> +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height);
> +
> +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
> + u8 mode, u32 biwidth);
> +
> +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap);
> +
> #endif /* __MTK_MMSYS_H */
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v28 06/11] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
2022-11-08 17:46 ` Matthias Brugger
@ 2022-11-28 7:38 ` Nancy Lin (林欣螢)
0 siblings, 0 replies; 30+ messages in thread
From: Nancy Lin (林欣螢) @ 2022-11-28 7:38 UTC (permalink / raw)
To: robh+dt, chunkuang.hu, linux, p.zabel, wim, matthias.bgg,
angelogioacchino.delregno, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, airlied,
Jason-JH Lin (林睿祥),
Singo Chang (張興國),
llvm, ndesaulniers, linux-kernel, dri-devel, nathan,
linux-mediatek, Yongqiang Niu (牛永强),
linux-arm-kernel
[-- Attachment #1: Type: text/html, Size: 10919 bytes --]
[-- Attachment #2: Type: text/plain, Size: 5972 bytes --]
Dear Matthias,
Thanks for the review.
On Tue, 2022-11-08 at 18:46 +0100, Matthias Brugger wrote:
>
> On 07/11/2022 08:22, Nancy.Lin wrote:
> > Add four mmsys config APIs. The config APIs are used for config
> > mmsys reg. Some mmsys regs need to be set according to the
> > HW engine binding to the mmsys simultaneously.
> >
> > 1. mtk_mmsys_merge_async_config: config merge async width/height.
> > async is used for cross-clock domain synchronization.
> > 2. mtk_mmsys_hdr_confing: config hdr backend async width/height.
> > 3. mtk_mmsys_mixer_in_config and mtk_mmsys_mixer_in_config:
> > config mixer related settings.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > Tested-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
>
> Not something we need to fix in this series, but it would make sense
> instead of
> adding all the EXPORTS to pass the functions as callbacks in the
> platform_device_register_data. But I realize you don't pass the
> VDOSYS number to
> the DRM driver to distinguish between the different MMSYS devices
> that created
> the platform device. I hadn't had a deep look on the DRM
> implementation but I
> suppose it will be challenge...
>
> Regards,
> Matthias
>
Do you mean to move all the mmsys config APIs as callback in mmsys
driver data?
If so, not only the four mmsys config APIs in this patch but also the
following original three APIs.
It would take some refactoring effort. I think it would be better to
change this after this series for vdosys1 if needed.
1. mtk_mmsys_ddp_connect
2. mtk_mmsys_ddp_disconnect
3. mtk_mmsys_ddp_dpi_fmt_config
Regards,
Nancy
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 6 +++++
> > drivers/soc/mediatek/mtk-mmsys.c | 35
> > ++++++++++++++++++++++++++
> > include/linux/soc/mediatek/mtk-mmsys.h | 9 +++++++
> > 3 files changed, 50 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index fd7b455bd675..454944a9409c 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -75,6 +75,12 @@
> > #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > (2 << 16)
> > #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > (3 << 16)
> >
> > +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD
> > 0xe30
> > +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD
> > 0xe70
> > +#define MT8195_VDO1_HDR_TOP_CFG
> > 0xd00
> > +#define MT8195_VDO1_MIXER_IN1_ALPHA
> > 0xd30
> > +#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
> > +
> > #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> > #define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > 1
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 73c8bd27e6ae..6040a3cff6f8 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -137,6 +137,41 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int
> > width, int height)
> > +{
> > + mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
> > + ~0, height << 16 | width);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
> > +
> > +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int
> > be_height)
> > +{
> > + mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
> > + be_height << 16 | be_width);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);
> > +
> > +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool
> > alpha_sel, u16 alpha,
> > + u8 mode, u32 biwidth)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > +
> > + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx
> > - 1) * 4, ~0,
> > + alpha << 16 | alpha);
> > + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 +
> > idx),
> > + alpha_sel << (19 + idx));
> > + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx -
> > 1) * 4,
> > + GENMASK(31, 16) | GENMASK(1, 0), biwidth
> > << 16 | mode);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
> > +
> > +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx,
> > bool channel_swap)
> > +{
> > + mtk_mmsys_update_bits(dev_get_drvdata(dev),
> > MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
> > + BIT(4), channel_swap << 4);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
> > +
> > void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
> > {
> > if (val)
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 127f1b888ace..a4708859c188 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -75,4 +75,13 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> >
> > void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
> >
> > +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int
> > width, int height);
> > +
> > +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int
> > be_height);
> > +
> > +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool
> > alpha_sel, u16 alpha,
> > + u8 mode, u32 biwidth);
> > +
> > +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx,
> > bool channel_swap);
> > +
> > #endif /* __MTK_MMSYS_H */
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v28 07/11] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
` (5 preceding siblings ...)
2022-11-07 7:22 ` [PATCH v28 06/11] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 08/11] soc: mediatek: mmsys: add mmsys for support 64 reset bits Nancy.Lin
` (3 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is used for this purpose. We prepare all the related HW settings
in one cmdq packet. The first command in the packet is "wait stream done",
and then following with all the HW settings. After the cmdq packet is
flush to GCE HW. The GCE waits for the "stream done event" to coming
and then starts flushing all the HW settings. This can guarantee all
the settings flush in the same vblanking.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 59 ++++++++++++++++++--------
include/linux/soc/mediatek/mtk-mmsys.h | 15 +++++--
2 files changed, 53 insertions(+), 21 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 6040a3cff6f8..1bd2f8e45d85 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -97,12 +97,27 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ struct cmdq_client_reg cmdq_base;
};
-static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
+static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val,
+ struct cmdq_pkt *cmdq_pkt)
{
u32 tmp;
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_pkt) {
+ if (mmsys->cmdq_base.size == 0) {
+ pr_err("mmsys lose gce property, failed to update mmsys bits with cmdq");
+ return;
+ }
+ cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
+ mmsys->cmdq_base.offset + offset, val,
+ mask);
+ return;
+ }
+#endif
+
tmp = readl_relaxed(mmsys->regs + offset);
tmp = (tmp & ~mask) | (val & mask);
writel_relaxed(tmp, mmsys->regs + offset);
@@ -119,7 +134,7 @@ void mtk_mmsys_ddp_connect(struct device *dev,
for (i = 0; i < mmsys->data->num_routes; i++)
if (cur == routes[i].from_comp && next == routes[i].to_comp)
mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask,
- routes[i].val);
+ routes[i].val, NULL);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -133,42 +148,45 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
for (i = 0; i < mmsys->data->num_routes; i++)
if (cur == routes[i].from_comp && next == routes[i].to_comp)
- mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0);
+ mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
-void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height)
+void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height,
+ struct cmdq_pkt *cmdq_pkt)
{
mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
- ~0, height << 16 | width);
+ ~0, height << 16 | width, cmdq_pkt);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
-void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height)
+void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height,
+ struct cmdq_pkt *cmdq_pkt)
{
mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
- be_height << 16 | be_width);
+ be_height << 16 | be_width, cmdq_pkt);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);
void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
- u8 mode, u32 biwidth)
+ u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0,
- alpha << 16 | alpha);
+ alpha << 16 | alpha, cmdq_pkt);
mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),
- alpha_sel << (19 + idx));
+ alpha_sel << (19 + idx), cmdq_pkt);
mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
- GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode);
+ GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
-void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap)
+void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,
+ struct cmdq_pkt *cmdq_pkt)
{
mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
- BIT(4), channel_swap << 4);
+ BIT(4), channel_swap << 4, cmdq_pkt);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
@@ -176,10 +194,10 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
{
if (val)
mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8186_MMSYS_DPI_OUTPUT_FORMAT,
- DPI_RGB888_DDR_CON, DPI_FORMAT_MASK);
+ DPI_RGB888_DDR_CON, DPI_FORMAT_MASK, NULL);
else
mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8186_MMSYS_DPI_OUTPUT_FORMAT,
- DPI_RGB565_SDR_CON, DPI_FORMAT_MASK);
+ DPI_RGB565_SDR_CON, DPI_FORMAT_MASK, NULL);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
@@ -192,9 +210,9 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
spin_lock_irqsave(&mmsys->lock, flags);
if (assert)
- mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0);
+ mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL);
else
- mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id));
+ mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL);
spin_unlock_irqrestore(&mmsys->lock, flags);
@@ -262,6 +280,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret)
+ dev_dbg(dev, "No mediatek,gce-client-reg!\n");
+#endif
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index a4708859c188..37296146ac5a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
enum mtk_ddp_comp_id;
struct device;
@@ -75,13 +79,16 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
-void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height);
+void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width,
+ int height, struct cmdq_pkt *cmdq_pkt);
-void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height);
+void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height,
+ struct cmdq_pkt *cmdq_pkt);
void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
- u8 mode, u32 biwidth);
+ u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt);
-void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap);
+void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,
+ struct cmdq_pkt *cmdq_pkt);
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v28 08/11] soc: mediatek: mmsys: add mmsys for support 64 reset bits
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
` (6 preceding siblings ...)
2022-11-07 7:22 ` [PATCH v28 07/11] soc: mediatek: add cmdq support of " Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 09/11] soc: mediatek: mmsys: add reset control for MT8195 vdosys1 Nancy.Lin
` (2 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
Add mmsys for support 64 reset bits. It is a preparation for MT8195
vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits.
1. Add the number of reset bits in mmsys private data
2. move the whole "reset register code section" behind the
"get mmsys->data" code section for getting the num_resets in mmsys->data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 40 +++++++++++++++++++++-----------
drivers/soc/mediatek/mtk-mmsys.h | 1 +
2 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1bd2f8e45d85..78601372512f 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -20,6 +20,8 @@
#include "mt8195-mmsys.h"
#include "mt8365-mmsys.h"
+#define MMSYS_SW_RESET_PER_REG 32
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@@ -51,6 +53,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+ .num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -58,6 +61,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+ .num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -65,6 +69,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.routes = mmsys_mt8186_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
+ .num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -72,6 +77,7 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.routes = mmsys_mt8192_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
+ .num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
@@ -206,13 +212,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
{
struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
unsigned long flags;
+ u32 offset;
+ u32 reg;
+
+ offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+ id = id % MMSYS_SW_RESET_PER_REG;
+ reg = mmsys->data->sw0_rst_offset + offset;
spin_lock_irqsave(&mmsys->lock, flags);
if (assert)
- mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL);
+ mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL);
else
- mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL);
+ mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL);
spin_unlock_irqrestore(&mmsys->lock, flags);
@@ -267,20 +279,22 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
- spin_lock_init(&mmsys->lock);
+ mmsys->data = of_device_get_match_data(&pdev->dev);
- mmsys->rcdev.owner = THIS_MODULE;
- mmsys->rcdev.nr_resets = 32;
- mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
- mmsys->rcdev.of_node = pdev->dev.of_node;
- ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
- if (ret) {
- dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
- return ret;
+ if (mmsys->data->num_resets > 0) {
+ spin_lock_init(&mmsys->lock);
+
+ mmsys->rcdev.owner = THIS_MODULE;
+ mmsys->rcdev.nr_resets = mmsys->data->num_resets;
+ mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+ mmsys->rcdev.of_node = pdev->dev.of_node;
+ ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+ return ret;
+ }
}
- mmsys->data = of_device_get_match_data(&pdev->dev);
-
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
if (ret)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 77f37f8c715b..e19994749adb 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -91,6 +91,7 @@ struct mtk_mmsys_driver_data {
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
const u16 sw0_rst_offset;
+ const u32 num_resets;
};
/*
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v28 09/11] soc: mediatek: mmsys: add reset control for MT8195 vdosys1
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
` (7 preceding siblings ...)
2022-11-07 7:22 ` [PATCH v28 08/11] soc: mediatek: mmsys: add mmsys for support 64 reset bits Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 10/11] soc: mediatek: add mtk-mutex component - dp_intf1 Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 11/11] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
10 siblings, 0 replies; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
MT8195 vdosys1 has more than 32 reset bits and a different reset base
than other chips. Add the number of reset bits and reset base in mmsys
private data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 454944a9409c..a6652ae63431 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -75,6 +75,7 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
#define MT8195_VDO1_HDR_TOP_CFG 0xd00
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 78601372512f..5278edd032c6 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -90,6 +90,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_vdo1_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
+ .sw0_rst_offset = MT8195_VDO1_SW0_RST_B,
+ .num_resets = 64,
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v28 10/11] soc: mediatek: add mtk-mutex component - dp_intf1
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
` (8 preceding siblings ...)
2022-11-07 7:22 ` [PATCH v28 09/11] soc: mediatek: mmsys: add reset control for MT8195 vdosys1 Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 11/11] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
10 siblings, 0 replies; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
Add mtk-mutex DDP_COMPONENT_DP_INTF1 component. The MT8195 vdosys1 path
component contains ovl_adaptor, merge5, and dp_intf1. It is a preparation
for adding support for MT8195 vdosys1 path component.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c1a33d52038e..41cba6aa0e83 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -602,6 +602,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DP_INTF0:
sof_id = MUTEX_SOF_DP_INTF0;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
if (mtx->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -642,6 +645,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
case DDP_COMPONENT_DP_INTF0:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v28 11/11] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
` (9 preceding siblings ...)
2022-11-07 7:22 ` [PATCH v28 10/11] soc: mediatek: add mtk-mutex component - dp_intf1 Nancy.Lin
@ 2022-11-07 7:22 ` Nancy.Lin
10 siblings, 0 replies; 30+ messages in thread
From: Nancy.Lin @ 2022-11-07 7:22 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, wim,
AngeloGioacchino Del Regno, linux, nfraprado
Cc: devicetree, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
David Airlie, jason-jh . lin, singo.chang, llvm,
Nick Desaulniers, linux-kernel, dri-devel, Nathan Chancellor,
Nancy . Lin, linux-mediatek, linux-arm-kernel
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements
which include MDP_RDMA0~7, MERGE0~3, and ETHDR.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 33 ++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 41cba6aa0e83..8d0eb70690e5 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -130,6 +130,24 @@
#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
#define MT8195_MUTEX_MOD_DISP_PWM0 27
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18
+#define MT8195_MUTEX_MOD_DISP1_DPI0 25
+#define MT8195_MUTEX_MOD_DISP1_DPI1 26
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27
+
#define MT8365_MUTEX_MOD_DISP_OVL0 7
#define MT8365_MUTEX_MOD_DISP_OVL0_2L 8
#define MT8365_MUTEX_MOD_DISP_RDMA0 9
@@ -372,6 +390,21 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+ [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0,
+ [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1,
+ [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2,
+ [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3,
+ [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4,
+ [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5,
+ [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6,
+ [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7,
+ [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0,
+ [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1,
+ [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2,
+ [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3,
+ [DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread