[PATCH 0/2] drm: rcar-du: Avoid writing reserved register fields

[PATCH 0/2] drm: rcar-du: Avoid writing reserved register fields

[Laurent Pinchart]

Hello,

This patch series addresses writes to reserved register fields or
reserved registers.

Depending on the DU variant, some registers or register fields are
marked as reserved, but the rcar-du driver writes them unconditionally.
There is a high chance that those registers and fields are simply
ignored, as shown by the lack of known issue. However, high chances
don't satisfy functional safety requirements when they don't match the
documentation.

As there is no chance of datasheet updates that will document these
reserved fields as safe to be written with non-zero values, update the
driver to comply with the documentation.

Laurent Pinchart (2):
  drm: rcar-du: Don't write unimplemented ESCR and OTAR registers on
    Gen3
  drm: rcar-du: Disable alpha blending for DU planes used with VSP

 drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 17 +++++++++++++++--
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c  |  2 +-
 2 files changed, 16 insertions(+), 3 deletions(-)

-- 
Regards,

Laurent Pinchart

[PATCH 1/2] drm: rcar-du: Don't write unimplemented ESCR and OTAR registers on Gen3

[Laurent Pinchart]

The ESCR and OTAR registers are not present in all DU channels on Gen3
SoCs. ESCR only exists in channels that can be routed to an LVDS or
DPAD, and OTAR in channels that can be routed to a DPAD. Skip writing
those registers for other channels. This replaces the DU gen check, as
Gen4 doesn't have LVDS or DPAD outputs.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 5e552b326162..d6d29be6b4f4 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -298,12 +298,25 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 		escr = params.escr;
 	}
 
-	if (rcdu->info->gen < 4) {
+	/*
+	 * The ESCR register only exists in DU channels that can output to an
+	 * LVDS or DPAT, and the OTAR register in DU channels that can output
+	 * to a DPAD.
+	 */
+	if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs |
+	     rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs |
+	     rcdu->info->routes[RCAR_DU_OUTPUT_LVDS0].possible_crtcs |
+	     rcdu->info->routes[RCAR_DU_OUTPUT_LVDS1].possible_crtcs) &
+	    BIT(rcrtc->index)) {
 		dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
 
 		rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
+	}
+
+	if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs |
+	     rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs) &
+	    BIT(rcrtc->index))
 		rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
-	}
 
 	/* Signal polarities */
 	dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
-- 
Regards,

Laurent Pinchart

[PATCH 2/2] drm: rcar-du: Disable alpha blending for DU planes used with VSP

[Laurent Pinchart]

When the input to a DU channel comes from a VSP, the DU doesn't perform
any blending operation. Select XRGB8888 instead of ARGB8888 to ensure
that the corresponding registers don't get written with invalid values.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index fe90be51d64e..45c05d0ffc70 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -73,7 +73,7 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
 			.src.y2 = mode->vdisplay << 16,
 			.zpos = 0,
 		},
-		.format = rcar_du_format_info(DRM_FORMAT_ARGB8888),
+		.format = rcar_du_format_info(DRM_FORMAT_XRGB8888),
 		.source = RCAR_DU_PLANE_VSPD1,
 		.colorkey = 0,
 	};
-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/2] drm: rcar-du: Disable alpha blending for DU planes used with VSP

[Tomi Valkeinen]

On 22/02/2023 07:06, Laurent Pinchart wrote:
> When the input to a DU channel comes from a VSP, the DU doesn't perform
> any blending operation. Select XRGB8888 instead of ARGB8888 to ensure
> that the corresponding registers don't get written with invalid values.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>   drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> index fe90be51d64e..45c05d0ffc70 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> @@ -73,7 +73,7 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
>   			.src.y2 = mode->vdisplay << 16,
>   			.zpos = 0,
>   		},
> -		.format = rcar_du_format_info(DRM_FORMAT_ARGB8888),
> +		.format = rcar_du_format_info(DRM_FORMAT_XRGB8888),
>   		.source = RCAR_DU_PLANE_VSPD1,
>   		.colorkey = 0,
>   	};

Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

  Tomi

Re: [PATCH 1/2] drm: rcar-du: Don't write unimplemented ESCR and OTAR registers on Gen3

[Tomi Valkeinen]

On 22/02/2023 07:06, Laurent Pinchart wrote:
> The ESCR and OTAR registers are not present in all DU channels on Gen3
> SoCs. ESCR only exists in channels that can be routed to an LVDS or
> DPAD, and OTAR in channels that can be routed to a DPAD. Skip writing
> those registers for other channels. This replaces the DU gen check, as
> Gen4 doesn't have LVDS or DPAD outputs.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>   drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 17 +++++++++++++++--
>   1 file changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> index 5e552b326162..d6d29be6b4f4 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -298,12 +298,25 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
>   		escr = params.escr;
>   	}
>   
> -	if (rcdu->info->gen < 4) {
> +	/*
> +	 * The ESCR register only exists in DU channels that can output to an
> +	 * LVDS or DPAT, and the OTAR register in DU channels that can output
> +	 * to a DPAD.
> +	 */
> +	if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs |
> +	     rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs |
> +	     rcdu->info->routes[RCAR_DU_OUTPUT_LVDS0].possible_crtcs |
> +	     rcdu->info->routes[RCAR_DU_OUTPUT_LVDS1].possible_crtcs) &
> +	    BIT(rcrtc->index)) {
>   		dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
>   
>   		rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
> +	}
> +
> +	if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs |
> +	     rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs) &
> +	    BIT(rcrtc->index))
>   		rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
> -	}
>   
>   	/* Signal polarities */
>   	dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)

Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

  Tomi