From: Marek Vasut <marex@denx.de>
To: dri-devel@lists.freedesktop.org
Cc: Marek Vasut <marex@denx.de>,
Neil Armstrong <neil.armstrong@linaro.org>,
Robert Foss <rfoss@kernel.org>,
Andrzej Hajda <andrzej.hajda@intel.com>,
Jonas Karlman <jonas@kwiboo.se>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Subject: [PATCH 4/5] drm/bridge: tc358762: Guess the meaning of LCDCTRL bits
Date: Thu, 15 Jun 2023 22:19:01 +0200 [thread overview]
Message-ID: <20230615201902.566182-4-marex@denx.de> (raw)
In-Reply-To: <20230615201902.566182-1-marex@denx.de>
The register content and behavior is very similar to TC358764 VP_CTRL.
All the bits except for unknown bit 6 also seem to match, even though
the datasheet is just not available. Add a comment and reuse the bit
definitions.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: David Airlie <airlied@gmail.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/bridge/tc358762.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c
index 77f2ec9de9e59..a092e2096074f 100644
--- a/drivers/gpu/drm/bridge/tc358762.c
+++ b/drivers/gpu/drm/bridge/tc358762.c
@@ -41,8 +41,17 @@
#define DSI_LANEENABLE 0x0210 /* Enables each lane */
#define DSI_RX_START 1
-/* LCDC/DPI Host Registers */
-#define LCDCTRL 0x0420
+/* LCDC/DPI Host Registers, based on guesswork that this matches TC358764 */
+#define LCDCTRL 0x0420 /* Video Path Control */
+#define LCDCTRL_MSF BIT(0) /* Magic square in RGB666 */
+#define LCDCTRL_VTGEN BIT(4)/* Use chip clock for timing */
+#define LCDCTRL_UNK6 BIT(6) /* Unknown */
+#define LCDCTRL_EVTMODE BIT(5) /* Event mode */
+#define LCDCTRL_RGB888 BIT(8) /* RGB888 mode */
+#define LCDCTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */
+#define LCDCTRL_DEPOL BIT(18) /* Polarity of DE signal */
+#define LCDCTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */
+#define LCDCTRL_VSDELAY(v) (((v) & 0xfff) << 20) /* VSYNC delay */
/* SPI Master Registers */
#define SPICMR 0x0450
@@ -114,7 +123,8 @@ static int tc358762_init(struct tc358762 *ctx)
tc358762_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
tc358762_write(ctx, SPICMR, 0x00);
- tc358762_write(ctx, LCDCTRL, 0x00100150);
+ tc358762_write(ctx, LCDCTRL, LCDCTRL_VSDELAY(1) | LCDCTRL_RGB888 |
+ LCDCTRL_UNK6 | LCDCTRL_VTGEN);
tc358762_write(ctx, SYSCTRL, 0x040f);
msleep(100);
--
2.39.2
next prev parent reply other threads:[~2023-06-15 20:19 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 20:18 [PATCH 1/5] drm/bridge: tc358762: Split register programming from pre-enable to enable Marek Vasut
2023-06-15 20:18 ` [PATCH 2/5] drm/bridge: tc358762: Switch to atomic ops Marek Vasut
2023-06-16 19:02 ` Sam Ravnborg
2023-06-15 20:19 ` [PATCH 3/5] drm/bridge: tc358762: Instruct DSI host to generate HSE packets Marek Vasut
2023-06-16 19:03 ` Sam Ravnborg
2023-11-16 16:06 ` Marc Kleine-Budde
2023-11-16 18:17 ` Marek Vasut
2023-06-15 20:19 ` Marek Vasut [this message]
2023-06-16 19:04 ` [PATCH 4/5] drm/bridge: tc358762: Guess the meaning of LCDCTRL bits Sam Ravnborg
2023-06-15 20:19 ` [PATCH 5/5] drm/bridge: tc358762: Handle HS/VS polarity Marek Vasut
2023-06-16 19:04 ` Sam Ravnborg
2023-06-16 19:02 ` [PATCH 1/5] drm/bridge: tc358762: Split register programming from pre-enable to enable Sam Ravnborg
2023-08-18 9:11 ` Dmitry Baryshkov
2023-06-22 10:10 ` rfoss
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