From: Sam Ravnborg <sam@ravnborg.org>
To: Marek Vasut <marex@denx.de>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
Robert Foss <rfoss@kernel.org>, Jonas Karlman <jonas@kwiboo.se>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
dri-devel@lists.freedesktop.org,
Andrzej Hajda <andrzej.hajda@intel.com>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Subject: Re: [PATCH 4/5] drm/bridge: tc358762: Guess the meaning of LCDCTRL bits
Date: Fri, 16 Jun 2023 21:04:09 +0200 [thread overview]
Message-ID: <20230616190409.GI1697490@ravnborg.org> (raw)
In-Reply-To: <20230615201902.566182-4-marex@denx.de>
On Thu, Jun 15, 2023 at 10:19:01PM +0200, Marek Vasut wrote:
> The register content and behavior is very similar to TC358764 VP_CTRL.
> All the bits except for unknown bit 6 also seem to match, even though
> the datasheet is just not available. Add a comment and reuse the bit
> definitions.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
next prev parent reply other threads:[~2023-06-16 19:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 20:18 [PATCH 1/5] drm/bridge: tc358762: Split register programming from pre-enable to enable Marek Vasut
2023-06-15 20:18 ` [PATCH 2/5] drm/bridge: tc358762: Switch to atomic ops Marek Vasut
2023-06-16 19:02 ` Sam Ravnborg
2023-06-15 20:19 ` [PATCH 3/5] drm/bridge: tc358762: Instruct DSI host to generate HSE packets Marek Vasut
2023-06-16 19:03 ` Sam Ravnborg
2023-11-16 16:06 ` Marc Kleine-Budde
2023-11-16 18:17 ` Marek Vasut
2023-06-15 20:19 ` [PATCH 4/5] drm/bridge: tc358762: Guess the meaning of LCDCTRL bits Marek Vasut
2023-06-16 19:04 ` Sam Ravnborg [this message]
2023-06-15 20:19 ` [PATCH 5/5] drm/bridge: tc358762: Handle HS/VS polarity Marek Vasut
2023-06-16 19:04 ` Sam Ravnborg
2023-06-16 19:02 ` [PATCH 1/5] drm/bridge: tc358762: Split register programming from pre-enable to enable Sam Ravnborg
2023-08-18 9:11 ` Dmitry Baryshkov
2023-06-22 10:10 ` rfoss
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