From: Marc Kleine-Budde <mkl@pengutronix.de>
To: Marek Vasut <marex@denx.de>
Cc: kernel@pengutronix.de, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 3/5] drm/bridge: tc358762: Instruct DSI host to generate HSE packets
Date: Thu, 16 Nov 2023 17:06:34 +0100 [thread overview]
Message-ID: <20231116-tarantula-posing-b941e929b40d-mkl@pengutronix.de> (raw)
In-Reply-To: <20230615201902.566182-3-marex@denx.de>
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Hey Marek,
On 15.06.2023 22:19:00, Marek Vasut wrote:
> This bridge seems to need the HSE packet, otherwise the image is
> shifted up and corrupted at the bottom. This makes the bridge
> work with Samsung DSIM on i.MX8MM and i.MX8MP.
I'm using v6.6 (which includes this series) on an i.MX8MP with the 7inch
Rspi Panel ("powertip,ph800480t013-idf02"), but I cannot get a stable
image.
With an unmodified imx8mp clock tree the lower 1/4 of the image sheers
to the left.
With 24.75 MHz on the media_disp1_pix and media_mipi_phy1_ref and 792
MHz on video_pll1_out, the image is not static, but wobbly and it's
wrapped around half of the image.
video_pll1_ref_sel 1 1 0 24000000 0 0 50000 Y
video_pll1 1 1 0 792000000 0 0 50000 Y
video_pll1_bypass 1 1 0 792000000 0 0 50000 Y
video_pll1_out 2 2 0 792000000 0 0 50000 Y
media_mipi_phy1_ref 1 1 0 24750000 0 0 50000 Y
media_mipi_phy1_ref_root 0 0 0 24750000 0 0 50000 Y
media_disp2_pix 0 0 0 792000000 0 0 50000 N
media_disp2_pix_root_clk 0 0 0 792000000 0 0 50000 N
media_disp1_pix 1 1 0 24750000 0 0 50000 Y
media_disp1_pix_root_clk 1 1 0 24750000 0 0 50000 Y
Do you have a working device tree for such a setup? regards, Marc
Relevant DT snipped for my setup:
&{/} {
panel {
compatible = "powertip,ph800480t013-idf02";
power-supply = <&attiny>;
backlight = <&attiny>;
port {
panel_in: endpoint {
remote-endpoint = <&bridge_out>;
};
};
};
};
&mipi_dsi {
samsung,esc-clock-frequency = <54000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_VIDEO_PLL1_OUT>;
assigned-clock-rates = <200000000>, <24750000>;
status = "okay";
bridge@0 {
compatible = "toshiba,tc358762";
reg = <0>;
vddc-supply = <&attiny>;
reset-gpio = <&attiny 0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
port@1 {
reg = <1>;
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi_out: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&bridge_in>;
};
};
};
};
&media_blk_ctrl {
assigned-clock-rates = <500000000>, <200000000>,
<0>, <0>, <792000000>;
};
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung Nürnberg | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
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next prev parent reply other threads:[~2023-11-16 16:06 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 20:18 [PATCH 1/5] drm/bridge: tc358762: Split register programming from pre-enable to enable Marek Vasut
2023-06-15 20:18 ` [PATCH 2/5] drm/bridge: tc358762: Switch to atomic ops Marek Vasut
2023-06-16 19:02 ` Sam Ravnborg
2023-06-15 20:19 ` [PATCH 3/5] drm/bridge: tc358762: Instruct DSI host to generate HSE packets Marek Vasut
2023-06-16 19:03 ` Sam Ravnborg
2023-11-16 16:06 ` Marc Kleine-Budde [this message]
2023-11-16 18:17 ` Marek Vasut
2023-06-15 20:19 ` [PATCH 4/5] drm/bridge: tc358762: Guess the meaning of LCDCTRL bits Marek Vasut
2023-06-16 19:04 ` Sam Ravnborg
2023-06-15 20:19 ` [PATCH 5/5] drm/bridge: tc358762: Handle HS/VS polarity Marek Vasut
2023-06-16 19:04 ` Sam Ravnborg
2023-06-16 19:02 ` [PATCH 1/5] drm/bridge: tc358762: Split register programming from pre-enable to enable Sam Ravnborg
2023-08-18 9:11 ` Dmitry Baryshkov
2023-06-22 10:10 ` rfoss
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