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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com,
	contact@emersion.fr, harry.wentland@amd.com, mwen@igalia.com,
	jadahl@redhat.com, sebastian.wick@redhat.com,
	shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es,
	mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com,
	victoria@system76.com, daniel@ffwll.ch, quic_naseer@quicinc.com,
	quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com,
	arthurgrillo@riseup.net, marcan@marcan.st, Liviu.Dudau@arm.com,
	sashamcintosh@google.com, sean@poorly.run,
	Uma Shankar <uma.shankar@intel.com>
Subject: [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities to colorop
Date: Tue, 13 Feb 2024 12:18:24 +0530	[thread overview]
Message-ID: <20240213064835.139464-18-uma.shankar@intel.com> (raw)
In-Reply-To: <20240213064835.139464-1-uma.shankar@intel.com>

This defines the lut segments and create the color pipeline

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 109 +++++++++++++++++++++
 1 file changed, 109 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index e223edbe4c13..223cd1ff7291 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3811,6 +3811,105 @@ static const struct intel_color_funcs ilk_color_funcs = {
 	.get_config = ilk_get_config,
 };
 
+static const struct drm_color_lut_range xelpd_degamma_hdr[] = {
+	/* segment 1 */
+	{
+		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
+				DRM_MODE_LUT_INTERPOLATE |
+				DRM_MODE_LUT_NON_DECREASING),
+		.count = 128,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 0, .end = (1 << 24) - 1,
+		.min = 0, .max = (1 << 24) - 1,
+	},
+	/* segment 2 */
+	{
+		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
+				DRM_MODE_LUT_INTERPOLATE |
+				DRM_MODE_LUT_REUSE_LAST |
+				DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = (1 << 24) - 1, .end = 1 << 24,
+		.min = 0, .max = (1 << 27) - 1,
+	},
+	/* Segment 3 */
+	{
+		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
+				DRM_MODE_LUT_INTERPOLATE |
+				DRM_MODE_LUT_REUSE_LAST |
+				DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 1 << 24, .end = 3 << 24,
+		.min = 0, .max = (1 << 27) - 1,
+	},
+	/* Segment 4 */
+	{
+		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
+				DRM_MODE_LUT_INTERPOLATE |
+				DRM_MODE_LUT_REUSE_LAST |
+				DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 3 << 24, .end = 7 << 24,
+		.min = 0, .max = (1 << 27) - 1,
+	}
+};
+
+/* FIXME input bpc? */
+static const struct drm_color_lut_range xelpd_gamma_hdr[] = {
+	/*
+	 * ToDo: Add Segment 1
+	 * There is an optional fine segment added with 9 lut values
+	 * Will be added later
+	 */
+
+	/* segment 2 */
+	{
+		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
+				DRM_MODE_LUT_INTERPOLATE |
+				DRM_MODE_LUT_NON_DECREASING),
+		.count = 32,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 0, .end = (1 << 24) - 1,
+		.min = 0, .max = (1 << 24) - 1,
+	},
+	/* segment 3 */
+	{
+		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
+				DRM_MODE_LUT_INTERPOLATE |
+				DRM_MODE_LUT_REUSE_LAST |
+				DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = (1 << 24) - 1, .end = 1 << 24,
+		.min = 0, .max = 1 << 24,
+	},
+	/* Segment 4 */
+	{
+		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
+				DRM_MODE_LUT_INTERPOLATE |
+				DRM_MODE_LUT_REUSE_LAST |
+				DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 1 << 24, .end = 3 << 24,
+		.min = 0, .max = (3 << 24),
+	},
+	/* Segment 5 */
+	{
+		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
+				DRM_MODE_LUT_INTERPOLATE |
+				DRM_MODE_LUT_REUSE_LAST |
+				DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 3 << 24, .end = 7 << 24,
+		.min = 0, .max = (7 << 24),
+	},
+};
+
 /* TODO: Move to another file */
 struct intel_plane_colorop *intel_colorop_alloc(void)
 {
@@ -3865,6 +3964,11 @@ int intel_plane_tf_pipeline_init(struct drm_plane *plane, struct drm_prop_enum_l
 	if (ret)
 		return ret;
 
+	if (icl_is_hdr_plane(i915, to_intel_plane(plane)->id)) {
+		drm_colorop_lutcaps_init(&colorop->base, plane, xelpd_degamma_hdr,
+					 sizeof(xelpd_degamma_hdr));
+	}
+
 	list->type = colorop->base.base.id;
 	list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop->base.base.id);
 
@@ -3886,6 +3990,11 @@ int intel_plane_tf_pipeline_init(struct drm_plane *plane, struct drm_prop_enum_l
 	if (ret)
 		return ret;
 
+	if (icl_is_hdr_plane(i915, to_intel_plane(plane)->id)) {
+		drm_colorop_lutcaps_init(&colorop->base, plane, xelpd_gamma_hdr,
+					 sizeof(xelpd_gamma_hdr));
+	}
+
 	drm_colorop_set_next_property(prev_op, &colorop->base);
 
 	return 0;
-- 
2.42.0


  parent reply	other threads:[~2024-02-13  6:42 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-13  6:48 [PATCH 00/28] Plane Color Pipeline support for Intel platforms Uma Shankar
2024-02-13  6:48 ` [PATCH 01/28] [NOT FOR REVIEW] drm: color pipeline base work Uma Shankar
2024-02-13 21:15   ` kernel test robot
2024-02-14  2:46   ` kernel test robot
2024-02-16 12:07   ` kernel test robot
2024-02-17 16:56   ` kernel test robot
2024-02-13  6:48 ` [PATCH 02/28] drm: Add missing function declarations Uma Shankar
2024-02-13  6:48 ` [PATCH 03/28] drm: handle NULL next colorop in drm_colorop_set_next_property Uma Shankar
2024-02-13  6:48 ` [PATCH 04/28] drm: Fix error logging in set Color Pipeline Uma Shankar
2024-02-13  6:48 ` [PATCH 05/28] drm: Add support for 3x3 CTM Uma Shankar
2024-02-13  9:15   ` Pekka Paalanen
2024-02-14  6:55     ` Shankar, Uma
2024-02-13  6:48 ` [PATCH 06/28] drm: Add Enhanced LUT precision structure Uma Shankar
2024-02-13  6:48 ` [PATCH 07/28] drm: Add 1D LUT color op Uma Shankar
2024-02-13  6:48 ` [PATCH 08/28] drm: Add Color lut range attributes Uma Shankar
2024-02-13 12:04   ` Sebastian Wick
2024-02-14  7:34     ` Shankar, Uma
2024-02-13  6:48 ` [PATCH 09/28] drm: Add Color ops capability property Uma Shankar
2024-02-13 12:04   ` Sebastian Wick
2024-02-14  7:36     ` Shankar, Uma
2024-02-13  6:48 ` [PATCH 10/28] drm: Define helper to create color " Uma Shankar
2024-02-13  6:48 ` [PATCH 11/28] drm: Define helper for adding capability property for 1D LUT Uma Shankar
2024-02-13  6:48 ` [PATCH 12/28] drm/i915: Add identifiers for intel color blocks Uma Shankar
2024-02-13  6:48 ` [PATCH 13/28] drm/i915: Add intel_color_op Uma Shankar
2024-02-13  6:48 ` [PATCH 14/28] drm/i915/color: Add helper to allocate intel colorop Uma Shankar
2024-02-13  6:48 ` [PATCH 15/28] drm/i915/color: Add helper to create " Uma Shankar
2024-02-13  6:48 ` [PATCH 16/28] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2024-02-19  7:34   ` Dan Carpenter
2024-02-13  6:48 ` Uma Shankar [this message]
2024-02-13  9:37   ` [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities to colorop Pekka Paalanen
2024-02-14  7:28     ` Shankar, Uma
2024-02-14  9:03       ` Pekka Paalanen
2024-02-19 10:34         ` Shankar, Uma
2024-02-19 12:02           ` Pekka Paalanen
2024-02-13  6:48 ` [PATCH 18/28] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2024-02-13  6:48 ` [PATCH 19/28] drm/i915/color: Add framework to set colorop Uma Shankar
2024-02-13  6:48 ` [PATCH 20/28] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2024-02-13  6:48 ` [PATCH 21/28] drm/i915/color: Add plane CTM callback for TGL and beyond Uma Shankar
2024-02-13  6:48 ` [PATCH 22/28] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2024-02-13  6:48 ` [PATCH 23/28] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2024-02-13  6:48 ` [PATCH 24/28] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2024-02-13  6:48 ` [PATCH 25/28] drm/i915/color: Program Pre-CSC registers Uma Shankar
2024-02-13  6:48 ` [PATCH 26/28] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2024-02-13  6:48 ` [PATCH 27/28] FIXME: force disable legacy plane color properties for TGL and beyond Uma Shankar
2024-02-13  6:48 ` [PATCH 28/28] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2024-02-13 11:01 ` [PATCH 00/28] Plane Color Pipeline support for Intel platforms Pekka Paalanen
2024-02-14  7:33   ` Shankar, Uma
2024-02-16 21:47 ` Harry Wentland
2024-02-19 10:49   ` Shankar, Uma

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