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From: Pekka Paalanen <pekka.paalanen@haloniitty.fi>
To: "Shankar, Uma" <uma.shankar@intel.com>
Cc: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"contact@emersion.fr" <contact@emersion.fr>,
	"harry.wentland@amd.com" <harry.wentland@amd.com>,
	"mwen@igalia.com" <mwen@igalia.com>,
	"jadahl@redhat.com" <jadahl@redhat.com>,
	"sebastian.wick@redhat.com" <sebastian.wick@redhat.com>,
	"shashank.sharma@amd.com" <shashank.sharma@amd.com>,
	"agoins@nvidia.com" <agoins@nvidia.com>,
	"joshua@froggi.es" <joshua@froggi.es>,
	"mdaenzer@redhat.com" <mdaenzer@redhat.com>,
	"aleixpol@kde.org" <aleixpol@kde.org>,
	"xaver.hugl@gmail.com" <xaver.hugl@gmail.com>,
	"victoria@system76.com" <victoria@system76.com>,
	"daniel@ffwll.ch" <daniel@ffwll.ch>,
	"quic_naseer@quicinc.com" <quic_naseer@quicinc.com>,
	"quic_cbraga@quicinc.com" <quic_cbraga@quicinc.com>,
	"quic_abhinavk@quicinc.com" <quic_abhinavk@quicinc.com>,
	"arthurgrillo@riseup.net" <arthurgrillo@riseup.net>,
	"marcan@marcan.st" <marcan@marcan.st>,
	"Liviu.Dudau@arm.com" <Liviu.Dudau@arm.com>,
	"sashamcintosh@google.com" <sashamcintosh@google.com>,
	"sean@poorly.run" <sean@poorly.run>
Subject: Re: [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities to colorop
Date: Wed, 14 Feb 2024 11:03:40 +0200	[thread overview]
Message-ID: <20240214110340.477e9df3@eldfell> (raw)
In-Reply-To: <DM4PR11MB636037556D1EF1ACC2A70629F44E2@DM4PR11MB6360.namprd11.prod.outlook.com>

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On Wed, 14 Feb 2024 07:28:37 +0000
"Shankar, Uma" <uma.shankar@intel.com> wrote:

> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Pekka
> > Paalanen
> > Sent: Tuesday, February 13, 2024 3:07 PM
> > To: Shankar, Uma <uma.shankar@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
> > ville.syrjala@linux.intel.com; contact@emersion.fr; harry.wentland@amd.com;
> > mwen@igalia.com; jadahl@redhat.com; sebastian.wick@redhat.com;
> > shashank.sharma@amd.com; agoins@nvidia.com; joshua@froggi.es;
> > mdaenzer@redhat.com; aleixpol@kde.org; xaver.hugl@gmail.com;
> > victoria@system76.com; daniel@ffwll.ch; quic_naseer@quicinc.com;
> > quic_cbraga@quicinc.com; quic_abhinavk@quicinc.com; arthurgrillo@riseup.net;
> > marcan@marcan.st; Liviu.Dudau@arm.com; sashamcintosh@google.com;
> > sean@poorly.run
> > Subject: Re: [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities
> > to colorop
> > 
> > On Tue, 13 Feb 2024 12:18:24 +0530
> > Uma Shankar <uma.shankar@intel.com> wrote:
> >   
> > > This defines the lut segments and create the color pipeline
> > >
> > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_color.c | 109
> > > +++++++++++++++++++++
> > >  1 file changed, 109 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > > b/drivers/gpu/drm/i915/display/intel_color.c
> > > index e223edbe4c13..223cd1ff7291 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > > @@ -3811,6 +3811,105 @@ static const struct intel_color_funcs  
> > ilk_color_funcs = {  
> > >  	.get_config = ilk_get_config,
> > >  };
> > >
> > > +static const struct drm_color_lut_range xelpd_degamma_hdr[] = {
> > > +	/* segment 1 */
> > > +	{
> > > +		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
> > > +				DRM_MODE_LUT_INTERPOLATE |
> > > +				DRM_MODE_LUT_NON_DECREASING),  
> > 
> > Hi Uma,
> > 
> > is it a good idea to have these flags per-segment?
> > 
> > I would find it very strange, unusable really, if REFLECT_NEGATIVE applied on
> > some but not all segments, for example. Is such flexibility really necessary in the
> > hardware description?  
> 
> Hi Pekka,
> Idea to have these flags is to just have some option in case there are some differences
> across segments. Most cases this should not be the case, just helps to future proof
> the implementation.
> 
> Based on how the community feels on the usability of it, we can take a call on the flags
> and the expected interpretation for the same. We are open for suggestions on the same.
> 
> >   
> > > +		.count = 128,
> > > +		.input_bpc = 24, .output_bpc = 16,  
> > 
> > The same question about input_bpc and output_bpc.  
> 
> Same for these as well, userspace can just ignore these if no usage. However, for some clients
> it may help in Lut computations.
> The original idea for the structure came from Ville (missed to mention that in cover letter, will get that
> updated in next version).
> 
> @ville.syrjala@linux.intel.com Please share your inputs on the usability of these attributes.

Userspace will always need to evaluate whether each segment is good
enough individually, so maybe it's not that big deal.

Ignoring these is not an option for userspace, because that would mean
userspace does not know what it is getting. If UAPI contains a
parameter, then the onus is on userspace to ensure the value is
acceptable.

> > > +		.start = 0, .end = (1 << 24) - 1,
> > > +		.min = 0, .max = (1 << 24) - 1,
> > > +	},
> > > +	/* segment 2 */
> > > +	{
> > > +		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
> > > +				DRM_MODE_LUT_INTERPOLATE |
> > > +				DRM_MODE_LUT_REUSE_LAST |
> > > +				DRM_MODE_LUT_NON_DECREASING),
> > > +		.count = 1,
> > > +		.input_bpc = 24, .output_bpc = 16,
> > > +		.start = (1 << 24) - 1, .end = 1 << 24,  
> > 
> > What if there is a gap or overlap between the previous segment .end and the next
> > segment .start? Is it forbidden? Will the kernel common code verify that drivers
> > don't make mistakes? Or IGT?  
> 
> This is just to help give some reference to userspace.  As of now, driver trusts the values
> coming from userspace if it sends wrong values its on him and driver can't help much.
> However, we surely can have some sanity check like non decreasing luts etc. to driver.

But what will guarantee that the driver provided values are consistent?
That they actually describe a template of a well-formed sampled
curve? If they are not consistent, userspace cannot use the colorop.
Whose responsibility is it to ensure the consistency?

We have a few examples of drivers getting descriptive values like
these simply wrong until DRM common code started sanity-checking them,
the bitmasks of possible_clones and possible_crtcs for example.

There should also be DRM common code to verify that userspace provided
data matches the segmented LUT description rather than drivers just
trusting it. If it doesn't match, the atomic commit must fail rather
than silently malfunction. The same with programming hardware: if
hardware does not produce the intended result from a given segmented
LUT configuration, the atomic commit must fail instead of malfunction.

> 
> Ideally LUT values should not overlap, but we can indicate this explicitly with flag to
> hint the userspace (for overlap or otherwise) and also get a check in driver for the same.

Sorry? How could overlapping segments ever work? Or segments with a gap
between them?

If segments overlap, what's the rule for choosing which segment to use
for an input value hitting both? The segments can disagree on the
result.

If there are gaps, what is the rule how to handle an input value
hitting a gap?


Thanks,
pq

> 
> Regards,
> Uma Shankar
> 
> > 
> > Thanks,
> > pq
> >   
> > > +		.min = 0, .max = (1 << 27) - 1,
> > > +	},
> > > +	/* Segment 3 */
> > > +	{
> > > +		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
> > > +				DRM_MODE_LUT_INTERPOLATE |
> > > +				DRM_MODE_LUT_REUSE_LAST |
> > > +				DRM_MODE_LUT_NON_DECREASING),
> > > +		.count = 1,
> > > +		.input_bpc = 24, .output_bpc = 16,
> > > +		.start = 1 << 24, .end = 3 << 24,
> > > +		.min = 0, .max = (1 << 27) - 1,
> > > +	},
> > > +	/* Segment 4 */
> > > +	{
> > > +		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
> > > +				DRM_MODE_LUT_INTERPOLATE |
> > > +				DRM_MODE_LUT_REUSE_LAST |
> > > +				DRM_MODE_LUT_NON_DECREASING),
> > > +		.count = 1,
> > > +		.input_bpc = 24, .output_bpc = 16,
> > > +		.start = 3 << 24, .end = 7 << 24,
> > > +		.min = 0, .max = (1 << 27) - 1,
> > > +	}
> > > +};
> > > +
> > > +/* FIXME input bpc? */
> > > +static const struct drm_color_lut_range xelpd_gamma_hdr[] = {
> > > +	/*
> > > +	 * ToDo: Add Segment 1
> > > +	 * There is an optional fine segment added with 9 lut values
> > > +	 * Will be added later
> > > +	 */
> > > +
> > > +	/* segment 2 */
> > > +	{
> > > +		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
> > > +				DRM_MODE_LUT_INTERPOLATE |
> > > +				DRM_MODE_LUT_NON_DECREASING),
> > > +		.count = 32,
> > > +		.input_bpc = 24, .output_bpc = 16,
> > > +		.start = 0, .end = (1 << 24) - 1,
> > > +		.min = 0, .max = (1 << 24) - 1,
> > > +	},
> > > +	/* segment 3 */
> > > +	{
> > > +		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
> > > +				DRM_MODE_LUT_INTERPOLATE |
> > > +				DRM_MODE_LUT_REUSE_LAST |
> > > +				DRM_MODE_LUT_NON_DECREASING),
> > > +		.count = 1,
> > > +		.input_bpc = 24, .output_bpc = 16,
> > > +		.start = (1 << 24) - 1, .end = 1 << 24,
> > > +		.min = 0, .max = 1 << 24,
> > > +	},
> > > +	/* Segment 4 */
> > > +	{
> > > +		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
> > > +				DRM_MODE_LUT_INTERPOLATE |
> > > +				DRM_MODE_LUT_REUSE_LAST |
> > > +				DRM_MODE_LUT_NON_DECREASING),
> > > +		.count = 1,
> > > +		.input_bpc = 24, .output_bpc = 16,
> > > +		.start = 1 << 24, .end = 3 << 24,
> > > +		.min = 0, .max = (3 << 24),
> > > +	},
> > > +	/* Segment 5 */
> > > +	{
> > > +		.flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
> > > +				DRM_MODE_LUT_INTERPOLATE |
> > > +				DRM_MODE_LUT_REUSE_LAST |
> > > +				DRM_MODE_LUT_NON_DECREASING),
> > > +		.count = 1,
> > > +		.input_bpc = 24, .output_bpc = 16,
> > > +		.start = 3 << 24, .end = 7 << 24,
> > > +		.min = 0, .max = (7 << 24),
> > > +	},
> > > +};
> > > +
> > >  /* TODO: Move to another file */
> > >  struct intel_plane_colorop *intel_colorop_alloc(void)  { @@ -3865,6
> > > +3964,11 @@ int intel_plane_tf_pipeline_init(struct drm_plane *plane, struct  
> > drm_prop_enum_l  
> > >  	if (ret)
> > >  		return ret;
> > >
> > > +	if (icl_is_hdr_plane(i915, to_intel_plane(plane)->id)) {
> > > +		drm_colorop_lutcaps_init(&colorop->base, plane,  
> > xelpd_degamma_hdr,  
> > > +					 sizeof(xelpd_degamma_hdr));
> > > +	}
> > > +
> > >  	list->type = colorop->base.base.id;
> > >  	list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d",
> > > colorop->base.base.id);
> > >
> > > @@ -3886,6 +3990,11 @@ int intel_plane_tf_pipeline_init(struct drm_plane  
> > *plane, struct drm_prop_enum_l  
> > >  	if (ret)
> > >  		return ret;
> > >
> > > +	if (icl_is_hdr_plane(i915, to_intel_plane(plane)->id)) {
> > > +		drm_colorop_lutcaps_init(&colorop->base, plane,  
> > xelpd_gamma_hdr,  
> > > +					 sizeof(xelpd_gamma_hdr));
> > > +	}
> > > +
> > >  	drm_colorop_set_next_property(prev_op, &colorop->base);
> > >
> > >  	return 0;  
> 


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  reply	other threads:[~2024-02-14  9:04 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-13  6:48 [PATCH 00/28] Plane Color Pipeline support for Intel platforms Uma Shankar
2024-02-13  6:48 ` [PATCH 01/28] [NOT FOR REVIEW] drm: color pipeline base work Uma Shankar
2024-02-13 21:15   ` kernel test robot
2024-02-14  2:46   ` kernel test robot
2024-02-16 12:07   ` kernel test robot
2024-02-17 16:56   ` kernel test robot
2024-02-13  6:48 ` [PATCH 02/28] drm: Add missing function declarations Uma Shankar
2024-02-13  6:48 ` [PATCH 03/28] drm: handle NULL next colorop in drm_colorop_set_next_property Uma Shankar
2024-02-13  6:48 ` [PATCH 04/28] drm: Fix error logging in set Color Pipeline Uma Shankar
2024-02-13  6:48 ` [PATCH 05/28] drm: Add support for 3x3 CTM Uma Shankar
2024-02-13  9:15   ` Pekka Paalanen
2024-02-14  6:55     ` Shankar, Uma
2024-02-13  6:48 ` [PATCH 06/28] drm: Add Enhanced LUT precision structure Uma Shankar
2024-02-13  6:48 ` [PATCH 07/28] drm: Add 1D LUT color op Uma Shankar
2024-02-13  6:48 ` [PATCH 08/28] drm: Add Color lut range attributes Uma Shankar
2024-02-13 12:04   ` Sebastian Wick
2024-02-14  7:34     ` Shankar, Uma
2024-02-13  6:48 ` [PATCH 09/28] drm: Add Color ops capability property Uma Shankar
2024-02-13 12:04   ` Sebastian Wick
2024-02-14  7:36     ` Shankar, Uma
2024-02-13  6:48 ` [PATCH 10/28] drm: Define helper to create color " Uma Shankar
2024-02-13  6:48 ` [PATCH 11/28] drm: Define helper for adding capability property for 1D LUT Uma Shankar
2024-02-13  6:48 ` [PATCH 12/28] drm/i915: Add identifiers for intel color blocks Uma Shankar
2024-02-13  6:48 ` [PATCH 13/28] drm/i915: Add intel_color_op Uma Shankar
2024-02-13  6:48 ` [PATCH 14/28] drm/i915/color: Add helper to allocate intel colorop Uma Shankar
2024-02-13  6:48 ` [PATCH 15/28] drm/i915/color: Add helper to create " Uma Shankar
2024-02-13  6:48 ` [PATCH 16/28] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2024-02-19  7:34   ` Dan Carpenter
2024-02-13  6:48 ` [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities to colorop Uma Shankar
2024-02-13  9:37   ` Pekka Paalanen
2024-02-14  7:28     ` Shankar, Uma
2024-02-14  9:03       ` Pekka Paalanen [this message]
2024-02-19 10:34         ` Shankar, Uma
2024-02-19 12:02           ` Pekka Paalanen
2024-02-13  6:48 ` [PATCH 18/28] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2024-02-13  6:48 ` [PATCH 19/28] drm/i915/color: Add framework to set colorop Uma Shankar
2024-02-13  6:48 ` [PATCH 20/28] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2024-02-13  6:48 ` [PATCH 21/28] drm/i915/color: Add plane CTM callback for TGL and beyond Uma Shankar
2024-02-13  6:48 ` [PATCH 22/28] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2024-02-13  6:48 ` [PATCH 23/28] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2024-02-13  6:48 ` [PATCH 24/28] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2024-02-13  6:48 ` [PATCH 25/28] drm/i915/color: Program Pre-CSC registers Uma Shankar
2024-02-13  6:48 ` [PATCH 26/28] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2024-02-13  6:48 ` [PATCH 27/28] FIXME: force disable legacy plane color properties for TGL and beyond Uma Shankar
2024-02-13  6:48 ` [PATCH 28/28] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2024-02-13 11:01 ` [PATCH 00/28] Plane Color Pipeline support for Intel platforms Pekka Paalanen
2024-02-14  7:33   ` Shankar, Uma
2024-02-16 21:47 ` Harry Wentland
2024-02-19 10:49   ` Shankar, Uma

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