From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com,
contact@emersion.fr, harry.wentland@amd.com, mwen@igalia.com,
jadahl@redhat.com, sebastian.wick@redhat.com,
shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es,
mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com,
victoria@system76.com, daniel@ffwll.ch, quic_naseer@quicinc.com,
quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com,
arthurgrillo@riseup.net, marcan@marcan.st, Liviu.Dudau@arm.com,
sashamcintosh@google.com, sean@poorly.run,
Uma Shankar <uma.shankar@intel.com>
Subject: [PATCH 25/28] drm/i915/color: Program Pre-CSC registers
Date: Tue, 13 Feb 2024 12:18:32 +0530 [thread overview]
Message-ID: <20240213064835.139464-26-uma.shankar@intel.com> (raw)
In-Reply-To: <20240213064835.139464-1-uma.shankar@intel.com>
Add callback for programming Pre-CSC LUT for TGL and beyond
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 88 ++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 0d68f8303502..6dd9b8e43352 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3779,9 +3779,97 @@ void intel_color_load_plane_csc_matrix(const struct drm_plane_state *plane_state
i915->display.funcs.color->load_plane_csc_matrix(plane_state, blob);
}
+static void xelpd_program_plane_pre_csc_lut(const struct drm_plane_state *state,
+ const struct drm_color_lut_ext *pre_csc_lut,
+ u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size;
+
+ if (icl_is_hdr_plane(dev_priv, plane)) {
+ lut_size = 128;
+
+ intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
+ offset | PLANE_PAL_PREC_AUTO_INCREMENT);
+
+ if (pre_csc_lut) {
+ for (i = 0; i < lut_size; i++) {
+ u64 word = drm_color_lut_extract_ext(pre_csc_lut[i].green, 24);
+ u32 lut_val = (word & 0xffffff);
+
+ intel_de_write_fw(dev_priv,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ lut_val);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ while (i < 131)
+ intel_de_write_fw(dev_priv,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ pre_csc_lut[i++].green);
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ intel_de_write_fw(dev_priv,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write_fw(dev_priv,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ 1 << 24);
+ } while (i++ < 130);
+ }
+
+ intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
+ } else {
+ lut_size = 32;
+
+ /*
+ * First 3 planes are HDR, so reduce by 3 to get to the right
+ * SDR plane offset
+ */
+ plane = plane - 3;
+
+ intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, 0),
+ offset | PLANE_PAL_PREC_AUTO_INCREMENT);
+
+ if (pre_csc_lut) {
+ for (i = 0; i < lut_size; i++)
+ intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ pre_csc_lut[i].green);
+ /* Program the max register to clamp values > 1.0. */
+ while (i < 35)
+ intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ pre_csc_lut[i++].green);
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 16) - 1)) / (lut_size - 1);
+
+ intel_de_write_fw(dev_priv,
+ PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ 1 << 16);
+ } while (i++ < 34);
+ }
+
+ intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, 0), 0);
+ }
+}
+
static void xelpd_plane_load_luts(const struct drm_plane_state *plane_state,
const struct drm_property_blob *blob, bool is_pre_csc)
{
+ struct drm_color_lut_ext *lut = blob->data;
+
+ if (is_pre_csc)
+ xelpd_program_plane_pre_csc_lut(plane_state, lut, 0);
}
void intel_color_load_plane_luts(const struct drm_plane_state *plane_state,
--
2.42.0
next prev parent reply other threads:[~2024-02-13 6:43 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-13 6:48 [PATCH 00/28] Plane Color Pipeline support for Intel platforms Uma Shankar
2024-02-13 6:48 ` [PATCH 01/28] [NOT FOR REVIEW] drm: color pipeline base work Uma Shankar
2024-02-13 21:15 ` kernel test robot
2024-02-14 2:46 ` kernel test robot
2024-02-16 12:07 ` kernel test robot
2024-02-17 16:56 ` kernel test robot
2024-02-13 6:48 ` [PATCH 02/28] drm: Add missing function declarations Uma Shankar
2024-02-13 6:48 ` [PATCH 03/28] drm: handle NULL next colorop in drm_colorop_set_next_property Uma Shankar
2024-02-13 6:48 ` [PATCH 04/28] drm: Fix error logging in set Color Pipeline Uma Shankar
2024-02-13 6:48 ` [PATCH 05/28] drm: Add support for 3x3 CTM Uma Shankar
2024-02-13 9:15 ` Pekka Paalanen
2024-02-14 6:55 ` Shankar, Uma
2024-02-13 6:48 ` [PATCH 06/28] drm: Add Enhanced LUT precision structure Uma Shankar
2024-02-13 6:48 ` [PATCH 07/28] drm: Add 1D LUT color op Uma Shankar
2024-02-13 6:48 ` [PATCH 08/28] drm: Add Color lut range attributes Uma Shankar
2024-02-13 12:04 ` Sebastian Wick
2024-02-14 7:34 ` Shankar, Uma
2024-02-13 6:48 ` [PATCH 09/28] drm: Add Color ops capability property Uma Shankar
2024-02-13 12:04 ` Sebastian Wick
2024-02-14 7:36 ` Shankar, Uma
2024-02-13 6:48 ` [PATCH 10/28] drm: Define helper to create color " Uma Shankar
2024-02-13 6:48 ` [PATCH 11/28] drm: Define helper for adding capability property for 1D LUT Uma Shankar
2024-02-13 6:48 ` [PATCH 12/28] drm/i915: Add identifiers for intel color blocks Uma Shankar
2024-02-13 6:48 ` [PATCH 13/28] drm/i915: Add intel_color_op Uma Shankar
2024-02-13 6:48 ` [PATCH 14/28] drm/i915/color: Add helper to allocate intel colorop Uma Shankar
2024-02-13 6:48 ` [PATCH 15/28] drm/i915/color: Add helper to create " Uma Shankar
2024-02-13 6:48 ` [PATCH 16/28] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2024-02-19 7:34 ` Dan Carpenter
2024-02-13 6:48 ` [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities to colorop Uma Shankar
2024-02-13 9:37 ` Pekka Paalanen
2024-02-14 7:28 ` Shankar, Uma
2024-02-14 9:03 ` Pekka Paalanen
2024-02-19 10:34 ` Shankar, Uma
2024-02-19 12:02 ` Pekka Paalanen
2024-02-13 6:48 ` [PATCH 18/28] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2024-02-13 6:48 ` [PATCH 19/28] drm/i915/color: Add framework to set colorop Uma Shankar
2024-02-13 6:48 ` [PATCH 20/28] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2024-02-13 6:48 ` [PATCH 21/28] drm/i915/color: Add plane CTM callback for TGL and beyond Uma Shankar
2024-02-13 6:48 ` [PATCH 22/28] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2024-02-13 6:48 ` [PATCH 23/28] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2024-02-13 6:48 ` [PATCH 24/28] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2024-02-13 6:48 ` Uma Shankar [this message]
2024-02-13 6:48 ` [PATCH 26/28] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2024-02-13 6:48 ` [PATCH 27/28] FIXME: force disable legacy plane color properties for TGL and beyond Uma Shankar
2024-02-13 6:48 ` [PATCH 28/28] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2024-02-13 11:01 ` [PATCH 00/28] Plane Color Pipeline support for Intel platforms Pekka Paalanen
2024-02-14 7:33 ` Shankar, Uma
2024-02-16 21:47 ` Harry Wentland
2024-02-19 10:49 ` Shankar, Uma
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