* [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3
@ 2020-07-20 23:41 Khaled Almahallawy
2020-07-20 23:41 ` [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support Khaled Almahallawy
2020-07-21 0:07 ` [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Manasi Navare
0 siblings, 2 replies; 7+ messages in thread
From: Khaled Almahallawy @ 2020-07-20 23:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: manasi.d.navare, animesh.manna, Khaled Almahallawy
Add the missing CP2520 pattern 2 and 3 phy compliance patterns
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 2 +-
include/drm/drm_dp_helper.h | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index a3c82e726057..d0fb78c6aca6 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
return err;
break;
- case DP_PHY_TEST_PATTERN_CP2520:
+ case DP_PHY_TEST_PATTERN_CP2520_PAT1:
err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
&data->hbr2_reset,
sizeof(data->hbr2_reset));
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index e47dc22ebf50..65dd6cd71f1e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -708,7 +708,9 @@
# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
# define DP_PHY_TEST_PATTERN_PRBS7 0x3
# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
-# define DP_PHY_TEST_PATTERN_CP2520 0x5
+# define DP_PHY_TEST_PATTERN_CP2520_PAT1 0x5
+# define DP_PHY_TEST_PATTERN_CP2520_PAT2 0x6
+# define DP_PHY_TEST_PATTERN_CP2520_PAT3 0x7
#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
--
2.17.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support
2020-07-20 23:41 [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Khaled Almahallawy
@ 2020-07-20 23:41 ` Khaled Almahallawy
2020-07-21 0:11 ` Manasi Navare
2020-07-21 0:07 ` [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Manasi Navare
1 sibling, 1 reply; 7+ messages in thread
From: Khaled Almahallawy @ 2020-07-20 23:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: manasi.d.navare, animesh.manna, Khaled Almahallawy
Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d6295eb20b63..effadc096740 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5371,7 +5371,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
&intel_dp->compliance.test_data.phytest;
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
enum pipe pipe = crtc->pipe;
- u32 pattern_val;
+ u32 pattern_val, dp_tp_ctl;
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
@@ -5411,7 +5411,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
- case DP_PHY_TEST_PATTERN_CP2520:
+ case DP_PHY_TEST_PATTERN_CP2520_PAT1:
/*
* FIXME: Ideally pattern should come from DPCD 0x24A. As
* current firmware of DPR-100 could not set it, so hardcoding
@@ -5423,6 +5423,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
pattern_val);
break;
+ case DP_PHY_TEST_PATTERN_CP2520_PAT3:
+ DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ dp_tp_ctl = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
+ dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
+ dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TS4a;
+ dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+ dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
+ intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl);
+ break;
default:
WARN(1, "Invalid Phy Test Pattern\n");
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0d31f3bf634..a4607bd1ac26 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9982,6 +9982,10 @@ enum skl_power_gate {
#define DP_TP_CTL_MODE_SST (0 << 27)
#define DP_TP_CTL_MODE_MST (1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TS4a (0 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
--
2.17.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3
2020-07-20 23:41 [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Khaled Almahallawy
2020-07-20 23:41 ` [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support Khaled Almahallawy
@ 2020-07-21 0:07 ` Manasi Navare
2020-07-21 0:40 ` Almahallawy, Khaled
1 sibling, 1 reply; 7+ messages in thread
From: Manasi Navare @ 2020-07-21 0:07 UTC (permalink / raw)
To: Khaled Almahallawy; +Cc: intel-gfx, animesh.manna, dri-devel
On Mon, Jul 20, 2020 at 04:41:25PM -0700, Khaled Almahallawy wrote:
> Add the missing CP2520 pattern 2 and 3 phy compliance patterns
>
> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 2 +-
> include/drm/drm_dp_helper.h | 4 +++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index a3c82e726057..d0fb78c6aca6 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> return err;
>
> break;
> - case DP_PHY_TEST_PATTERN_CP2520:
> + case DP_PHY_TEST_PATTERN_CP2520_PAT1:
> err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
> &data->hbr2_reset,
> sizeof(data->hbr2_reset));
Where do we read PAT2 and PAT3, I see you defined those newly and patch 2/2 has them
in teh switch case but the drm_dp_get_phy_test_pattern function doesnt read them?
Manasi
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index e47dc22ebf50..65dd6cd71f1e 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -708,7 +708,9 @@
> # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
> # define DP_PHY_TEST_PATTERN_PRBS7 0x3
> # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
> -# define DP_PHY_TEST_PATTERN_CP2520 0x5
> +# define DP_PHY_TEST_PATTERN_CP2520_PAT1 0x5
> +# define DP_PHY_TEST_PATTERN_CP2520_PAT2 0x6
> +# define DP_PHY_TEST_PATTERN_CP2520_PAT3 0x7
>
> #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> --
> 2.17.1
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support
2020-07-20 23:41 ` [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support Khaled Almahallawy
@ 2020-07-21 0:11 ` Manasi Navare
2020-07-21 0:20 ` Almahallawy, Khaled
0 siblings, 1 reply; 7+ messages in thread
From: Manasi Navare @ 2020-07-21 0:11 UTC (permalink / raw)
To: Khaled Almahallawy; +Cc: intel-gfx, animesh.manna, dri-devel
On Mon, Jul 20, 2020 at 04:41:26PM -0700, Khaled Almahallawy wrote:
> Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.
>
> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 2 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d6295eb20b63..effadc096740 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5371,7 +5371,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> &intel_dp->compliance.test_data.phytest;
> struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
> enum pipe pipe = crtc->pipe;
> - u32 pattern_val;
> + u32 pattern_val, dp_tp_ctl;
>
> switch (data->phy_pattern) {
> case DP_PHY_TEST_PATTERN_NONE:
> @@ -5411,7 +5411,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> DDI_DP_COMP_CTL_ENABLE |
> DDI_DP_COMP_CTL_CUSTOM80);
> break;
> - case DP_PHY_TEST_PATTERN_CP2520:
> + case DP_PHY_TEST_PATTERN_CP2520_PAT1:
> /*
> * FIXME: Ideally pattern should come from DPCD 0x24A. As
> * current firmware of DPR-100 could not set it, so hardcoding
> @@ -5423,6 +5423,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
> pattern_val);
> break;
> + case DP_PHY_TEST_PATTERN_CP2520_PAT3:
> + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
> + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
> + dp_tp_ctl = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
> + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
> + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TS4a;
> + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
> + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl);
> + break;
> default:
> WARN(1, "Invalid Phy Test Pattern\n");
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0d31f3bf634..a4607bd1ac26 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9982,6 +9982,10 @@ enum skl_power_gate {
> #define DP_TP_CTL_MODE_SST (0 << 27)
> #define DP_TP_CTL_MODE_MST (1 << 27)
> #define DP_TP_CTL_FORCE_ACT (1 << 25)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TS4a (0 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
The bspec calls them Training Pattern 4a/b/c, why is it _TS4a. TP4b, TP4c?
We shd make it uniform, all TP4a/b/c perhaps?
Manasi
> #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
> #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
> #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
> --
> 2.17.1
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support
2020-07-21 0:11 ` Manasi Navare
@ 2020-07-21 0:20 ` Almahallawy, Khaled
0 siblings, 0 replies; 7+ messages in thread
From: Almahallawy, Khaled @ 2020-07-21 0:20 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx, Manna, Animesh, dri-devel
On Mon, 2020-07-20 at 17:11 -0700, Manasi Navare wrote:
> On Mon, Jul 20, 2020 at 04:41:26PM -0700, Khaled Almahallawy wrote:
> > Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source
> > tests.
> >
> > Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++--
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > 2 files changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index d6295eb20b63..effadc096740 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5371,7 +5371,7 @@ static void
> > intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> > &intel_dp->compliance.test_data.phytest;
> > struct intel_crtc *crtc = to_intel_crtc(dig_port-
> > >base.base.crtc);
> > enum pipe pipe = crtc->pipe;
> > - u32 pattern_val;
> > + u32 pattern_val, dp_tp_ctl;
> >
> > switch (data->phy_pattern) {
> > case DP_PHY_TEST_PATTERN_NONE:
> > @@ -5411,7 +5411,7 @@ static void
> > intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> > DDI_DP_COMP_CTL_ENABLE |
> > DDI_DP_COMP_CTL_CUSTOM80);
> > break;
> > - case DP_PHY_TEST_PATTERN_CP2520:
> > + case DP_PHY_TEST_PATTERN_CP2520_PAT1:
> > /*
> > * FIXME: Ideally pattern should come from DPCD 0x24A.
> > As
> > * current firmware of DPR-100 could not set it, so
> > hardcoding
> > @@ -5423,6 +5423,16 @@ static void
> > intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> > DDI_DP_COMP_CTL_ENABLE |
> > DDI_DP_COMP_CTL_HBR2 |
> > pattern_val);
> > break;
> > + case DP_PHY_TEST_PATTERN_CP2520_PAT3:
> > + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
> > + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> > 0x0);
> > + dp_tp_ctl = intel_de_read(dev_priv,
> > TGL_DP_TP_CTL(pipe));
> > + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
> > + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TS4a;
> > + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> > + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
> > + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe),
> > dp_tp_ctl);
> > + break;
> > default:
> > WARN(1, "Invalid Phy Test Pattern\n");
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index a0d31f3bf634..a4607bd1ac26 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9982,6 +9982,10 @@ enum skl_power_gate {
> > #define DP_TP_CTL_MODE_SST (0 << 27)
> > #define DP_TP_CTL_MODE_MST (1 << 27)
> > #define DP_TP_CTL_FORCE_ACT (1 << 25)
> > +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
> > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TS4a (0 << 19)
> > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
> > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
>
> The bspec calls them Training Pattern 4a/b/c, why is it _TS4a. TP4b,
> TP4c?
> We shd make it uniform, all TP4a/b/c perhaps?
Apology,will fix to TP4a/b/c then
>
> Manasi
>
> > #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
> > #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
> > #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
> > --
> > 2.17.1
> >
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3
2020-07-21 0:07 ` [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Manasi Navare
@ 2020-07-21 0:40 ` Almahallawy, Khaled
2020-07-21 18:56 ` Manasi Navare
0 siblings, 1 reply; 7+ messages in thread
From: Almahallawy, Khaled @ 2020-07-21 0:40 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx, Manna, Animesh, dri-devel
On Mon, 2020-07-20 at 17:07 -0700, Manasi Navare wrote:
> On Mon, Jul 20, 2020 at 04:41:25PM -0700, Khaled Almahallawy wrote:
> > Add the missing CP2520 pattern 2 and 3 phy compliance patterns
> >
> > Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
> > ---
> > drivers/gpu/drm/drm_dp_helper.c | 2 +-
> > include/drm/drm_dp_helper.h | 4 +++-
> > 2 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > b/drivers/gpu/drm/drm_dp_helper.c
> > index a3c82e726057..d0fb78c6aca6 100644
> > --- a/drivers/gpu/drm/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct
> > drm_dp_aux *aux,
> > return err;
> >
> > break;
> > - case DP_PHY_TEST_PATTERN_CP2520:
> > + case DP_PHY_TEST_PATTERN_CP2520_PAT1:
> > err = drm_dp_dpcd_read(aux,
> > DP_TEST_HBR2_SCRAMBLER_RESET,
> > &data->hbr2_reset,
> > sizeof(data->hbr2_reset));
>
> Where do we read PAT2 and PAT3, I see you defined those newly and
> patch 2/2 has them
> in teh switch case but the drm_dp_get_phy_test_pattern function
> doesnt read them?
>
Per my understanding from the specs, only HBR2 (CP2520 PAT1) requires
reading dpcd address 0024Ah to set HBR2_COMPLIANCT_SCRAMBLER_RESET.
TPS4 (CP2520 PAT3) doesn’t require that.
I’m not sure about CP2520 PAT2 if it has use or not. In the test scope
we can select 6 patterns. PAT2 is not one of them.
Thanks
~Khaled
> Manasi
>
> > diff --git a/include/drm/drm_dp_helper.h
> > b/include/drm/drm_dp_helper.h
> > index e47dc22ebf50..65dd6cd71f1e 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -708,7 +708,9 @@
> > # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
> > # define DP_PHY_TEST_PATTERN_PRBS7 0x3
> > # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
> > -# define DP_PHY_TEST_PATTERN_CP2520 0x5
> > +# define DP_PHY_TEST_PATTERN_CP2520_PAT1 0x5
> > +# define DP_PHY_TEST_PATTERN_CP2520_PAT2 0x6
> > +# define DP_PHY_TEST_PATTERN_CP2520_PAT3 0x7
> >
> > #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> > #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> > --
> > 2.17.1
> >
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3
2020-07-21 0:40 ` Almahallawy, Khaled
@ 2020-07-21 18:56 ` Manasi Navare
0 siblings, 0 replies; 7+ messages in thread
From: Manasi Navare @ 2020-07-21 18:56 UTC (permalink / raw)
To: Almahallawy, Khaled; +Cc: intel-gfx, Manna, Animesh, dri-devel
On Mon, Jul 20, 2020 at 05:40:10PM -0700, Almahallawy, Khaled wrote:
> On Mon, 2020-07-20 at 17:07 -0700, Manasi Navare wrote:
> > On Mon, Jul 20, 2020 at 04:41:25PM -0700, Khaled Almahallawy wrote:
> > > Add the missing CP2520 pattern 2 and 3 phy compliance patterns
> > >
> > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
> > > ---
> > > drivers/gpu/drm/drm_dp_helper.c | 2 +-
> > > include/drm/drm_dp_helper.h | 4 +++-
> > > 2 files changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > > b/drivers/gpu/drm/drm_dp_helper.c
> > > index a3c82e726057..d0fb78c6aca6 100644
> > > --- a/drivers/gpu/drm/drm_dp_helper.c
> > > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > > @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct
> > > drm_dp_aux *aux,
> > > return err;
> > >
> > > break;
> > > -case DP_PHY_TEST_PATTERN_CP2520:
> > > +case DP_PHY_TEST_PATTERN_CP2520_PAT1:
> > > err = drm_dp_dpcd_read(aux,
> > > DP_TEST_HBR2_SCRAMBLER_RESET,
> > > &data->hbr2_reset,
> > > sizeof(data->hbr2_reset));
> >
> > Where do we read PAT2 and PAT3, I see you defined those newly and
> > patch 2/2 has them
> > in teh switch case but the drm_dp_get_phy_test_pattern function
> > doesnt read them?
> >
>
> Per my understanding from the specs, only HBR2 (CP2520 PAT1) requires
> reading dpcd address 0024Ah to set HBR2_COMPLIANCT_SCRAMBLER_RESET.
> TPS4 (CP2520 PAT3) doesn’t require that.
> I’m not sure about CP2520 PAT2 if it has use or not. In the test scope
> we can select 6 patterns. PAT2 is not one of them.
>
> Thanks
> ~Khaled
Okay got it, with that
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
>
> > Manasi
> >
> > > diff --git a/include/drm/drm_dp_helper.h
> > > b/include/drm/drm_dp_helper.h
> > > index e47dc22ebf50..65dd6cd71f1e 100644
> > > --- a/include/drm/drm_dp_helper.h
> > > +++ b/include/drm/drm_dp_helper.h
> > > @@ -708,7 +708,9 @@
> > > # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
> > > # define DP_PHY_TEST_PATTERN_PRBS7 0x3
> > > # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
> > > -# define DP_PHY_TEST_PATTERN_CP2520 0x5
> > > +# define DP_PHY_TEST_PATTERN_CP2520_PAT10x5
> > > +# define DP_PHY_TEST_PATTERN_CP2520_PAT20x6
> > > +# define DP_PHY_TEST_PATTERN_CP2520_PAT30x7
> > >
> > > #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> > > #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> > > --
> > > 2.17.1
> > >
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-07-21 18:54 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-20 23:41 [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Khaled Almahallawy
2020-07-20 23:41 ` [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support Khaled Almahallawy
2020-07-21 0:11 ` Manasi Navare
2020-07-21 0:20 ` Almahallawy, Khaled
2020-07-21 0:07 ` [PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3 Manasi Navare
2020-07-21 0:40 ` Almahallawy, Khaled
2020-07-21 18:56 ` Manasi Navare
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).