[PATCH] Optimized division operation to shift operation

[PATCH] Optimized division operation to shift operation

[Bernard Zhao]

On some processors, the / operate will call the compiler`s div lib,
which is low efficient, We can replace the / operation with shift,
so that we can replace the call of the division library with one
shift assembly instruction.

Signed-off-by: Bernard Zhao <bernard@vivo.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index b205039..66cd078 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -175,10 +175,10 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 	amdgpu_ucode_print_mc_hdr(&hdr->header);
 
 	adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
-	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
+	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
 	new_io_mc_regs = (const __le32 *)
 		(adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
-	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
+	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
 	new_fw_data = (const __le32 *)
 		(adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 9da9596..ca26d63 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -193,10 +193,10 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 	amdgpu_ucode_print_mc_hdr(&hdr->header);
 
 	adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
-	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
+	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
 	io_mc_regs = (const __le32 *)
 		(adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
-	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
+	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
 	fw_data = (const __le32 *)
 		(adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 27d83204..295039c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -318,10 +318,10 @@ static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 	amdgpu_ucode_print_mc_hdr(&hdr->header);
 
 	adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
-	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
+	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
 	io_mc_regs = (const __le32 *)
 		(adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
-	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
+	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
 	fw_data = (const __le32 *)
 		(adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 
-- 
2.7.4

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Re: [PATCH] Optimized division operation to shift operation

[Alex Deucher]

On Tue, Apr 14, 2020 at 9:05 AM Bernard Zhao <bernard@vivo.com> wrote:
>
> On some processors, the / operate will call the compiler`s div lib,
> which is low efficient, We can replace the / operation with shift,
> so that we can replace the call of the division library with one
> shift assembly instruction.
>
> Signed-off-by: Bernard Zhao <bernard@vivo.com>

Applied.  thanks.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++--
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++--
>  3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index b205039..66cd078 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -175,10 +175,10 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
>         amdgpu_ucode_print_mc_hdr(&hdr->header);
>
>         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>         new_io_mc_regs = (const __le32 *)
>                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>         new_fw_data = (const __le32 *)
>                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 9da9596..ca26d63 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -193,10 +193,10 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
>         amdgpu_ucode_print_mc_hdr(&hdr->header);
>
>         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>         io_mc_regs = (const __le32 *)
>                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>         fw_data = (const __le32 *)
>                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 27d83204..295039c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -318,10 +318,10 @@ static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
>         amdgpu_ucode_print_mc_hdr(&hdr->header);
>
>         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>         io_mc_regs = (const __le32 *)
>                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>         fw_data = (const __le32 *)
>                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH] Optimized division operation to shift operation

[Jani Nikula]

On Tue, 14 Apr 2020, Alex Deucher <alexdeucher@gmail.com> wrote:
> On Tue, Apr 14, 2020 at 9:05 AM Bernard Zhao <bernard@vivo.com> wrote:
>>
>> On some processors, the / operate will call the compiler`s div lib,
>> which is low efficient, We can replace the / operation with shift,
>> so that we can replace the call of the division library with one
>> shift assembly instruction.

This was applied already, and it's not in a driver I look after... but
to me this feels like something that really should be
justified. Using >> instead of / for multiples of 2 division mattered 20
years ago, I'd be surprised if it still did on modern compilers.

BR,
Jani.


>>
>> Signed-off-by: Bernard Zhao <bernard@vivo.com>
>
> Applied.  thanks.
>
> Alex
>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++--
>>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
>>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++--
>>  3 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> index b205039..66cd078 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> @@ -175,10 +175,10 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
>>         amdgpu_ucode_print_mc_hdr(&hdr->header);
>>
>>         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>>         new_io_mc_regs = (const __le32 *)
>>                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>         new_fw_data = (const __le32 *)
>>                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> index 9da9596..ca26d63 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> @@ -193,10 +193,10 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
>>         amdgpu_ucode_print_mc_hdr(&hdr->header);
>>
>>         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>>         io_mc_regs = (const __le32 *)
>>                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>         fw_data = (const __le32 *)
>>                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> index 27d83204..295039c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> @@ -318,10 +318,10 @@ static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
>>         amdgpu_ucode_print_mc_hdr(&hdr->header);
>>
>>         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>>         io_mc_regs = (const __le32 *)
>>                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>         fw_data = (const __le32 *)
>>                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>>
>> --
>> 2.7.4
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH] Optimized division operation to shift operation

[Christian König]

Am 15.04.20 um 09:41 schrieb Jani Nikula:
> On Tue, 14 Apr 2020, Alex Deucher <alexdeucher@gmail.com> wrote:
>> On Tue, Apr 14, 2020 at 9:05 AM Bernard Zhao <bernard@vivo.com> wrote:
>>> On some processors, the / operate will call the compiler`s div lib,
>>> which is low efficient, We can replace the / operation with shift,
>>> so that we can replace the call of the division library with one
>>> shift assembly instruction.
> This was applied already, and it's not in a driver I look after... but
> to me this feels like something that really should be
> justified. Using >> instead of / for multiples of 2 division mattered 20
> years ago, I'd be surprised if it still did on modern compilers.

I have similar worries, especially since we replace the "/ (4 * 2)" with 
">> 3" it's making the code just a bit less readable.

And that the code runs exactly once while loading the driver and pushing 
the firmware into the hardware. So performance is completely irrelevant 
here.

Regards,
Christian.

>
> BR,
> Jani.
>
>
>>> Signed-off-by: Bernard Zhao <bernard@vivo.com>
>> Applied.  thanks.
>>
>> Alex
>>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++--
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++--
>>>   3 files changed, 6 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> index b205039..66cd078 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> @@ -175,10 +175,10 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
>>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
>>>
>>>          adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
>>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
>>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>>>          new_io_mc_regs = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
>>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
>>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>>          new_fw_data = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> index 9da9596..ca26d63 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> @@ -193,10 +193,10 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
>>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
>>>
>>>          adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
>>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
>>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>>>          io_mc_regs = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
>>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
>>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>>          fw_data = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> index 27d83204..295039c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> @@ -318,10 +318,10 @@ static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
>>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
>>>
>>>          adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
>>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
>>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>>>          io_mc_regs = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
>>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
>>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>>          fw_data = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>>>
>>> --
>>> 2.7.4
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C1e91f7edcfe0473b0d7008d7e11074a8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637225333103893889&amp;sdata=VDJlEY2%2Bl1SSO8Fw1dYqqPFqQtyHpsxQ0Tm7iVOgJQY%3D&amp;reserved=0
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Re: [PATCH] Optimized division operation to shift operation

[Daniel Vetter]

On Wed, Apr 15, 2020 at 9:57 AM Christian König
<christian.koenig@amd.com> wrote:
>
> Am 15.04.20 um 09:41 schrieb Jani Nikula:
> > On Tue, 14 Apr 2020, Alex Deucher <alexdeucher@gmail.com> wrote:
> >> On Tue, Apr 14, 2020 at 9:05 AM Bernard Zhao <bernard@vivo.com> wrote:
> >>> On some processors, the / operate will call the compiler`s div lib,
> >>> which is low efficient, We can replace the / operation with shift,
> >>> so that we can replace the call of the division library with one
> >>> shift assembly instruction.
> > This was applied already, and it's not in a driver I look after... but
> > to me this feels like something that really should be
> > justified. Using >> instead of / for multiples of 2 division mattered 20
> > years ago, I'd be surprised if it still did on modern compilers.
>
> I have similar worries, especially since we replace the "/ (4 * 2)" with
> ">> 3" it's making the code just a bit less readable.
>
> And that the code runs exactly once while loading the driver and pushing
> the firmware into the hardware. So performance is completely irrelevant
> here.

Yeah, and even in general I'd really want to see proof that such bad
compilers exist first. Doing a peephole pass for stuff like this is
like undergrad compiler course stuff. Also I'd trust the compiler's
call on which is faster much more than humans doing a manual peephole
pass.

Or am I just massively biased from all the layman following of what
kind of our gl/vk/compute compiler people are doing on a daily basis?
-Daniel

>
> Regards,
> Christian.
>
> >
> > BR,
> > Jani.
> >
> >
> >>> Signed-off-by: Bernard Zhao <bernard@vivo.com>
> >> Applied.  thanks.
> >>
> >> Alex
> >>
> >>> ---
> >>>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++--
> >>>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
> >>>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++--
> >>>   3 files changed, 6 insertions(+), 6 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> >>> index b205039..66cd078 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> >>> @@ -175,10 +175,10 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
> >>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
> >>>
> >>>          adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
> >>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
> >>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
> >>>          new_io_mc_regs = (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
> >>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
> >>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
> >>>          new_fw_data = (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >>> index 9da9596..ca26d63 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >>> @@ -193,10 +193,10 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
> >>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
> >>>
> >>>          adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
> >>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
> >>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
> >>>          io_mc_regs = (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
> >>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
> >>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
> >>>          fw_data = (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> >>> index 27d83204..295039c 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> >>> @@ -318,10 +318,10 @@ static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
> >>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
> >>>
> >>>          adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
> >>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
> >>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
> >>>          io_mc_regs = (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
> >>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
> >>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
> >>>          fw_data = (const __le32 *)
> >>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
> >>>
> >>> --
> >>> 2.7.4
> >>>
> >>> _______________________________________________
> >>> amd-gfx mailing list
> >>> amd-gfx@lists.freedesktop.org
> >>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C1e91f7edcfe0473b0d7008d7e11074a8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637225333103893889&amp;sdata=VDJlEY2%2Bl1SSO8Fw1dYqqPFqQtyHpsxQ0Tm7iVOgJQY%3D&amp;reserved=0
> >> _______________________________________________
> >> dri-devel mailing list
> >> dri-devel@lists.freedesktop.org
> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C1e91f7edcfe0473b0d7008d7e11074a8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637225333103893889&amp;sdata=EpqRRbCiksur%2BjMlVQplExuJsmw6UPODhyBOutOVukw%3D&amp;reserved=0
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel



-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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RE: [PATCH] Optimized division operation to shift operation

[David Laight]

From: Christian König
> Sent: 15 April 2020 08:57
> Am 15.04.20 um 09:41 schrieb Jani Nikula:
> > On Tue, 14 Apr 2020, Alex Deucher <alexdeucher@gmail.com> wrote:
> >> On Tue, Apr 14, 2020 at 9:05 AM Bernard Zhao <bernard@vivo.com> wrote:
> >>> On some processors, the / operate will call the compiler`s div lib,
> >>> which is low efficient, We can replace the / operation with shift,
> >>> so that we can replace the call of the division library with one
> >>> shift assembly instruction.
> > This was applied already, and it's not in a driver I look after... but
> > to me this feels like something that really should be
> > justified. Using >> instead of / for multiples of 2 division mattered 20
> > years ago, I'd be surprised if it still did on modern compilers.
> 
> I have similar worries, especially since we replace the "/ (4 * 2)" with
> ">> 3" it's making the code just a bit less readable.
> 
> And that the code runs exactly once while loading the driver and pushing
> the firmware into the hardware. So performance is completely irrelevant
> here.

Force the division to be unsigned and the compiler will use a shift.

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
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Re: [PATCH] Optimized division operation to shift operation

[Deucher, Alexander]

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[AMD Public Use]

I've gone ahead and dropped the patch.

Alex
________________________________
From: Koenig, Christian <Christian.Koenig@amd.com>
Sent: Wednesday, April 15, 2020 3:57 AM
To: Jani Nikula <jani.nikula@linux.intel.com>; Alex Deucher <alexdeucher@gmail.com>; Bernard Zhao <bernard@vivo.com>
Cc: Sierra Guiza, Alejandro (Alex) <Alex.Sierra@amd.com>; Zeng, Oak <Oak.Zeng@amd.com>; Maling list - DRI developers <dri-devel@lists.freedesktop.org>; David Airlie <airlied@linux.ie>; Kuehling, Felix <Felix.Kuehling@amd.com>; LKML <linux-kernel@vger.kernel.org>; amd-gfx list <amd-gfx@lists.freedesktop.org>; kernel@vivo.com <kernel@vivo.com>; Huang, Ray <Ray.Huang@amd.com>; Russell, Kent <Kent.Russell@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Sam Ravnborg <sam@ravnborg.org>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>
Subject: Re: [PATCH] Optimized division operation to shift operation

Am 15.04.20 um 09:41 schrieb Jani Nikula:
> On Tue, 14 Apr 2020, Alex Deucher <alexdeucher@gmail.com> wrote:
>> On Tue, Apr 14, 2020 at 9:05 AM Bernard Zhao <bernard@vivo.com> wrote:
>>> On some processors, the / operate will call the compiler`s div lib,
>>> which is low efficient, We can replace the / operation with shift,
>>> so that we can replace the call of the division library with one
>>> shift assembly instruction.
> This was applied already, and it's not in a driver I look after... but
> to me this feels like something that really should be
> justified. Using >> instead of / for multiples of 2 division mattered 20
> years ago, I'd be surprised if it still did on modern compilers.

I have similar worries, especially since we replace the "/ (4 * 2)" with
">> 3" it's making the code just a bit less readable.

And that the code runs exactly once while loading the driver and pushing
the firmware into the hardware. So performance is completely irrelevant
here.

Regards,
Christian.

>
> BR,
> Jani.
>
>
>>> Signed-off-by: Bernard Zhao <bernard@vivo.com>
>> Applied.  thanks.
>>
>> Alex
>>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++--
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++--
>>>   3 files changed, 6 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> index b205039..66cd078 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> @@ -175,10 +175,10 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
>>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
>>>
>>>          adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
>>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
>>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>>>          new_io_mc_regs = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
>>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
>>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>>          new_fw_data = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> index 9da9596..ca26d63 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> @@ -193,10 +193,10 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
>>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
>>>
>>>          adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
>>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
>>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>>>          io_mc_regs = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
>>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
>>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>>          fw_data = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> index 27d83204..295039c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> @@ -318,10 +318,10 @@ static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
>>>          amdgpu_ucode_print_mc_hdr(&hdr->header);
>>>
>>>          adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
>>> -       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
>>> +       regs_size = le32_to_cpu(hdr->io_debug_size_bytes) >> 3;
>>>          io_mc_regs = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
>>> -       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
>>> +       ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>>          fw_data = (const __le32 *)
>>>                  (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>>>
>>> --
>>> 2.7.4
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C1e91f7edcfe0473b0d7008d7e11074a8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637225333103893889&amp;sdata=VDJlEY2%2Bl1SSO8Fw1dYqqPFqQtyHpsxQ0Tm7iVOgJQY%3D&amp;reserved=0
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C1e91f7edcfe0473b0d7008d7e11074a8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637225333103893889&amp;sdata=EpqRRbCiksur%2BjMlVQplExuJsmw6UPODhyBOutOVukw%3D&amp;reserved=0


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