* [PATCH 0/5] staging: mt7621-pci-phy: Use only two phys to avoid unstable pcie links
@ 2020-03-20 11:01 Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 1/5] staging: mt7621-pci-phy: avoid to create to different phys for a dual port one Sergio Paracuellos
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Sergio Paracuellos @ 2020-03-20 11:01 UTC (permalink / raw)
To: gregkh; +Cc: neil, driverdev-devel, gerg
Mt7621 soc has two phy's for the pcie one of them using just a different
register for settig it up but sharing all the rest of the config. Until
now we was presenting this schema as three different phy's in the device
tree using the 'phy-cells' node property to discriminate an index and setting
up a complete phy for the dual port index. This sometimes worked properly
but reconfiguring the same registers twice presents sometimes some unstable
pcie links and the ports was not properly being detected. The problems
only appears on hard resets and soft resets was properly working. Instead
of having this schema just set two phy's in the device tree and use the
'phy-cells' property to say if the port has or not a dual port. Doing
this configuration and set up becomes easier, LOC is decreased and the
behaviour also gets deterministic with properly and stable pcie links in
both hard and soft resets.
Device tree and controller driver have been also updated to be aligned with
this changes.
Other minor two patches are included in this series:
* One changing a variable in a prunt trace.
* Other to set to NULL gpio descriptor if getting it failed for some reason.
This changes have been tested in gnubee PC1 resulting in a totally working
PCI system without any incidence in more that ten hard resets:
Trace:
[ 16.543950] mt7621-pci-phy 1e149000.pcie-phy: PHY for 0xbe149000 (dual port = 1)
[ 16.558831] mt7621-pci-phy 1e14a000.pcie-phy: PHY for 0xbe14a000 (dual port = 0)
[ 16.673539] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
[ 16.684656] mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
[ 16.795657] mt7621-pci 1e140000.pcie: PCIE0 enabled
[ 16.805374] mt7621-pci 1e140000.pcie: PCIE1 enabled
[ 16.815091] mt7621-pci 1e140000.pcie: PCIE2 enabled
[ 16.824816] mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
[ 16.843544] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
[ 16.856224] pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff]
[ 16.869922] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
[ 16.883619] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 16.894613] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400
[ 16.906615] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff]
[ 16.919106] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 16.931676] pci 0000:00:00.0: supports D1
[ 16.939668] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[ 16.951486] pci 0000:00:01.0: [0e8d:0801] type 01 class 0x060400
[ 16.963496] pci 0000:00:01.0: reg 0x10: [mem 0x00000000-0x7fffffff]
[ 16.975989] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 16.988546] pci 0000:00:01.0: supports D1
[ 16.996538] pci 0000:00:01.0: PME# supported from D0 D1 D3hot
[ 17.008296] pci 0000:00:02.0: [0e8d:0801] type 01 class 0x060400
[ 17.020305] pci 0000:00:02.0: reg 0x10: [mem 0x00000000-0x7fffffff]
[ 17.032802] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 17.045359] pci 0000:00:02.0: supports D1
[ 17.053325] pci 0000:00:02.0: PME# supported from D0 D1 D3hot
[ 17.065945] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 17.081913] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 17.097858] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 17.114063] pci 0000:01:00.0: [1b21:0611] type 00 class 0x010185
[ 17.126080] pci 0000:01:00.0: reg 0x10: [io 0x0000-0x0007]
[ 17.137192] pci 0000:01:00.0: reg 0x14: [io 0x0000-0x0003]
[ 17.148308] pci 0000:01:00.0: reg 0x18: [io 0x0000-0x0007]
[ 17.159426] pci 0000:01:00.0: reg 0x1c: [io 0x0000-0x0003]
[ 17.170538] pci 0000:01:00.0: reg 0x20: [io 0x0000-0x000f]
[ 17.181656] pci 0000:01:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
[ 17.194293] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
[ 17.223008] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[ 17.233445] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]
[ 17.245593] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
[ 17.259119] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff pref]
[ 17.273510] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 17.286904] pci 0000:02:00.0: [1b21:0611] type 00 class 0x010185
[ 17.298927] pci 0000:02:00.0: reg 0x10: [io 0x0000-0x0007]
[ 17.310039] pci 0000:02:00.0: reg 0x14: [io 0x0000-0x0003]
[ 17.321150] pci 0000:02:00.0: reg 0x18: [io 0x0000-0x0007]
[ 17.332262] pci 0000:02:00.0: reg 0x1c: [io 0x0000-0x0003]
[ 17.343372] pci 0000:02:00.0: reg 0x20: [io 0x0000-0x000f]
[ 17.354484] pci 0000:02:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
[ 17.367118] pci 0000:02:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:01.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
[ 17.395830] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
[ 17.406265] pci 0000:00:01.0: bridge window [io 0x0000-0x0fff]
[ 17.418411] pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff]
[ 17.431935] pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff pref]
[ 17.446325] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
[ 17.459716] pci 0000:03:00.0: [1b21:0611] type 00 class 0x010185
[ 17.471731] pci 0000:03:00.0: reg 0x10: [io 0x0000-0x0007]
[ 17.482844] pci 0000:03:00.0: reg 0x14: [io 0x0000-0x0003]
[ 17.493958] pci 0000:03:00.0: reg 0x18: [io 0x0000-0x0007]
[ 17.505069] pci 0000:03:00.0: reg 0x1c: [io 0x0000-0x0003]
[ 17.516180] pci 0000:03:00.0: reg 0x20: [io 0x0000-0x000f]
[ 17.527291] pci 0000:03:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
[ 17.539922] pci 0000:03:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:02.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
[ 17.568645] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
[ 17.579079] pci 0000:00:02.0: bridge window [io 0x0000-0x0fff]
[ 17.591220] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff]
[ 17.604744] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff pref]
[ 17.619136] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
[ 17.632385] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
[ 17.645563] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
[ 17.659436] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
[ 17.672612] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
[ 17.686482] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
[ 17.699665] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
[ 17.713537] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
[ 17.727064] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
[ 17.741455] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
[ 17.754981] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x603fffff pref]
[ 17.769372] pci 0000:00:02.0: BAR 8: assigned [mem 0x60400000-0x604fffff]
[ 17.782899] pci 0000:00:02.0: BAR 9: assigned [mem 0x60500000-0x605fffff pref]
[ 17.797290] pci 0000:00:00.0: BAR 1: assigned [mem 0x60600000-0x6060ffff]
[ 17.810823] pci 0000:00:01.0: BAR 1: assigned [mem 0x60610000-0x6061ffff]
[ 17.824359] pci 0000:00:02.0: BAR 1: assigned [mem 0x60620000-0x6062ffff]
[ 17.837888] pci 0000:00:00.0: BAR 7: assigned [io 0x1e160000-0x1e160fff]
[ 17.851414] pci 0000:00:01.0: BAR 7: assigned [io 0x1e161000-0x1e161fff]
[ 17.864940] pci 0000:00:02.0: BAR 7: assigned [io 0x1e162000-0x1e162fff]
[ 17.878482] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
[ 17.892012] pci 0000:01:00.0: BAR 4: assigned [io 0x1e160000-0x1e16000f]
[ 17.905543] pci 0000:01:00.0: BAR 0: assigned [io 0x1e160010-0x1e160017]
[ 17.919073] pci 0000:01:00.0: BAR 2: assigned [io 0x1e160018-0x1e16001f]
[ 17.932604] pci 0000:01:00.0: BAR 1: assigned [io 0x1e160020-0x1e160023]
[ 17.946134] pci 0000:01:00.0: BAR 3: assigned [io 0x1e160024-0x1e160027]
[ 17.959671] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 17.969566] pci 0000:00:00.0: bridge window [io 0x1e160000-0x1e160fff]
[ 17.983090] pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff]
[ 17.996614] pci 0000:00:00.0: bridge window [mem 0x60100000-0x601fffff pref]
[ 18.011012] pci 0000:02:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
[ 18.024542] pci 0000:02:00.0: BAR 4: assigned [io 0x1e161000-0x1e16100f]
[ 18.038073] pci 0000:02:00.0: BAR 0: assigned [io 0x1e161010-0x1e161017]
[ 18.051604] pci 0000:02:00.0: BAR 2: assigned [io 0x1e161018-0x1e16101f]
[ 18.065134] pci 0000:02:00.0: BAR 1: assigned [io 0x1e161020-0x1e161023]
[ 18.078666] pci 0000:02:00.0: BAR 3: assigned [io 0x1e161024-0x1e161027]
[ 18.092200] pci 0000:00:01.0: PCI bridge to [bus 02]
[ 18.102095] pci 0000:00:01.0: bridge window [io 0x1e161000-0x1e161fff]
[ 18.115617] pci 0000:00:01.0: bridge window [mem 0x60200000-0x602fffff]
[ 18.129142] pci 0000:00:01.0: bridge window [mem 0x60300000-0x603fffff pref]
[ 18.143540] pci 0000:03:00.0: BAR 5: assigned [mem 0x60400000-0x604001ff]
[ 18.157074] pci 0000:03:00.0: BAR 4: assigned [io 0x1e162000-0x1e16200f]
[ 18.170606] pci 0000:03:00.0: BAR 0: assigned [io 0x1e162010-0x1e162017]
[ 18.184136] pci 0000:03:00.0: BAR 2: assigned [io 0x1e162018-0x1e16201f]
[ 18.197667] pci 0000:03:00.0: BAR 1: assigned [io 0x1e162020-0x1e162023]
[ 18.211196] pci 0000:03:00.0: BAR 3: assigned [io 0x1e162024-0x1e162027]
[ 18.224734] pci 0000:00:02.0: PCI bridge to [bus 03]
[ 18.234630] pci 0000:00:02.0: bridge window [io 0x1e162000-0x1e162fff]
[ 18.248153] pci 0000:00:02.0: bridge window [mem 0x60400000-0x604fffff]
[ 18.261675] pci 0000:00:02.0: bridge window [mem 0x60500000-0x605fffff pref]
Sergio Paracuellos (5):
staging: mt7621-pci-phy: avoid to create to different phys for a dual
port one
staging: mt7621-dts: set up only two pcie phys
staging: mt7621-pci: use only two phys from device tree
staging: mt7621-pci: change variable to print for slot
staging: mt7621-pci: be sure gpio descriptor is null on fails
drivers/staging/mt7621-dts/mt7621.dtsi | 6 +-
.../staging/mt7621-pci-phy/pci-mt7621-phy.c | 144 +++++++-----------
drivers/staging/mt7621-pci/pci-mt7621.c | 13 +-
3 files changed, 72 insertions(+), 91 deletions(-)
--
2.25.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/5] staging: mt7621-pci-phy: avoid to create to different phys for a dual port one
2020-03-20 11:01 [PATCH 0/5] staging: mt7621-pci-phy: Use only two phys to avoid unstable pcie links Sergio Paracuellos
@ 2020-03-20 11:01 ` Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 2/5] staging: mt7621-dts: set up only two pcie phys Sergio Paracuellos
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Sergio Paracuellos @ 2020-03-20 11:01 UTC (permalink / raw)
To: gregkh; +Cc: neil, driverdev-devel, gerg
This soc has two phy's for the pcie one of them using just a different
register for settig it up but sharing all the rest of the config. Until
now we was presenting this schema as three different phy's in the device
tree using the 'phy-cells' node property to discriminate an index and
setting up a complete phy for the dual port index. This sometimes worked
properly but reconfiguring the same registers twice presents sometimes
some unstable pcie links and the ports was not properly being detected.
The problems only appears on hard resets and soft resets was properly
working. Instead of having this schema just set two phy's in the device
ree and use the 'phy-cells' property to say if the port has or not a dual
port. Doing this configuration and set up becomes easier, LOC is decreased
and the behaviour also gets deterministic with properly and stable pcie
links in both hard and soft resets.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
.../staging/mt7621-pci-phy/pci-mt7621-phy.c | 144 +++++++-----------
1 file changed, 59 insertions(+), 85 deletions(-)
diff --git a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
index 648f0c8df003..63dfbb85af11 100644
--- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
+++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
@@ -77,32 +77,22 @@
#define MAX_PHYS 2
-/**
- * struct mt7621_pci_phy_instance - Mt7621 Pcie PHY device
- * @phy: pointer to the kernel PHY device
- * @port_base: base register
- * @index: internal ID to identify the Mt7621 PCIe PHY
- */
-struct mt7621_pci_phy_instance {
- struct phy *phy;
- void __iomem *port_base;
- u32 index;
-};
-
/**
* struct mt7621_pci_phy - Mt7621 Pcie PHY core
* @dev: pointer to device
* @regmap: kernel regmap pointer
- * @phys: pointer to Mt7621 PHY device
- * @nphys: number of PHY devices for this core
+ * @phy: pointer to the kernel PHY device
+ * @port_base: base register
+ * @has_dual_port: if the phy has dual ports.
* @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst'
* needs to be executed. Depends on chip revision.
*/
struct mt7621_pci_phy {
struct device *dev;
struct regmap *regmap;
- struct mt7621_pci_phy_instance **phys;
- int nphys;
+ struct phy *phy;
+ void __iomem *port_base;
+ bool has_dual_port;
bool bypass_pipe_rst;
};
@@ -130,23 +120,23 @@ static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy,
phy_write(phy, val, reg);
}
-static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy,
- struct mt7621_pci_phy_instance *instance)
+static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy)
{
- u32 offset = (instance->index != 1) ?
- RG_PE1_PIPE_REG : RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH;
-
- mt7621_phy_rmw(phy, offset,
- RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC,
- RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_RST);
+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_CMD_FRC);
+
+ if (phy->has_dual_port) {
+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
+ 0, RG_PE1_PIPE_RST);
+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
+ 0, RG_PE1_PIPE_CMD_FRC);
+ }
}
-static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy,
- struct mt7621_pci_phy_instance *instance)
+static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy)
{
struct device *dev = phy->dev;
u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
- u32 offset;
reg = (reg >> 6) & 0x7;
/* Set PCIe Port PHY to disable SSC */
@@ -156,10 +146,13 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy,
RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE_VAL(0x00));
/* disable port */
- offset = (instance->index != 1) ?
- RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
- mt7621_phy_rmw(phy, offset,
- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
+ mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG,
+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
+
+ if (phy->has_dual_port) {
+ mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
+ }
if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
/* Set Pre-divider ratio (for host mode) */
@@ -223,43 +216,44 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy,
static int mt7621_pci_phy_init(struct phy *phy)
{
- struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
- struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
if (mphy->bypass_pipe_rst)
- mt7621_bypass_pipe_rst(mphy, instance);
+ mt7621_bypass_pipe_rst(mphy);
- mt7621_set_phy_for_ssc(mphy, instance);
+ mt7621_set_phy_for_ssc(mphy);
return 0;
}
static int mt7621_pci_phy_power_on(struct phy *phy)
{
- struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
- struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
- u32 offset = (instance->index != 1) ?
- RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
/* Enable PHY and disable force mode */
- mt7621_phy_rmw(mphy, offset,
- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN,
- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
+ RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
+
+ if (mphy->has_dual_port) {
+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
+ RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
+ }
return 0;
}
static int mt7621_pci_phy_power_off(struct phy *phy)
{
- struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
- struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
- u32 offset = (instance->index != 1) ?
- RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
/* Disable PHY */
- mt7621_phy_rmw(mphy, offset,
- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN,
- RG_PE1_FRC_PHY_EN);
+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
+
+ if (mphy->has_dual_port) {
+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
+ }
return 0;
}
@@ -282,13 +276,15 @@ static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev,
{
struct mt7621_pci_phy *mt7621_phy = dev_get_drvdata(dev);
- if (args->args_count == 0)
- return mt7621_phy->phys[0]->phy;
-
if (WARN_ON(args->args[0] >= MAX_PHYS))
return ERR_PTR(-ENODEV);
- return mt7621_phy->phys[args->args[0]]->phy;
+ mt7621_phy->has_dual_port = args->args[0];
+
+ dev_info(dev, "PHY for 0x%08x (dual port = %d)\n",
+ (unsigned int)mt7621_phy->port_base, mt7621_phy->has_dual_port);
+
+ return mt7621_phy->phy;
}
static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
@@ -309,19 +305,11 @@ static int mt7621_pci_phy_probe(struct platform_device *pdev)
struct phy_provider *provider;
struct mt7621_pci_phy *phy;
struct resource *res;
- int port;
- void __iomem *port_base;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
return -ENOMEM;
- phy->nphys = MAX_PHYS;
- phy->phys = devm_kcalloc(dev, phy->nphys,
- sizeof(*phy->phys), GFP_KERNEL);
- if (!phy->phys)
- return -ENOMEM;
-
attr = soc_device_match(mt7621_pci_quirks_match);
if (attr)
phy->bypass_pipe_rst = true;
@@ -335,39 +323,25 @@ static int mt7621_pci_phy_probe(struct platform_device *pdev)
return -ENXIO;
}
- port_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(port_base)) {
+ phy->port_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(phy->port_base)) {
dev_err(dev, "failed to remap phy regs\n");
- return PTR_ERR(port_base);
+ return PTR_ERR(phy->port_base);
}
- phy->regmap = devm_regmap_init_mmio(phy->dev, port_base,
+ phy->regmap = devm_regmap_init_mmio(phy->dev, phy->port_base,
&mt7621_pci_phy_regmap_config);
if (IS_ERR(phy->regmap))
return PTR_ERR(phy->regmap);
- for (port = 0; port < MAX_PHYS; port++) {
- struct mt7621_pci_phy_instance *instance;
- struct phy *pphy;
-
- instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
- if (!instance)
- return -ENOMEM;
-
- phy->phys[port] = instance;
-
- pphy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops);
- if (IS_ERR(phy)) {
- dev_err(dev, "failed to create phy\n");
- return PTR_ERR(phy);
- }
-
- instance->port_base = port_base;
- instance->phy = pphy;
- instance->index = port;
- phy_set_drvdata(pphy, instance);
+ phy->phy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create phy\n");
+ return PTR_ERR(phy);
}
+ phy_set_drvdata(phy->phy, phy);
+
provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate);
return PTR_ERR_OR_ZERO(provider);
--
2.25.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/5] staging: mt7621-dts: set up only two pcie phys
2020-03-20 11:01 [PATCH 0/5] staging: mt7621-pci-phy: Use only two phys to avoid unstable pcie links Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 1/5] staging: mt7621-pci-phy: avoid to create to different phys for a dual port one Sergio Paracuellos
@ 2020-03-20 11:01 ` Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 3/5] staging: mt7621-pci: use only two phys from device tree Sergio Paracuellos
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Sergio Paracuellos @ 2020-03-20 11:01 UTC (permalink / raw)
To: gregkh; +Cc: neil, driverdev-devel, gerg
This soc has only two real pcie phys one of them
having a different register to enable and disable it.
Change this to have only two dt nodes for the phys and
use 'phy-cells' properly to say if the phy has dual ports.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 488474153535..10fb497cf81a 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -535,8 +535,8 @@ pcie: pcie@1e140000 {
reset-names = "pcie0", "pcie1", "pcie2";
clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
clock-names = "pcie0", "pcie1", "pcie2";
- phys = <&pcie0_phy 0>, <&pcie0_phy 1>, <&pcie1_phy 0>;
- phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+ phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
+ phy-names = "pcie-phy0", "pcie-phy2";
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
<&gpio 8 GPIO_ACTIVE_LOW>,
@@ -573,7 +573,7 @@ pcie0_phy: pcie-phy@1e149000 {
#phy-cells = <1>;
};
- pcie1_phy: pcie-phy@1e14a000 {
+ pcie2_phy: pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e14a000 0x0700>;
#phy-cells = <1>;
--
2.25.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/5] staging: mt7621-pci: use only two phys from device tree
2020-03-20 11:01 [PATCH 0/5] staging: mt7621-pci-phy: Use only two phys to avoid unstable pcie links Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 1/5] staging: mt7621-pci-phy: avoid to create to different phys for a dual port one Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 2/5] staging: mt7621-dts: set up only two pcie phys Sergio Paracuellos
@ 2020-03-20 11:01 ` Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 4/5] staging: mt7621-pci: change variable to print for slot Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 5/5] staging: mt7621-pci: be sure gpio descriptor is null on fails Sergio Paracuellos
4 siblings, 0 replies; 6+ messages in thread
From: Sergio Paracuellos @ 2020-03-20 11:01 UTC (permalink / raw)
To: gregkh; +Cc: neil, driverdev-devel, gerg
In order to align work with the mt7621-pci-phy part of
the driver and device tree which is now using only two
real phys one of them dual ported properly parse the
device tree and don't call phy initialization for the
slot 1 because is being taking into account when the
phy for the slot 0 is instantiated.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index d6fc8a08c9bd..a521653d8dba 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -358,7 +358,7 @@ static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
snprintf(name, sizeof(name), "pcie-phy%d", slot);
port->phy = devm_phy_get(dev, name);
- if (IS_ERR(port->phy))
+ if (IS_ERR(port->phy) && slot != 1)
return PTR_ERR(port->phy);
port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
@@ -495,6 +495,11 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
u32 slot = port->slot;
+ if (slot == 1) {
+ port->enabled = true;
+ continue;
+ }
+
err = mt7621_pcie_init_port(port);
if (err) {
dev_err(dev, "Initiating port %d failed\n", slot);
--
2.25.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/5] staging: mt7621-pci: change variable to print for slot
2020-03-20 11:01 [PATCH 0/5] staging: mt7621-pci-phy: Use only two phys to avoid unstable pcie links Sergio Paracuellos
` (2 preceding siblings ...)
2020-03-20 11:01 ` [PATCH 3/5] staging: mt7621-pci: use only two phys from device tree Sergio Paracuellos
@ 2020-03-20 11:01 ` Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 5/5] staging: mt7621-pci: be sure gpio descriptor is null on fails Sergio Paracuellos
4 siblings, 0 replies; 6+ messages in thread
From: Sergio Paracuellos @ 2020-03-20 11:01 UTC (permalink / raw)
To: gregkh; +Cc: neil, driverdev-devel, gerg
We are using the counter to print the slot which has been
enabled. Use the correct associated slot for the port instead.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index a521653d8dba..bc410c3d9afc 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -562,7 +562,7 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
if (port->enabled) {
mt7621_pcie_port_clk_enable(port);
mt7621_pcie_enable_port(port);
- dev_info(dev, "PCIE%d enabled\n", num_slots_enabled);
+ dev_info(dev, "PCIE%d enabled\n", port->slot);
num_slots_enabled++;
}
}
--
2.25.1
_______________________________________________
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devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5/5] staging: mt7621-pci: be sure gpio descriptor is null on fails
2020-03-20 11:01 [PATCH 0/5] staging: mt7621-pci-phy: Use only two phys to avoid unstable pcie links Sergio Paracuellos
` (3 preceding siblings ...)
2020-03-20 11:01 ` [PATCH 4/5] staging: mt7621-pci: change variable to print for slot Sergio Paracuellos
@ 2020-03-20 11:01 ` Sergio Paracuellos
4 siblings, 0 replies; 6+ messages in thread
From: Sergio Paracuellos @ 2020-03-20 11:01 UTC (permalink / raw)
To: gregkh; +Cc: neil, driverdev-devel, gerg
Function 'devm_gpiod_get_index_optional' returns NULL if the
descriptor is invalid and the error associated for the error
pointer is ENOENT. Sometimes if the pin is just assigned the
error associated for the pointer might not be ENOENT but other.
In order to avoid weirds behaviours if this happen set descriptor
to NULL in the driver port structure.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index bc410c3d9afc..739504f7e4fc 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -363,8 +363,10 @@ static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
GPIOD_OUT_LOW);
- if (IS_ERR(port->gpio_rst))
+ if (IS_ERR(port->gpio_rst)) {
dev_notice(dev, "Failed to get GPIO for PCIe%d\n", slot);
+ port->gpio_rst = NULL;
+ }
port->slot = slot;
port->pcie = pcie;
--
2.25.1
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http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-03-20 11:01 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-20 11:01 [PATCH 0/5] staging: mt7621-pci-phy: Use only two phys to avoid unstable pcie links Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 1/5] staging: mt7621-pci-phy: avoid to create to different phys for a dual port one Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 2/5] staging: mt7621-dts: set up only two pcie phys Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 3/5] staging: mt7621-pci: use only two phys from device tree Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 4/5] staging: mt7621-pci: change variable to print for slot Sergio Paracuellos
2020-03-20 11:01 ` [PATCH 5/5] staging: mt7621-pci: be sure gpio descriptor is null on fails Sergio Paracuellos
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