From: Rob Herring <robh@kernel.org>
To: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org,
tsbogend@alpha.franken.de, sboyd@kernel.org,
gregkh@linuxfoundation.org, linux-mips@vger.kernel.org,
linux-kernel@vger.kernel.org, john@phrozen.org, neil@brown.name,
linux-clk@vger.kernel.org
Subject: Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation
Date: Fri, 5 Mar 2021 16:47:56 -0600 [thread overview]
Message-ID: <20210305224756.GA777984@robh.at.kernel.org> (raw)
In-Reply-To: <20210218070709.11932-3-sergio.paracuellos@gmail.com>
On Thu, Feb 18, 2021 at 08:07:05AM +0100, Sergio Paracuellos wrote:
> Adds device tree binding documentation for clocks in the
> MT7621 SOC.
>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
> .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++++++++++++++++++
> 1 file changed, 66 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> new file mode 100644
> index 000000000000..842a0f2c9d40
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MT7621 Clock Device Tree Bindings
> +
> +maintainers:
> + - Sergio Paracuellos <sergio.paracuellos@gmail.com>
> +
> +description: |
> + The MT7621 has a PLL controller from where the cpu clock is provided
> + as well as derived clocks for the bus and the peripherals. It also
> + can gate SoC device clocks.
> +
> + Each clock is assigned an identifier and client nodes use this identifier
> + to specify the clock which they consume.
> +
> + All these identifiers could be found in:
> + [1]: <include/dt-bindings/clock/mt7621-clk.h>.
> +
> +properties:
> + compatible:
> + const: mediatek,mt7621-clk
> +
> + "#clock-cells":
> + description:
> + The first cell indicates the clock number, see [1] for available
> + clocks.
> + const: 1
> +
> + ralink,sysctl:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle of syscon used to control system registers
> +
> + ralink,memctl:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle of syscon used to control memory registers
I assume one of these phandles are the main registers for the clocks?
Make this a child node and drop that phandle.
> +
> + clock-output-names:
> + maxItems: 8
> +
> +required:
> + - compatible
> + - '#clock-cells'
> + - ralink,sysctl
> + - ralink,memctl
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt7621-clk.h>
> +
> + pll {
> + compatible = "mediatek,mt7621-clk";
> + #clock-cells = <1>;
> + ralink,sysctl = <&sysc>;
> + ralink,memctl = <&memc>;
> + clock-output-names = "xtal", "cpu", "bus",
> + "50m", "125m", "150m",
> + "250m", "270m";
> + };
> --
> 2.25.1
>
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next prev parent reply other threads:[~2021-03-05 22:48 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-18 7:07 [PATCH v9 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621 Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation Sergio Paracuellos
2021-03-05 22:47 ` Rob Herring [this message]
2021-03-06 1:52 ` Chuanhong Guo
2021-03-06 7:12 ` Sergio Paracuellos
2021-03-06 9:54 ` Sergio Paracuellos
2021-03-07 6:27 ` Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 3/6] clk: ralink: add clock driver for mt7621 SoC Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 4/6] staging: mt7621-dts: make use of new 'mt7621-clk' Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 6/6] MAINTAINERS: add MT7621 CLOCK maintainer Sergio Paracuellos
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