From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: Rob Herring <robh@kernel.org>
Cc: "open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Stephen Boyd <sboyd@kernel.org>,
Greg KH <gregkh@linuxfoundation.org>,
"open list:MIPS" <linux-mips@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
John Crispin <john@phrozen.org>, NeilBrown <neil@brown.name>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation
Date: Sat, 6 Mar 2021 08:12:43 +0100 [thread overview]
Message-ID: <CAMhs-H_RoA-JvT9Q1K+8tEA1vqS6HWuE-D4=kWVsoOWTwjTGbw@mail.gmail.com> (raw)
In-Reply-To: <20210305224756.GA777984@robh.at.kernel.org>
Hi Rob,
On Fri, Mar 5, 2021 at 11:47 PM Rob Herring <robh@kernel.org> wrote:
[snip]
> > +
> > + ralink,sysctl:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + phandle of syscon used to control system registers
> > +
> > + ralink,memctl:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + phandle of syscon used to control memory registers
>
> I assume one of these phandles are the main registers for the clocks?
> Make this a child node and drop that phandle.
The 'ralink,sysctl' phandle is to read bootstrap register to be able
to derive xtal and a clk gate register for the peripherals.
The 'ralink,memctl' phandle is to read the cpu clock frequency from
the memory controller.
So there is not "main registers". I already put this as a child node
in v4 and I was told to get rid of child nodes. I need this as a
regmap to other DT node registers (sysctl, and memctl) to be able to
use the driver without specific architecture operations and properly
enable for COMPILE_TEST without dirty Makefile arch flags. Both sysctl
and memctl has no other child nodes, and I think that's why I was told
to avoid child nodes at the end. I explained here [0] current sysctl
and memctl in the mt7621 device tree and my view of the need for this
two syscons:
[0]: https://lkml.org/lkml/2021/1/2/9
So to avoid to send again "a previous version" on this patch, please
guide me in the correct thing to do. Stephen, Rob, I will be really
happy with your help :)
Best regards,
Sergio Paracuellos
>
> > +
> > + clock-output-names:
> > + maxItems: 8
> > +
> > +required:
> > + - compatible
> > + - '#clock-cells'
> > + - ralink,sysctl
> > + - ralink,memctl
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt7621-clk.h>
> > +
> > + pll {
> > + compatible = "mediatek,mt7621-clk";
> > + #clock-cells = <1>;
> > + ralink,sysctl = <&sysc>;
> > + ralink,memctl = <&memc>;
> > + clock-output-names = "xtal", "cpu", "bus",
> > + "50m", "125m", "150m",
> > + "250m", "270m";
> > + };
> > --
> > 2.25.1
> >
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next prev parent reply other threads:[~2021-03-06 7:13 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-18 7:07 [PATCH v9 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621 Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation Sergio Paracuellos
2021-03-05 22:47 ` Rob Herring
2021-03-06 1:52 ` Chuanhong Guo
2021-03-06 7:12 ` Sergio Paracuellos [this message]
2021-03-06 9:54 ` Sergio Paracuellos
2021-03-07 6:27 ` Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 3/6] clk: ralink: add clock driver for mt7621 SoC Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 4/6] staging: mt7621-dts: make use of new 'mt7621-clk' Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' Sergio Paracuellos
2021-02-18 7:07 ` [PATCH v9 6/6] MAINTAINERS: add MT7621 CLOCK maintainer Sergio Paracuellos
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