* Re: [PATCH v1] staging: intel-dpa: gswip: Introduce Gigabit Ethernet Switch (GSWIP) device driver
[not found] <03832ecb6a34876ef26a24910816f22694c0e325.1572863013.git.jack.ping.chng@intel.com>
@ 2019-11-04 12:20 ` Greg KH
2019-11-04 16:42 ` Andrew Lunn
2019-11-04 19:19 ` David Miller
0 siblings, 2 replies; 4+ messages in thread
From: Greg KH @ 2019-11-04 12:20 UTC (permalink / raw)
To: Jack Ping CHNG
Cc: devel, cheol.yong.kim, andriy.shevchenko, netdev, linux-kernel,
davem, mallikarjunax.reddy
On Mon, Nov 04, 2019 at 07:22:20PM +0800, Jack Ping CHNG wrote:
> This driver enables the Intel's LGM SoC GSWIP block.
> GSWIP is a core module tailored for L2/L3/L4+ data plane and QoS functions.
> It allows CPUs and other accelerators connected to the SoC datapath
> to enqueue and dequeue packets through DMAs.
> Most configuration values are stored in tables such as
> Parsing and Classification Engine tables, Buffer Manager tables and
> Pseudo MAC tables.
Why is this being submitted to staging? What is wrong with the "real"
part of the kernel for this?
Your TODO file is really vague, and doesn't give anyone any real things
to work on with you, which is odd.
> Signed-off-by: Jack Ping CHNG <jack.ping.chng@intel.com>
> Signed-off-by: Amireddy Mallikarjuna reddy <mallikarjunax.reddy@linux.intel.com>
There is a group of people within Intel that you have to get code
reviewed by before you can send it to me. Please go by that process and
not try to circumvent it by dumping it on staging without that review.
It is there for good reasons.
greg k-h
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v1] staging: intel-dpa: gswip: Introduce Gigabit Ethernet Switch (GSWIP) device driver
2019-11-04 12:20 ` [PATCH v1] staging: intel-dpa: gswip: Introduce Gigabit Ethernet Switch (GSWIP) device driver Greg KH
@ 2019-11-04 16:42 ` Andrew Lunn
[not found] ` <4D649A99D5D6C446954219080E51FB468192606D@BGSMSX103.gar.corp.intel.com>
2019-11-04 19:19 ` David Miller
1 sibling, 1 reply; 4+ messages in thread
From: Andrew Lunn @ 2019-11-04 16:42 UTC (permalink / raw)
To: Greg KH
Cc: devel, cheol.yong.kim, Jack Ping CHNG, andriy.shevchenko, netdev,
linux-kernel, mallikarjunax.reddy, davem
On Mon, Nov 04, 2019 at 01:20:09PM +0100, Greg KH wrote:
> On Mon, Nov 04, 2019 at 07:22:20PM +0800, Jack Ping CHNG wrote:
> > This driver enables the Intel's LGM SoC GSWIP block.
> > GSWIP is a core module tailored for L2/L3/L4+ data plane and QoS functions.
> > It allows CPUs and other accelerators connected to the SoC datapath
> > to enqueue and dequeue packets through DMAs.
> > Most configuration values are stored in tables such as
> > Parsing and Classification Engine tables, Buffer Manager tables and
> > Pseudo MAC tables.
>
> Why is this being submitted to staging? What is wrong with the "real"
> part of the kernel for this?
Or even, what is wrong with the current driver?
drivers/net/dsa/lantiq_gswip.c?
Jack, your patch does not seem to of made it to any of the lists. So i
cannot comment on it contents. If this is a switch driver, please
ensure you Cc: the usual suspects for switch drivers.
Andrew
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v1] staging: intel-dpa: gswip: Introduce Gigabit Ethernet Switch (GSWIP) device driver
2019-11-04 12:20 ` [PATCH v1] staging: intel-dpa: gswip: Introduce Gigabit Ethernet Switch (GSWIP) device driver Greg KH
2019-11-04 16:42 ` Andrew Lunn
@ 2019-11-04 19:19 ` David Miller
1 sibling, 0 replies; 4+ messages in thread
From: David Miller @ 2019-11-04 19:19 UTC (permalink / raw)
To: gregkh
Cc: devel, cheol.yong.kim, jack.ping.chng, andriy.shevchenko, netdev,
linux-kernel, mallikarjunax.reddy
From: Greg KH <gregkh@linuxfoundation.org>
Date: Mon, 4 Nov 2019 13:20:09 +0100
> Why is this being submitted to staging? What is wrong with the "real"
> part of the kernel for this?
Agreed, this makes no sense at all.
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v1] staging: intel-dpa: gswip: Introduce Gigabit Ethernet Switch (GSWIP) device driver
[not found] ` <4D649A99D5D6C446954219080E51FB468192606D@BGSMSX103.gar.corp.intel.com>
@ 2019-11-07 9:47 ` Chng, Jack Ping
0 siblings, 0 replies; 4+ messages in thread
From: Chng, Jack Ping @ 2019-11-07 9:47 UTC (permalink / raw)
To: Greg KH, Andrew Lunn
Cc: Kim, Cheol Yong, devel, Chng, Jack Ping, Shevchenko, Andriy,
netdev, linux-kernel, mallikarjunax.reddy, davem
On Mon, Nov 04, 2019 at 01:20:09PM +0100, Greg KH wrote:
>> On Mon, Nov 04, 2019 at 07:22:20PM +0800, Jack Ping CHNG wrote:
>>> This driver enables the Intel's LGM SoC GSWIP block.
>>> GSWIP is a core module tailored for L2/L3/L4+ data plane and QoS functions.
>>> It allows CPUs and other accelerators connected to the SoC datapath
>>> to enqueue and dequeue packets through DMAs.
>>> Most configuration values are stored in tables such as Parsing and
>>> Classification Engine tables, Buffer Manager tables and Pseudo MAC
>>> tables.
>> Why is this being submitted to staging? What is wrong with the "real"
>> part of the kernel for this?
>>
>> Or even, what is wrong with the current driver?
>> drivers/net/dsa/lantiq_gswip.c?
GSWIP (a new HW IP) is part of Intel Datapath Architecture drivers
design for new Intel network/GW SoC (LGM).
Currently there are few other drivers (for different HW blocks in the
datapath) which are still under internal code review.
Once it is done we are planning to submit staging folder.
Since the development is ongoing, we thought it is best to submit GSWIP
first in drivers/staging/intel-dpa folder.
In the meantime, we will prepare a more detail TODO list for intel-dpa
folder and a README to introduce the dpa.
>> Jack, your patch does not seem to of made it to any of the lists. So i cannot comment on it contents. If this is a switch driver, please ensure you Cc: the usual suspects for switch drivers.
>>
>> Andrew
Sure, I will resubmit my patch.
Best regards,
Chng Jack Ping
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-11-04 12:20 ` [PATCH v1] staging: intel-dpa: gswip: Introduce Gigabit Ethernet Switch (GSWIP) device driver Greg KH
2019-11-04 16:42 ` Andrew Lunn
[not found] ` <4D649A99D5D6C446954219080E51FB468192606D@BGSMSX103.gar.corp.intel.com>
2019-11-07 9:47 ` Chng, Jack Ping
2019-11-04 19:19 ` David Miller
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