From: Weiwei Li <liweiwei@iscas.ac.cn> To: Guo Ren <guoren@kernel.org> Cc: "Wei Wu (吴伟)" <lazyparser@gmail.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "Anup Patel" <anup@brainfault.org>, "Wang Junqiang" <wangjunqiang@iscas.ac.cn>, bin.meng@windriver.com, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "Alistair Francis" <alistair.francis@wdc.com>, "Palmer Dabbelt" <palmer@dabbelt.com> Subject: Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension Date: Mon, 17 Jan 2022 16:28:50 +0800 [thread overview] Message-ID: <facc03c8-f2ba-9e5e-b571-4fbfbdff72f3@iscas.ac.cn> (raw) In-Reply-To: <CAJF2gTTh+L5PX2kAnAMQUeindidpW=tWRhAX_B0HwV4rFzsyBA@mail.gmail.com> 在 2022/1/17 下午3:18, Guo Ren 写道: > On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently >> - add PTE_PBMT bits check for inner PTE >> - add reserved bits check for all PTE >> >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> >> Tested-by: Heiko Stuebner <heiko@sntech.de> >> Reviewed-by: Anup Patel <anup@brainfault.org> >> --- >> target/riscv/cpu.c | 1 + >> target/riscv/cpu.h | 1 + >> target/riscv/cpu_bits.h | 3 +++ >> target/riscv/cpu_helper.c | 8 ++++++-- >> 4 files changed, 11 insertions(+), 2 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 45ac98e06b..4f82bd00a3 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = { >> >> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), >> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), >> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), >> >> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), >> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index c3d1845ca1..53f314c752 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -329,6 +329,7 @@ struct RISCVCPU { >> bool ext_icsr; >> bool ext_svinval; >> bool ext_svnapot; >> + bool ext_svpbmt; >> bool ext_zfh; >> bool ext_zfhmin; >> >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index bc23e3b523..ee294c1d0b 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -486,7 +486,10 @@ typedef enum { >> #define PTE_A 0x040 /* Accessed */ >> #define PTE_D 0x080 /* Dirty */ >> #define PTE_SOFT 0x300 /* Reserved for Software */ >> +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */ >> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */ >> #define PTE_N 0x8000000000000000 /* NAPOT translation */ >> +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */ >> >> /* Page table PPN shift amount */ >> #define PTE_PPN_SHIFT 10 >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> index 832a2dd79c..f90766e026 100644 >> --- a/target/riscv/cpu_helper.c >> +++ b/target/riscv/cpu_helper.c >> @@ -619,17 +619,21 @@ restart: >> return TRANSLATE_FAIL; >> } >> >> - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT; >> + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT; > This would break rv32. Please ref: > https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/ > Thanks for your comment . I'll merge this into our patchset. Regards, Weiwei Li >> RISCVCPU *cpu = env_archcpu(env); >> if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) { >> return TRANSLATE_FAIL; >> + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { >> + return TRANSLATE_FAIL; >> + } else if (pte & PTE_RSVD) { >> + return TRANSLATE_FAIL; >> } else if (!(pte & PTE_V)) { >> /* Invalid PTE */ >> return TRANSLATE_FAIL; >> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { >> /* Inner PTE, continue walking */ >> - if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) { >> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) { >> return TRANSLATE_FAIL; >> } >> base = ppn << PGSHIFT; >> -- >> 2.17.1 >> >> >
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn> To: Guo Ren <guoren@kernel.org> Cc: "Anup Patel" <anup@brainfault.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Alistair Francis" <alistair.francis@wdc.com>, bin.meng@windriver.com, "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "Wang Junqiang" <wangjunqiang@iscas.ac.cn>, "Wei Wu (吴伟)" <lazyparser@gmail.com> Subject: Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension Date: Mon, 17 Jan 2022 16:28:50 +0800 [thread overview] Message-ID: <facc03c8-f2ba-9e5e-b571-4fbfbdff72f3@iscas.ac.cn> (raw) In-Reply-To: <CAJF2gTTh+L5PX2kAnAMQUeindidpW=tWRhAX_B0HwV4rFzsyBA@mail.gmail.com> 在 2022/1/17 下午3:18, Guo Ren 写道: > On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently >> - add PTE_PBMT bits check for inner PTE >> - add reserved bits check for all PTE >> >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> >> Tested-by: Heiko Stuebner <heiko@sntech.de> >> Reviewed-by: Anup Patel <anup@brainfault.org> >> --- >> target/riscv/cpu.c | 1 + >> target/riscv/cpu.h | 1 + >> target/riscv/cpu_bits.h | 3 +++ >> target/riscv/cpu_helper.c | 8 ++++++-- >> 4 files changed, 11 insertions(+), 2 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 45ac98e06b..4f82bd00a3 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = { >> >> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), >> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), >> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), >> >> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), >> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index c3d1845ca1..53f314c752 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -329,6 +329,7 @@ struct RISCVCPU { >> bool ext_icsr; >> bool ext_svinval; >> bool ext_svnapot; >> + bool ext_svpbmt; >> bool ext_zfh; >> bool ext_zfhmin; >> >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index bc23e3b523..ee294c1d0b 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -486,7 +486,10 @@ typedef enum { >> #define PTE_A 0x040 /* Accessed */ >> #define PTE_D 0x080 /* Dirty */ >> #define PTE_SOFT 0x300 /* Reserved for Software */ >> +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */ >> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */ >> #define PTE_N 0x8000000000000000 /* NAPOT translation */ >> +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */ >> >> /* Page table PPN shift amount */ >> #define PTE_PPN_SHIFT 10 >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> index 832a2dd79c..f90766e026 100644 >> --- a/target/riscv/cpu_helper.c >> +++ b/target/riscv/cpu_helper.c >> @@ -619,17 +619,21 @@ restart: >> return TRANSLATE_FAIL; >> } >> >> - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT; >> + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT; > This would break rv32. Please ref: > https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/ > Thanks for your comment . I'll merge this into our patchset. Regards, Weiwei Li >> RISCVCPU *cpu = env_archcpu(env); >> if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) { >> return TRANSLATE_FAIL; >> + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { >> + return TRANSLATE_FAIL; >> + } else if (pte & PTE_RSVD) { >> + return TRANSLATE_FAIL; >> } else if (!(pte & PTE_V)) { >> /* Invalid PTE */ >> return TRANSLATE_FAIL; >> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { >> /* Inner PTE, continue walking */ >> - if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) { >> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) { >> return TRANSLATE_FAIL; >> } >> base = ppn << PGSHIFT; >> -- >> 2.17.1 >> >> >
next prev parent reply other threads:[~2022-01-17 8:32 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-16 2:59 [PATCH v4 0/4] support subsets of virtual memory extension Weiwei Li 2022-01-16 2:59 ` Weiwei Li 2022-01-16 2:59 ` [PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Weiwei Li 2022-01-16 2:59 ` Weiwei Li 2022-01-16 2:59 ` [PATCH v4 2/4] target/riscv: add support for svnapot extension Weiwei Li 2022-01-16 2:59 ` Weiwei Li 2022-01-16 4:29 ` Anup Patel 2022-01-16 4:29 ` Anup Patel 2022-01-16 2:59 ` [PATCH v4 3/4] target/riscv: add support for svinval extension Weiwei Li 2022-01-16 2:59 ` Weiwei Li 2022-01-16 2:59 ` [PATCH v4 4/4] target/riscv: add support for svpbmt extension Weiwei Li 2022-01-16 2:59 ` Weiwei Li 2022-01-17 7:18 ` Guo Ren 2022-01-17 7:18 ` Guo Ren 2022-01-17 8:28 ` Weiwei Li [this message] 2022-01-17 8:28 ` Weiwei Li
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