From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH v5 08/11] TAAv5 8
Date: Thu, 17 Oct 2019 17:14:07 -0700 [thread overview]
Message-ID: <20191018001407.GA28905@guptapadev.amr> (raw)
In-Reply-To: <alpine.DEB.2.21.1910161355340.2046@nanos.tec.linutronix.de>
On Wed, Oct 16, 2019 at 02:15:08PM +0200, speck for Thomas Gleixner wrote:
> On Wed, 16 Oct 2019, speck for Michal Hocko wrote:
> > Is tsx=auto going to lead to any different state than tsx=on? In other
> > words does auto mode make any sense at all?
>
> Is it only my vacation induced spark of mental sanity or is this whole TAA
> thing a complete trainwreck again?
>
> We're at version 5 and more than 3 month since the first RFC got posted and
> we are still debating which CPUs are affected and which migitations are
> going to be deployed depending on the CPU advertized misfeatures and the
> eventually surfacing microcode?
>
> Can we please stop this complete waste of time right now and start over
> with clarifying the situation? I.e. someone at Intel needs to sit down and
> write up a matrix:
>
> TAA-Affected | MDS_NO | VERW works | TSX_MSR | Resulting action
> -------------|--------|------------|---------|-----------------
> No | X | X | Y | ?
> No | X | X | N | None
> Yes | 0 | 0 | 0 | SNAFU
> ... | | | |
>
> You surely can fill in the rest on your own, right?
>
> And exactly that information wants to be in the admin documentation or in a
> separate Documentation/x86/taa.rst as well.
Below is the matrix for the impact of tsx=<on|off|auto> cmdline options
on state of TAA mitigation, VERW behavior and TSX feature for various
combinations of MSR_IA32_ARCH_CAPABILITIES bits.
1. tsx=auto
+----------+----------+----------------+---------------+--------------+-------------------+
| MSR_IA32_ARCH_CAPABILITIES bits | Result with cmdline tsx=auto |
+----------+----------+----------------+---------------+--------------+-------------------+
| TAA_NO | MDS_NO | TSX_CTRL_MSR | VERW clears | TSX state | TAA mitigation |
| | | | CPU buffers | after bootup | |
+==========+==========+================+===============+==============+===================+
| 0 | 0 | 0 | Yes | HW default | Same as MDS |
+----------+----------+----------------+---------------+--------------+-------------------+
| 0 | 0 | 1 | Invalid case | Invalid case | Invalid case |
+----------+----------+----------------+---------------+--------------+-------------------+
| 0 | 1 | 0 | No | HW default | Need ucode update |
+----------+----------+----------------+---------------+--------------+-------------------+
| 0 | 1 | 1 | Yes | TSX disabled | TSX disabled |
+----------+----------+----------------+---------------+--------------+-------------------+
| 1 | X | 1 | X | TSX enabled | None needed |
+----------+----------+----------------+---------------+--------------+-------------------+
2. tsx=on
+----------+----------+----------------+---------------+--------------+-------------------+
| MSR_IA32_ARCH_CAPABILITIES bits | Result with cmdline tsx=on |
+----------+----------+----------------+---------------+--------------+-------------------+
| TAA_NO | MDS_NO | TSX_CTRL_MSR | VERW clears | TSX state | TAA mitigation |
| | | | CPU buffers | after bootup | |
+==========+==========+================+===============+==============+===================+
| 0 | 0 | 0 | Yes | HW default | Same as MDS |
+----------+----------+----------------+---------------+--------------+-------------------+
| 0 | 0 | 1 | Invalid case | Invalid case | Invalid case |
+----------+----------+----------------+---------------+--------------+-------------------+
| 0 | 1 | 0 | No | HW default | Need ucode update |
+----------+----------+----------------+---------------+--------------+-------------------+
| 0 | 1 | 1 | Yes | TSX enabled | Same as MDS |
+----------+----------+----------------+---------------+--------------+-------------------+
| 1 | X | 1 | X | TSX enabled | None needed |
+----------+----------+----------------+---------------+--------------+-------------------+
3. tsx=off
+----------+----------+----------------+---------------+--------------+-------------------+
| MSR_IA32_ARCH_CAPABILITIES bits | Result with cmdline tsx=off |
+----------+----------+----------------+---------------+--------------+-------------------+
| TAA_NO | MDS_NO | TSX_CTRL_MSR | VERW clears | TSX state | TAA mitigation |
| | | | CPU buffers | after bootup | |
+==========+==========+================+===============+==============+===================+
| 0 | 0 | 0 | Yes | HW default | Same as MDS |
+----------+----------+----------------+---------------+--------------+-------------------+
| 0 | 0 | 1 | Invalid case | Invalid case | Invalid case |
+----------+----------+----------------+---------------+--------------+-------------------+
| 0 | 1 | 0 | No | HW default | Need ucode update |
+----------+----------+----------------+---------------+--------------+-------------------+
| 0 | 1 | 1 | Yes | TSX disabled | TSX disabled |
+----------+----------+----------------+---------------+--------------+-------------------+
| 1 | X | 1 | X | TSX disabled | None needed |
+----------+----------+----------------+---------------+--------------+-------------------+
Let me know if there are any questions.
Thanks,
Pawan
next prev parent reply other threads:[~2019-10-18 0:20 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-05 6:17 [MODERATED] [PATCH v5 00/11] TAAv5 0 Pawan Gupta
2019-10-05 6:26 ` [MODERATED] [PATCH v5 01/11] TAAv5 1 Pawan Gupta
2019-10-05 6:27 ` [MODERATED] [PATCH v5 02/11] TAAv5 2 Pawan Gupta
2019-10-05 6:28 ` [MODERATED] [PATCH v5 03/11] TAAv5 3 Pawan Gupta
2019-10-05 6:29 ` [MODERATED] [PATCH v5 04/11] TAAv5 4 Pawan Gupta
2019-10-05 6:30 ` [MODERATED] [PATCH v5 05/11] TAAv5 5 Pawan Gupta
2019-10-05 6:31 ` [MODERATED] [PATCH v5 06/11] TAAv5 6 Pawan Gupta
2019-10-05 6:32 ` [MODERATED] [PATCH v5 07/11] TAAv5 7 Pawan Gupta
2019-10-05 6:33 ` [MODERATED] [PATCH v5 08/11] TAAv5 8 Pawan Gupta
2019-10-05 6:34 ` [MODERATED] [PATCH v5 09/11] TAAv5 9 Pawan Gupta
2019-10-05 6:35 ` [MODERATED] [PATCH v5 10/11] TAAv5 10 Pawan Gupta
2019-10-05 6:36 ` [MODERATED] [PATCH v5 11/11] TAAv5 11 Pawan Gupta
2019-10-05 10:54 ` [MODERATED] Re: [PATCH v5 02/11] TAAv5 2 Borislav Petkov
2019-10-07 17:48 ` Pawan Gupta
[not found] ` <5d98396a.1c69fb81.6c7a8.23b1SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:43 ` [MODERATED] Re: [PATCH v5 03/11] TAAv5 3 Andy Lutomirski
2019-10-07 17:50 ` Pawan Gupta
[not found] ` <5d9839a4.1c69fb81.238e9.8312SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:45 ` [MODERATED] Re: [PATCH v5 04/11] TAAv5 4 Andy Lutomirski
[not found] ` <5d983ad2.1c69fb81.63edd.6575SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:49 ` [MODERATED] Re: [PATCH v5 09/11] TAAv5 9 Andy Lutomirski
2019-10-07 18:35 ` Pawan Gupta
[not found] ` <5d9838f1.1c69fb81.f1bab.d886SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:49 ` [MODERATED] Re: [PATCH v5 01/11] TAAv5 1 Andy Lutomirski
2019-10-06 17:40 ` Andrew Cooper
[not found] ` <5d983ad2.1c69fb81.e6640.8f51SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-06 17:06 ` [MODERATED] Re: [PATCH v5 09/11] TAAv5 9 Greg KH
2019-10-08 6:01 ` Pawan Gupta
2019-10-10 21:31 ` Pawan Gupta
2019-10-11 8:45 ` Greg KH
2019-10-21 8:00 ` Thomas Gleixner
2019-10-08 2:46 ` [MODERATED] Re: [PATCH v5 05/11] TAAv5 5 Josh Poimboeuf
2019-10-09 1:45 ` Pawan Gupta
2019-10-08 2:57 ` [MODERATED] Re: [PATCH v5 09/11] TAAv5 9 Josh Poimboeuf
2019-10-08 6:10 ` Pawan Gupta
2019-10-08 10:49 ` Jiri Kosina
2019-10-09 13:12 ` [MODERATED] Re: ***UNCHECKED*** [PATCH v5 08/11] TAAv5 8 Michal Hocko
2019-10-14 19:41 ` Thomas Gleixner
2019-10-14 19:51 ` [MODERATED] " Jiri Kosina
2019-10-14 21:04 ` [MODERATED] " Borislav Petkov
2019-10-14 21:31 ` Jiri Kosina
2019-10-15 8:01 ` Thomas Gleixner
2019-10-15 10:34 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-15 13:06 ` Josh Poimboeuf
2019-10-15 13:10 ` Jiri Kosina
2019-10-15 15:26 ` Josh Poimboeuf
2019-10-15 15:32 ` Jiri Kosina
2019-10-15 19:34 ` Tyler Hicks
2019-10-15 20:00 ` Josh Poimboeuf
2019-10-15 20:15 ` Jiri Kosina
2019-10-15 20:35 ` Jiri Kosina
2019-10-15 20:54 ` Josh Poimboeuf
2019-10-15 20:56 ` [MODERATED] " Pawan Gupta
2019-10-15 21:14 ` Jiri Kosina
2019-10-15 23:12 ` Josh Poimboeuf
2019-10-15 23:13 ` [MODERATED] [AUTOREPLY] [MODERATED] [AUTOREPLY] Automatic reply: " James, Hengameh M
2019-10-16 4:52 ` [MODERATED] " Jiri Kosina
2019-10-16 5:05 ` Jiri Kosina
2019-10-21 21:15 ` Luck, Tony
2019-10-16 7:14 ` Josh Poimboeuf
2019-10-16 7:20 ` Jiri Kosina
2019-10-18 1:17 ` Ben Hutchings
2019-10-18 4:04 ` Pawan Gupta
2019-10-15 17:47 ` Borislav Petkov
2019-10-16 7:26 ` [MODERATED] Re: ***UNCHECKED*** " Jiri Kosina
2019-10-16 7:54 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-16 9:23 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-16 12:15 ` Thomas Gleixner
2019-10-16 18:34 ` [MODERATED] " Pawan Gupta
2019-10-18 0:14 ` Pawan Gupta [this message]
2019-10-21 8:09 ` Thomas Gleixner
2019-10-21 12:54 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-21 20:01 ` [MODERATED] " Pawan Gupta
2019-10-21 20:33 ` Josh Poimboeuf
2019-10-21 20:34 ` Josh Poimboeuf
2019-10-21 20:33 ` Pawan Gupta
2019-10-21 23:01 ` Andrew Cooper
2019-10-21 23:37 ` Luck, Tony
2019-10-21 23:39 ` Andrew Cooper
2019-10-14 21:05 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191018001407.GA28905@guptapadev.amr \
--to=pawan.kumar.gupta@linux.intel.com \
--cc=speck@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).