From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] [PATCH v5 01/11] TAAv5 1
Date: Fri, 4 Oct 2019 23:26:30 -0700 [thread overview]
Message-ID: <=?utf-8?q?=3C731e305d73d05e0b0458340d5832331f0873a287=2E157025?= =?utf-8?q?5065=2Egit=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Ecom=3E?=> (raw)
In-Reply-To: <cover.1570255065.git.pawan.kumar.gupta@linux.intel.com>
Transactional Synchronization Extensions (TSX) may be used on certain
processors as part of a speculative side channel attack. A microcode
update for existing processors that are vulnerable to this attack will
add a new MSR, IA32_TSX_CTRL to allow the system administrator the
option to disable TSX as one of the possible mitigations. [Note that
future processors that are not vulnerable will also support the
IA32_TSX_CTRL MSR]. Add defines for the new IA32_TSX_CTRL MSR and its
bits.
TSX has two sub-features:
1. Restricted Transactional Memory (RTM) is an explicitly-used feature
where new instructions begin and end TSX transactions.
2. Hardware Lock Elision (HLE) is implicitly used when certain kinds of
"old" style locks are used by software.
Bit 7 of the IA32_ARCH_CAPABILITIES indicates the presence of the
IA32_TSX_CTRL MSR.
There are two control bits in IA32_TSX_CTRL MSR:
Bit 0: When set it disables the Restricted Transactional Memory (RTM)
sub-feature of TSX (will force all transactions to abort on the
XBEGIN instruction).
Bit 1: When set it disables the enumeration of the RTM feature (i.e.
it will make CPUID(EAX=7).EBX{bit11} read as 0).
The other TSX sub-feature, Hardware Lock Elision (HLE), is unconditionally
disabled but still enumerated as present by CPUID(EAX=7).EBX{bit4}.
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Reviewed-by: Mark Gross <mgross@linux.intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
---
arch/x86/include/asm/msr-index.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 271d837d69a8..45b6705d9f71 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -93,6 +93,7 @@
* Microarchitectural Data
* Sampling (MDS) vulnerabilities.
*/
+#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */
#define MSR_IA32_FLUSH_CMD 0x0000010b
#define L1D_FLUSH BIT(0) /*
@@ -103,6 +104,10 @@
#define MSR_IA32_BBL_CR_CTL 0x00000119
#define MSR_IA32_BBL_CR_CTL3 0x0000011e
+#define MSR_IA32_TSX_CTRL 0x00000122
+#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
+#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
+
#define MSR_IA32_SYSENTER_CS 0x00000174
#define MSR_IA32_SYSENTER_ESP 0x00000175
#define MSR_IA32_SYSENTER_EIP 0x00000176
--
2.20.1
next prev parent reply other threads:[~2019-10-05 6:32 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-05 6:17 [MODERATED] [PATCH v5 00/11] TAAv5 0 Pawan Gupta
2019-10-05 6:26 ` Pawan Gupta [this message]
2019-10-05 6:27 ` [MODERATED] [PATCH v5 02/11] TAAv5 2 Pawan Gupta
2019-10-05 6:28 ` [MODERATED] [PATCH v5 03/11] TAAv5 3 Pawan Gupta
2019-10-05 6:29 ` [MODERATED] [PATCH v5 04/11] TAAv5 4 Pawan Gupta
2019-10-05 6:30 ` [MODERATED] [PATCH v5 05/11] TAAv5 5 Pawan Gupta
2019-10-05 6:31 ` [MODERATED] [PATCH v5 06/11] TAAv5 6 Pawan Gupta
2019-10-05 6:32 ` [MODERATED] [PATCH v5 07/11] TAAv5 7 Pawan Gupta
2019-10-05 6:33 ` [MODERATED] [PATCH v5 08/11] TAAv5 8 Pawan Gupta
2019-10-05 6:34 ` [MODERATED] [PATCH v5 09/11] TAAv5 9 Pawan Gupta
2019-10-05 6:35 ` [MODERATED] [PATCH v5 10/11] TAAv5 10 Pawan Gupta
2019-10-05 6:36 ` [MODERATED] [PATCH v5 11/11] TAAv5 11 Pawan Gupta
2019-10-05 10:54 ` [MODERATED] Re: [PATCH v5 02/11] TAAv5 2 Borislav Petkov
2019-10-07 17:48 ` Pawan Gupta
[not found] ` <5d98396a.1c69fb81.6c7a8.23b1SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:43 ` [MODERATED] Re: [PATCH v5 03/11] TAAv5 3 Andy Lutomirski
2019-10-07 17:50 ` Pawan Gupta
[not found] ` <5d9839a4.1c69fb81.238e9.8312SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:45 ` [MODERATED] Re: [PATCH v5 04/11] TAAv5 4 Andy Lutomirski
[not found] ` <5d983ad2.1c69fb81.63edd.6575SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:49 ` [MODERATED] Re: [PATCH v5 09/11] TAAv5 9 Andy Lutomirski
2019-10-07 18:35 ` Pawan Gupta
[not found] ` <5d9838f1.1c69fb81.f1bab.d886SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:49 ` [MODERATED] Re: [PATCH v5 01/11] TAAv5 1 Andy Lutomirski
2019-10-06 17:40 ` Andrew Cooper
[not found] ` <5d983ad2.1c69fb81.e6640.8f51SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-06 17:06 ` [MODERATED] Re: [PATCH v5 09/11] TAAv5 9 Greg KH
2019-10-08 6:01 ` Pawan Gupta
2019-10-10 21:31 ` Pawan Gupta
2019-10-11 8:45 ` Greg KH
2019-10-21 8:00 ` Thomas Gleixner
2019-10-08 2:46 ` [MODERATED] Re: [PATCH v5 05/11] TAAv5 5 Josh Poimboeuf
2019-10-09 1:45 ` Pawan Gupta
2019-10-08 2:57 ` [MODERATED] Re: [PATCH v5 09/11] TAAv5 9 Josh Poimboeuf
2019-10-08 6:10 ` Pawan Gupta
2019-10-08 10:49 ` Jiri Kosina
2019-10-09 13:12 ` [MODERATED] Re: ***UNCHECKED*** [PATCH v5 08/11] TAAv5 8 Michal Hocko
2019-10-14 19:41 ` Thomas Gleixner
2019-10-14 19:51 ` [MODERATED] " Jiri Kosina
2019-10-14 21:04 ` [MODERATED] " Borislav Petkov
2019-10-14 21:31 ` Jiri Kosina
2019-10-15 8:01 ` Thomas Gleixner
2019-10-15 10:34 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-15 13:06 ` Josh Poimboeuf
2019-10-15 13:10 ` Jiri Kosina
2019-10-15 15:26 ` Josh Poimboeuf
2019-10-15 15:32 ` Jiri Kosina
2019-10-15 19:34 ` Tyler Hicks
2019-10-15 20:00 ` Josh Poimboeuf
2019-10-15 20:15 ` Jiri Kosina
2019-10-15 20:35 ` Jiri Kosina
2019-10-15 20:54 ` Josh Poimboeuf
2019-10-15 20:56 ` [MODERATED] " Pawan Gupta
2019-10-15 21:14 ` Jiri Kosina
2019-10-15 23:12 ` Josh Poimboeuf
2019-10-15 23:13 ` [MODERATED] [AUTOREPLY] [MODERATED] [AUTOREPLY] Automatic reply: " James, Hengameh M
2019-10-16 4:52 ` [MODERATED] " Jiri Kosina
2019-10-16 5:05 ` Jiri Kosina
2019-10-21 21:15 ` Luck, Tony
2019-10-16 7:14 ` Josh Poimboeuf
2019-10-16 7:20 ` Jiri Kosina
2019-10-18 1:17 ` Ben Hutchings
2019-10-18 4:04 ` Pawan Gupta
2019-10-15 17:47 ` Borislav Petkov
2019-10-16 7:26 ` [MODERATED] Re: ***UNCHECKED*** " Jiri Kosina
2019-10-16 7:54 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-16 9:23 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-16 12:15 ` Thomas Gleixner
2019-10-16 18:34 ` [MODERATED] " Pawan Gupta
2019-10-18 0:14 ` Pawan Gupta
2019-10-21 8:09 ` Thomas Gleixner
2019-10-21 12:54 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-21 20:01 ` [MODERATED] " Pawan Gupta
2019-10-21 20:33 ` Josh Poimboeuf
2019-10-21 20:34 ` Josh Poimboeuf
2019-10-21 20:33 ` Pawan Gupta
2019-10-21 23:01 ` Andrew Cooper
2019-10-21 23:37 ` Luck, Tony
2019-10-21 23:39 ` Andrew Cooper
2019-10-14 21:05 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
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