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From: Paolo Bonzini <pbonzini@redhat.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: ***UNCHECKED*** Re: [PATCH v7 3/5] NX 3
Date: Fri, 25 Oct 2019 11:08:25 +0200	[thread overview]
Message-ID: <201e8590-30ed-ab29-6fc2-bbeab1fb5592@redhat.com> (raw)
In-Reply-To: <20191025090331.GD7069@suse.de>

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On 25/10/19 11:03, speck for Joerg Roedel wrote:
> On Fri, Oct 25, 2019 at 10:48:04AM +0200, speck for Paolo Bonzini wrote:
>> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
>> index e7970a2e8eae..1f923dee99e5 100644
>> --- a/arch/x86/kvm/vmx/vmx.c
>> +++ b/arch/x86/kvm/vmx/vmx.c
>> @@ -992,6 +992,9 @@ static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
>>  		ignore_bits &= ~(u64)EFER_SCE;
>>  #endif
>>  
>> +	guest_efer &= ~ignore_bits;
>> +	guest_efer |= host_efer & ignore_bits;
>> +
>>  	/*
>>  	 * On EPT, we can't emulate NX, so we must switch EFER atomically.
>>  	 * On CPUs that support "load IA32_EFER", always switch EFER
>> @@ -1010,9 +1013,6 @@ static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
>>  	} else {
>>  		clear_atomic_switch_msr(vmx, MSR_EFER);
>>  
>> -		guest_efer &= ~ignore_bits;
>> -		guest_efer |= host_efer & ignore_bits;
>> -
>>  		vmx->guest_msrs[efer_offset].data = guest_efer;
>>  		vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
>>  
>>
>>
> 
> This works on my machine with ept=0 but breaks with ept=1:
> 
> 	KVM: entry failed, hardware error 0x80000021

Even simpler:

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index e7970a2e8eae..8979d5e7b6f5 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -969,17 +969,9 @@ static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 	u64 guest_efer = vmx->vcpu.arch.efer;
 	u64 ignore_bits = 0;
 
-	if (!enable_ept) {
-		/*
-		 * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
-		 * host CPUID is more efficient than testing guest CPUID
-		 * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
-		 */
-		if (boot_cpu_has(X86_FEATURE_SMEP))
-			guest_efer |= EFER_NX;
-		else if (!(guest_efer & EFER_NX))
-			ignore_bits |= EFER_NX;
-	}
+	/* Shadow paging assumes the NX bit to be available.  */
+	if (!enable_ept)
+		guest_efer |= EFER_NX;
 
 	/*
 	 * LMA and LME handled by hardware; SCE meaningless outside long mode.



This also shows why I couldn't reproduce it, my machine has SMEP and thus
always runs the guest with EFER.NXE=1.

Paolo


  reply	other threads:[~2019-10-25  9:08 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-24 16:34 [MODERATED] [PATCH v7 0/5] NX 0 Paolo Bonzini
2019-10-24 16:34 ` [MODERATED] [PATCH v7 1/5] NX 1 Paolo Bonzini
2019-10-30 18:38   ` [MODERATED] " Josh Poimboeuf
2019-10-31 11:05     ` Paolo Bonzini
2019-10-24 16:34 ` [MODERATED] [PATCH v7 2/5] NX 2 Paolo Bonzini
2019-10-24 16:34 ` [MODERATED] [PATCH v7 3/5] NX 3 Paolo Bonzini
2019-10-25  8:37   ` [MODERATED] Re: ***UNCHECKED*** " Joerg Roedel
2019-10-25  8:48     ` Paolo Bonzini
2019-10-25  9:03       ` [MODERATED] Re: ***UNCHECKED*** " Joerg Roedel
2019-10-25  9:08         ` Paolo Bonzini [this message]
2019-10-25  9:45           ` [MODERATED] Re: ***UNCHECKED*** " Joerg Roedel
2019-10-25 10:39             ` Paolo Bonzini
2019-10-29 20:33               ` mark gross
2019-10-31 11:02                 ` Paolo Bonzini
2019-10-24 16:34 ` [MODERATED] [PATCH v7 4/5] NX 4 Paolo Bonzini
2019-10-24 16:34 ` [MODERATED] [PATCH v7 5/5] NX 5 Paolo Bonzini
2019-10-24 18:27 ` [MODERATED] Re: [PATCH v7 0/5] NX 0 Ben Hutchings
2019-10-24 18:56   ` Paolo Bonzini

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