From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable
Date: Wed, 31 Oct 2012 22:52:30 +0100 [thread overview]
Message-ID: <1351720351-2688-5-git-send-email-daniel.vetter@ffwll.ch> (raw)
In-Reply-To: <1351720351-2688-1-git-send-email-daniel.vetter@ffwll.ch>
Found in Bspec vol4h South Display Engine Registers [CPT, PPT],
section "5.3.1 TRANS_CHICKEN_1—Transcoder Chicken Bits 1"
v2: Make it compile.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f1fe3a0..14851ab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3803,6 +3803,10 @@
#define TRANS_6BPC (2<<5)
#define TRANS_12BPC (3<<5)
+#define _TRANSA_CHICKEN1 0xf0060
+#define _TRANSB_CHICKEN1 0xf1060
+#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
+#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
#define _TRANSA_CHICKEN2 0xf0064
#define _TRANSB_CHICKEN2 0xf1064
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3469fbd..a0e8f51 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3786,6 +3786,7 @@ static void ibx_init_clock_gating(struct drm_device *dev)
static void cpt_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe;
/*
* On Ibex Peak and Cougar Point, we need to disable clock
@@ -3795,6 +3796,11 @@ static void cpt_init_clock_gating(struct drm_device *dev)
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
DPLS_EDP_PPS_FIX_DIS);
+ /* WADP0ClockGatingDisable */
+ for_each_pipe(pipe) {
+ I915_WRITE(TRANS_CHICKEN1(pipe),
+ TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
+ }
}
void intel_init_clock_gating(struct drm_device *dev)
--
1.7.11.4
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next prev parent reply other threads:[~2012-10-31 21:52 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-31 21:52 [PATCH 0/5] ivb fdi b/c fixes Daniel Vetter
2012-10-31 21:52 ` [PATCH 1/5] drm/i915: check whether the pch is the soulmate of the cpu Daniel Vetter
2012-11-01 15:58 ` Paulo Zanoni
2012-10-31 21:52 ` [PATCH 2/5] drm/i915: drop unnecessary check from fdi_link_train code Daniel Vetter
2012-10-31 21:52 ` [PATCH 3/5] drm/i915: CPT/PPT pch transcoder workaround Daniel Vetter
2012-11-01 8:15 ` [PATCH] drm/i915: CPT/PPT pch dp " Daniel Vetter
2012-11-01 14:37 ` Jesse Barnes
2012-11-01 15:33 ` Daniel Vetter
2012-11-01 15:35 ` Jesse Barnes
2012-11-01 16:12 ` Paulo Zanoni
2012-10-31 21:52 ` Daniel Vetter [this message]
2012-11-01 16:18 ` [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable Paulo Zanoni
2012-10-31 21:52 ` [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection Daniel Vetter
2012-11-01 16:35 ` Paulo Zanoni
2012-11-01 22:03 ` Daniel Vetter
-- strict thread matches above, loose matches on Subject: below --
2012-10-29 22:23 [PATCH 1/5] drm/i915: check whether the pch is the soulmate of the cpu Daniel Vetter
2012-10-29 22:23 ` [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable Daniel Vetter
2012-10-31 17:46 ` Paulo Zanoni
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