* [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw
@ 2013-01-30 14:59 Daniel Vetter
2013-01-30 14:59 ` [PATCH 2/2] drm/i915: kill cargo-culted locking from power well code Daniel Vetter
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Daniel Vetter @ 2013-01-30 14:59 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Sedat Dilek, Daniel Vetter, Paulo Zanoni
Dumps annoying noise into the dmesg:
[drm:intel_set_power_well] *ERROR* Timeout enabling power well
Reported-by: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 64d65f5..703219c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4053,6 +4053,9 @@ void intel_set_power_well(struct drm_device *dev, bool enable)
bool is_enabled, enable_requested;
uint32_t tmp;
+ if (!IS_HASWELL(dev))
+ return;
+
tmp = I915_READ(HSW_PWR_WELL_DRIVER);
is_enabled = tmp & HSW_PWR_WELL_STATE;
enable_requested = tmp & HSW_PWR_WELL_ENABLE;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915: kill cargo-culted locking from power well code
2013-01-30 14:59 [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw Daniel Vetter
@ 2013-01-30 14:59 ` Daniel Vetter
2013-01-30 17:40 ` Rodrigo Vivi
2013-01-30 15:55 ` [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw Sedat Dilek
2013-01-30 18:57 ` Paulo Zanoni
2 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2013-01-30 14:59 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter, Paulo Zanoni
We may not concurrently change the power wells code. Which
is already guaranteed since modesets aren't concurrent. That
leaves races against setup/teardown/suspend/resume, and for
those we already (try) rather hard not to hit concurrent
modesets.
No debug WARN_ON added since that would require us to grab the
modeset locks in init/suspend code. Which is again just cargo
culting since just grabbing the locks in those paths isn't good
enough, we need the right order of operations, too.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 703219c..f024e7d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4091,8 +4091,6 @@ void intel_init_power_well(struct drm_device *dev)
if (!IS_HASWELL(dev))
return;
- mutex_lock(&dev->struct_mutex);
-
/* For now, we need the power well to be always enabled. */
intel_set_power_well(dev, true);
@@ -4100,8 +4098,6 @@ void intel_init_power_well(struct drm_device *dev)
* the driver is in charge now. */
if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
I915_WRITE(HSW_PWR_WELL_BIOS, 0);
-
- mutex_unlock(&dev->struct_mutex);
}
/* Set up chip specific power management-related functions */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw
2013-01-30 14:59 [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw Daniel Vetter
2013-01-30 14:59 ` [PATCH 2/2] drm/i915: kill cargo-culted locking from power well code Daniel Vetter
@ 2013-01-30 15:55 ` Sedat Dilek
2013-01-30 18:57 ` Paulo Zanoni
2 siblings, 0 replies; 6+ messages in thread
From: Sedat Dilek @ 2013-01-30 15:55 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development, Paulo Zanoni
On Wed, Jan 30, 2013 at 3:59 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Dumps annoying noise into the dmesg:
>
> [drm:intel_set_power_well] *ERROR* Timeout enabling power well
>
> Reported-by: Sedat Dilek <sedat.dilek@gmail.com>
> Cc: Sedat Dilek <sedat.dilek@gmail.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: Sedat Dilek <sedat.dilek@gmail.com>
After S/R:
$ dmesg | egrep -i 'drm|i915|suspend|resume'
[ 10.887952] [drm] Initialized drm 1.1.0 20060810
[ 11.974280] [drm] Memory usable by graphics device = 2048M
[ 11.974290] i915 0000:00:02.0: setting latency timer to 64
[ 12.020550] i915 0000:00:02.0: irq 49 for MSI/MSI-X
[ 12.020563] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[ 12.020565] [drm] Driver supports precise vblank timestamp query.
[ 12.049337] fbcon: inteldrmfb (fb0) is primary device
[ 13.059191] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
[ 13.059192] i915 0000:00:02.0: registered panic notifier
[ 13.098925] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
[ 13.812483] [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off
[ 231.678520] Suspending console(s) (use no_console_suspend to debug)
[ 232.281962] PM: suspend of devices complete after 603.751 msecs
[ 232.282107] PM: late suspend of devices complete after 0.144 msecs
[ 232.377845] PM: noirq suspend of devices complete after 95.801 msecs
[ 232.719152] ACPI: Low-level resume complete
[ 232.956049] PM: noirq resume of devices complete after 143.982 msecs
[ 232.956224] PM: early resume of devices complete after 0.110 msecs
[ 232.956258] i915 0000:00:02.0: setting latency timer to 64
[ 234.634962] [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off
[ 235.398226] PM: resume of devices complete after 2443.721 msecs
- Sedat -
> ---
> drivers/gpu/drm/i915/intel_pm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 64d65f5..703219c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4053,6 +4053,9 @@ void intel_set_power_well(struct drm_device *dev, bool enable)
> bool is_enabled, enable_requested;
> uint32_t tmp;
>
> + if (!IS_HASWELL(dev))
> + return;
> +
> tmp = I915_READ(HSW_PWR_WELL_DRIVER);
> is_enabled = tmp & HSW_PWR_WELL_STATE;
> enable_requested = tmp & HSW_PWR_WELL_ENABLE;
> --
> 1.7.10.4
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: kill cargo-culted locking from power well code
2013-01-30 14:59 ` [PATCH 2/2] drm/i915: kill cargo-culted locking from power well code Daniel Vetter
@ 2013-01-30 17:40 ` Rodrigo Vivi
0 siblings, 0 replies; 6+ messages in thread
From: Rodrigo Vivi @ 2013-01-30 17:40 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development, Paulo Zanoni
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
On Wed, Jan 30, 2013 at 12:59 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> We may not concurrently change the power wells code. Which
> is already guaranteed since modesets aren't concurrent. That
> leaves races against setup/teardown/suspend/resume, and for
> those we already (try) rather hard not to hit concurrent
> modesets.
>
> No debug WARN_ON added since that would require us to grab the
> modeset locks in init/suspend code. Which is again just cargo
> culting since just grabbing the locks in those paths isn't good
> enough, we need the right order of operations, too.
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 703219c..f024e7d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4091,8 +4091,6 @@ void intel_init_power_well(struct drm_device *dev)
> if (!IS_HASWELL(dev))
> return;
>
> - mutex_lock(&dev->struct_mutex);
> -
> /* For now, we need the power well to be always enabled. */
> intel_set_power_well(dev, true);
>
> @@ -4100,8 +4098,6 @@ void intel_init_power_well(struct drm_device *dev)
> * the driver is in charge now. */
> if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
> I915_WRITE(HSW_PWR_WELL_BIOS, 0);
> -
> - mutex_unlock(&dev->struct_mutex);
> }
>
> /* Set up chip specific power management-related functions */
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw
2013-01-30 14:59 [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw Daniel Vetter
2013-01-30 14:59 ` [PATCH 2/2] drm/i915: kill cargo-culted locking from power well code Daniel Vetter
2013-01-30 15:55 ` [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw Sedat Dilek
@ 2013-01-30 18:57 ` Paulo Zanoni
2013-01-30 19:04 ` Daniel Vetter
2 siblings, 1 reply; 6+ messages in thread
From: Paulo Zanoni @ 2013-01-30 18:57 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Sedat Dilek, Intel Graphics Development, Paulo Zanoni
Hi
2013/1/30 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Dumps annoying noise into the dmesg:
>
> [drm:intel_set_power_well] *ERROR* Timeout enabling power well
>
> Reported-by: Sedat Dilek <sedat.dilek@gmail.com>
> Cc: Sedat Dilek <sedat.dilek@gmail.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 64d65f5..703219c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4053,6 +4053,9 @@ void intel_set_power_well(struct drm_device *dev, bool enable)
> bool is_enabled, enable_requested;
> uint32_t tmp;
>
> + if (!IS_HASWELL(dev))
> + return;
> +
> tmp = I915_READ(HSW_PWR_WELL_DRIVER);
> is_enabled = tmp & HSW_PWR_WELL_STATE;
> enable_requested = tmp & HSW_PWR_WELL_ENABLE;
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw
2013-01-30 18:57 ` Paulo Zanoni
@ 2013-01-30 19:04 ` Daniel Vetter
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2013-01-30 19:04 UTC (permalink / raw)
To: Paulo Zanoni
Cc: Sedat Dilek, Daniel Vetter, Intel Graphics Development, Paulo Zanoni
On Wed, Jan 30, 2013 at 04:57:45PM -0200, Paulo Zanoni wrote:
> Hi
>
> 2013/1/30 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > Dumps annoying noise into the dmesg:
> >
> > [drm:intel_set_power_well] *ERROR* Timeout enabling power well
> >
> > Reported-by: Sedat Dilek <sedat.dilek@gmail.com>
> > Cc: Sedat Dilek <sedat.dilek@gmail.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Both patches merged to dinq.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-01-30 19:02 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-01-30 14:59 [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw Daniel Vetter
2013-01-30 14:59 ` [PATCH 2/2] drm/i915: kill cargo-culted locking from power well code Daniel Vetter
2013-01-30 17:40 ` Rodrigo Vivi
2013-01-30 15:55 ` [PATCH 1/2] drm/i915: don't run hsw power well code on !hsw Sedat Dilek
2013-01-30 18:57 ` Paulo Zanoni
2013-01-30 19:04 ` Daniel Vetter
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).