[Intel-gfx] [PATCH rebased 1/3] drm/i915/dc3co: Do the full calculation of DC3CO exit only once

[Intel-gfx] [PATCH rebased 1/3] drm/i915/dc3co: Do the full calculation of DC3CO exit only once

[José Roberto de Souza]

This will calculaet the DC3CO exit delay only once per full modeset.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1d2fd1a8925a..e64e0c4c80dc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -802,7 +802,9 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 	dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 	dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
-	dev_priv->psr.dc3co_exit_delay = intel_get_frame_time_us(crtc_state);
+	/* DC5/DC6 required idle frames = 6 */
+	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
+	dev_priv->psr.dc3co_exit_delay = val;
 	dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
 
 	/*
@@ -1277,8 +1279,6 @@ static void
 tgl_dc3co_flush(struct drm_i915_private *dev_priv,
 		unsigned int frontbuffer_bits, enum fb_op_origin origin)
 {
-	u32 delay;
-
 	mutex_lock(&dev_priv->psr.lock);
 
 	if (!dev_priv->psr.dc3co_enabled)
@@ -1296,10 +1296,8 @@ tgl_dc3co_flush(struct drm_i915_private *dev_priv,
 		goto unlock;
 
 	tgl_psr2_enable_dc3co(dev_priv);
-	/* DC5/DC6 required idle frames = 6 */
-	delay = 6 * dev_priv->psr.dc3co_exit_delay;
 	mod_delayed_work(system_wq, &dev_priv->psr.idle_work,
-			 usecs_to_jiffies(delay));
+			 dev_priv->psr.dc3co_exit_delay);
 
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
-- 
2.25.0

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[Intel-gfx] [PATCH rebased 2/3] drm/i915/dc3co: Check for DC3C0 exit state instead of sleep

[José Roberto de Souza]

DC3C0 could have already exit so no need to always sleep, so lets
read the register with the state.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 21561acfa3ac..1075e4edd2b3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -807,7 +807,7 @@ static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
 	/*
 	 * Delay of 200us DC3CO Exit time B.Spec 49196
 	 */
-	usleep_range(200, 210);
+	intel_de_wait_for_set(dev_priv, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 1);
 }
 
 static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
-- 
2.25.0

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[Intel-gfx] [PATCH rebased 3/3] drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be changed

[José Roberto de Souza]

A recent change in BSpec allow us to change EXTLINE while transcoder
is enabled so this allow us to change it even when doing the first
fastset after taking over previous hardware state set by BIOS.
BIOS don't enable PSR, so if sink supports PSR it will be enabled on
the first fastset, so moving the EXTLINE compute and set to PSR flows
allow us to simplfy a bunch of code.

This will save a lot of time in all the IGT tests that uses CRC, as
when PSR2 is enabled CRCs are not generated, so we switch to PSR1, so
the previous code would compute dc3co_exitline=0 causing a full
modeset that would shutdown pipe, enable and train link.

BSpec: 49196
Cc: Imre Deak <imre.deak@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     | 86 --------------------
 drivers/gpu/drm/i915/display/intel_display.c |  1 -
 drivers/gpu/drm/i915/display/intel_psr.c     | 47 +++++++++++
 3 files changed, 47 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 32ea3c7e8b62..a31375f43f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3347,86 +3347,6 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
 	POSTING_READ(intel_dp->regs.dp_tp_ctl);
 }
 
-static void
-tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
-{
-	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
-	u32 val;
-
-	if (!cstate->dc3co_exitline)
-		return;
-
-	val = I915_READ(EXITLINE(cstate->cpu_transcoder));
-	val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
-	I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
-}
-
-static void
-tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
-{
-	u32 val, exit_scanlines;
-	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
-
-	if (!cstate->dc3co_exitline)
-		return;
-
-	exit_scanlines = cstate->dc3co_exitline;
-	exit_scanlines <<= EXITLINE_SHIFT;
-	val = I915_READ(EXITLINE(cstate->cpu_transcoder));
-	val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
-	val |= exit_scanlines;
-	val |= EXITLINE_ENABLE;
-	I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
-}
-
-static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
-					      struct intel_crtc_state *cstate)
-{
-	u32 exit_scanlines;
-	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
-	u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay;
-
-	cstate->dc3co_exitline = 0;
-
-	if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
-		return;
-
-	/* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
-	if (to_intel_crtc(cstate->uapi.crtc)->pipe != PIPE_A ||
-	    encoder->port != PORT_A)
-		return;
-
-	if (!cstate->has_psr2 || !cstate->hw.active)
-		return;
-
-	/*
-	 * DC3CO Exit time 200us B.Spec 49196
-	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
-	 */
-	exit_scanlines =
-		intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1;
-
-	if (WARN_ON(exit_scanlines > crtc_vdisplay))
-		return;
-
-	cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
-	DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline);
-}
-
-static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
-{
-	u32 val;
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-
-	if (INTEL_GEN(dev_priv) < 12)
-		return;
-
-	val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
-
-	if (val & EXITLINE_ENABLE)
-		crtc_state->dc3co_exitline = val & EXITLINE_MASK;
-}
-
 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state)
@@ -3439,7 +3359,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	int level = intel_ddi_dp_level(intel_dp);
 	enum transcoder transcoder = crtc_state->cpu_transcoder;
 
-	tgl_set_psr2_transcoder_exitline(crtc_state);
 	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
 				 crtc_state->lane_count, is_mst);
 
@@ -3826,7 +3745,6 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
 						  dig_port->ddi_io_power_domain);
 
 	intel_ddi_clk_disable(encoder);
-	tgl_clear_psr2_transcoder_exitline(old_crtc_state);
 }
 
 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
@@ -4410,9 +4328,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 		break;
 	}
 
-	if (encoder->type == INTEL_OUTPUT_EDP)
-		tgl_dc3co_exitline_get_config(pipe_config);
-
 	pipe_config->has_audio =
 		intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
 
@@ -4494,7 +4409,6 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
 		ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
 	} else {
 		ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
-		tgl_dc3co_exitline_compute_config(encoder, pipe_config);
 	}
 
 	if (ret)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dd03987cc24f..165b54fb2d59 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13576,7 +13576,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 	PIPE_CONF_CHECK_I(output_format);
-	PIPE_CONF_CHECK_I(dc3co_exitline);
 	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
 	if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e64e0c4c80dc..c56cdb1c8fb6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -600,6 +600,37 @@ static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
 	tgl_psr2_disable_dc3co(dev_priv);
 }
 
+static void
+tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
+				  struct intel_crtc_state *crtc_state)
+{
+	const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	u32 exit_scanlines;
+
+	if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
+		return;
+
+	/* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
+	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A ||
+	    dig_port->base.port != PORT_A)
+		return;
+
+	/*
+	 * DC3CO Exit time 200us B.Spec 49196
+	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+	 */
+	exit_scanlines =
+		intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
+
+	if (WARN_ON(exit_scanlines > crtc_vdisplay))
+		return;
+
+	crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
+	DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", crtc_state->dc3co_exitline);
+}
+
 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -671,6 +702,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
 	return true;
 }
 
@@ -788,6 +820,21 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 	I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
 
 	psr_irq_control(dev_priv);
+
+	if (INTEL_GEN(dev_priv) >= 12 && dev_priv->psr.psr2_enabled) {
+		u32 val;
+
+		/*
+		 * TODO: if future platforms supports DC3CO in more than one
+		 * transcoder, EXITLINE will need to be unset when disabling PSR
+		 */
+		val = I915_READ(EXITLINE(cpu_transcoder));
+		val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+		val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
+		if (crtc_state->dc3co_exitline)
+			val |= EXITLINE_ENABLE;
+		I915_WRITE(EXITLINE(cpu_transcoder), val);
+	}
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
-- 
2.25.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [rebased,1/3] drm/i915/dc3co: Do the full calculation of DC3CO exit only once

[Patchwork]

== Series Details ==

Series: series starting with [rebased,1/3] drm/i915/dc3co: Do the full calculation of DC3CO exit only once
URL   : https://patchwork.freedesktop.org/series/72132/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7757 -> Patchwork_16135
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/index.html

Known issues
------------

  Here are the changes found in Patchwork_16135 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-skl-6770hq:      [PASS][1] -> [DMESG-WARN][2] ([i915#889])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/fi-skl-6770hq/igt@i915_module_load@reload-with-fault-injection.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/fi-skl-6770hq/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][3] -> [FAIL][4] ([i915#178])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [PASS][5] -> [DMESG-WARN][6] ([i915#44])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@gem_exec_fence@basic-await-default:
    - {fi-ehl-1}:         [INCOMPLETE][7] ([i915#937]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/fi-ehl-1/igt@gem_exec_fence@basic-await-default.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/fi-ehl-1/igt@gem_exec_fence@basic-await-default.html

  * igt@i915_selftest@live_blt:
    - fi-byt-j1900:       [DMESG-FAIL][9] ([i915#725]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/fi-byt-j1900/igt@i915_selftest@live_blt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/fi-byt-j1900/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-byt-j1900:       [DMESG-FAIL][11] ([i915#722]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html

  
#### Warnings ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [DMESG-FAIL][13] ([i915#553] / [i915#725]) -> [DMESG-FAIL][14] ([i915#725])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/fi-hsw-4770r/igt@i915_selftest@live_blt.html
    - fi-hsw-4770:        [DMESG-FAIL][15] ([i915#725]) -> [DMESG-FAIL][16] ([i915#553] / [i915#725])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/fi-hsw-4770/igt@i915_selftest@live_blt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
  [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
  [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
  [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889
  [i915#937]: https://gitlab.freedesktop.org/drm/intel/issues/937


Participating hosts (45 -> 43)
------------------------------

  Additional (5): fi-bsw-n3050 fi-whl-u fi-ivb-3770 fi-bsw-kefka fi-skl-6600u 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-bdw-gvtdvm fi-byt-squawks fi-bsw-cyan fi-tgl-y fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7757 -> Patchwork_16135

  CI-20190529: 20190529
  CI_DRM_7757: 181f4cf3bdbbf2a8a67e406ef16f1cdc957379b6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5370: a98fb02cc2816a48eec374392d9b6941abb6af2c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16135: f6fdaaaf5313aeac850412cb2d728a5735ab4b5f @ git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_16135/build_32bit.log

  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  Building modules, stage 2.
  MODPOST 122 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:93: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1282: recipe for target 'modules' failed
make: *** [modules] Error 2


== Linux commits ==

f6fdaaaf5313 drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be changed
3f5faed5531e drm/i915/dc3co: Check for DC3C0 exit state instead of sleep
321e7f4691c2 drm/i915/dc3co: Do the full calculation of DC3CO exit only once

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/index.html
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[Intel-gfx] ✗ Fi.CI.BUILD: warning for series starting with [rebased,1/3] drm/i915/dc3co: Do the full calculation of DC3CO exit only once

[Patchwork]

== Series Details ==

Series: series starting with [rebased,1/3] drm/i915/dc3co: Do the full calculation of DC3CO exit only once
URL   : https://patchwork.freedesktop.org/series/72132/
State : warning

== Summary ==

CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  Building modules, stage 2.
  MODPOST 122 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:93: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1282: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/build_32bit.log
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [rebased,1/3] drm/i915/dc3co: Do the full calculation of DC3CO exit only once

[Patchwork]

== Series Details ==

Series: series starting with [rebased,1/3] drm/i915/dc3co: Do the full calculation of DC3CO exit only once
URL   : https://patchwork.freedesktop.org/series/72132/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7757_full -> Patchwork_16135_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_16135_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110841])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_ctx_shared@q-smoketest-bsd1:
    - shard-tglb:         [PASS][5] -> [INCOMPLETE][6] ([fdo#111735] / [i915#472]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb1/igt@gem_ctx_shared@q-smoketest-bsd1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb4/igt@gem_ctx_shared@q-smoketest-bsd1.html

  * igt@gem_exec_gttfill@basic:
    - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#111593] / [i915#472])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb5/igt@gem_exec_gttfill@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb6/igt@gem_exec_gttfill@basic.html

  * igt@gem_exec_parallel@vcs1:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#112080]) +4 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb2/igt@gem_exec_parallel@vcs1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb8/igt@gem_exec_parallel@vcs1.html

  * igt@gem_exec_schedule@pi-userfault-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([i915#677])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb6/igt@gem_exec_schedule@pi-userfault-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb2/igt@gem_exec_schedule@pi-userfault-bsd.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#109276]) +7 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html

  * igt@gem_exec_schedule@smoketest-bsd1:
    - shard-tglb:         [PASS][15] -> [INCOMPLETE][16] ([i915#463] / [i915#472])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb5/igt@gem_exec_schedule@smoketest-bsd1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb4/igt@gem_exec_schedule@smoketest-bsd1.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-kbl2/igt@gem_exec_suspend@basic-s3.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-kbl7/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive:
    - shard-glk:          [PASS][19] -> [TIMEOUT][20] ([fdo#112271] / [i915#530])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-glk3/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-glk2/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
    - shard-hsw:          [PASS][21] -> [INCOMPLETE][22] ([i915#530] / [i915#61])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-hsw5/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-hsw5/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html

  * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
    - shard-skl:          [PASS][23] -> [TIMEOUT][24] ([fdo#112271] / [i915#530])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl10/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl4/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-kbl:          [PASS][25] -> [TIMEOUT][26] ([fdo#112271] / [i915#530]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-kbl4/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-kbl4/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-apl:          [PASS][27] -> [TIMEOUT][28] ([fdo#112271] / [i915#530])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-apl6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-apl4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
    - shard-hsw:          [PASS][29] -> [TIMEOUT][30] ([fdo#112271] / [i915#530])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_persistent_relocs@forked-thrashing:
    - shard-kbl:          [PASS][31] -> [INCOMPLETE][32] ([fdo#103665] / [i915#530]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-kbl1/igt@gem_persistent_relocs@forked-thrashing.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-kbl6/igt@gem_persistent_relocs@forked-thrashing.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][33] -> [FAIL][34] ([i915#644])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-glk4/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][35] -> [FAIL][36] ([i915#454])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
    - shard-skl:          [PASS][37] -> [FAIL][38] ([i915#454])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl4/igt@i915_pm_dc@dc6-psr.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl4/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rps@waitboost:
    - shard-iclb:         [PASS][39] -> [FAIL][40] ([i915#413])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb4/igt@i915_pm_rps@waitboost.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb4/igt@i915_pm_rps@waitboost.html

  * igt@i915_selftest@live_requests:
    - shard-tglb:         [PASS][41] -> [INCOMPLETE][42] ([i915#472])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb8/igt@i915_selftest@live_requests.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb5/igt@i915_selftest@live_requests.html

  * igt@i915_suspend@debugfs-reader:
    - shard-iclb:         [PASS][43] -> [DMESG-WARN][44] ([fdo#111764])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb2/igt@i915_suspend@debugfs-reader.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb1/igt@i915_suspend@debugfs-reader.html

  * igt@kms_color@pipe-a-ctm-0-75:
    - shard-skl:          [PASS][45] -> [DMESG-WARN][46] ([i915#109]) +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl4/igt@kms_color@pipe-a-ctm-0-75.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl5/igt@kms_color@pipe-a-ctm-0-75.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x42-random:
    - shard-tglb:         [PASS][47] -> [DMESG-WARN][48] ([i915#402])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html

  * igt@kms_flip@flip-vs-dpms-off-vs-modeset:
    - shard-kbl:          [PASS][49] -> [DMESG-WARN][50] ([i915#56] / [i915#78])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-kbl2/igt@kms_flip@flip-vs-dpms-off-vs-modeset.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-kbl2/igt@kms_flip@flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-glk:          [PASS][51] -> [FAIL][52] ([i915#79])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-glk9/igt@kms_flip@flip-vs-expired-vblank.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-glk4/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip_tiling@flip-x-tiled:
    - shard-skl:          [PASS][53] -> [FAIL][54] ([fdo#108145] / [i915#699])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl1/igt@kms_flip_tiling@flip-x-tiled.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl3/igt@kms_flip_tiling@flip-x-tiled.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [PASS][55] -> [FAIL][56] ([fdo#108145]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][57] -> [FAIL][58] ([fdo#108145] / [i915#265])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [PASS][59] -> [SKIP][60] ([fdo#109441]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@perf@short-reads:
    - shard-glk:          [PASS][61] -> [TIMEOUT][62] ([fdo#112271] / [i915#51])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-glk8/igt@perf@short-reads.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-glk8/igt@perf@short-reads.html

  * igt@perf_pmu@enable-race-vecs0:
    - shard-tglb:         [PASS][63] -> [INCOMPLETE][64] ([i915#470] / [i915#472])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb4/igt@perf_pmu@enable-race-vecs0.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb3/igt@perf_pmu@enable-race-vecs0.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@bcs0-mixed-process:
    - shard-skl:          [FAIL][65] ([i915#679]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl4/igt@gem_ctx_persistence@bcs0-mixed-process.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl8/igt@gem_ctx_persistence@bcs0-mixed-process.html

  * igt@gem_ctx_persistence@processes:
    - shard-glk:          [FAIL][67] ([i915#570]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-glk2/igt@gem_ctx_persistence@processes.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-glk4/igt@gem_ctx_persistence@processes.html

  * igt@gem_ctx_persistence@rcs0-mixed-process:
    - shard-apl:          [FAIL][69] ([i915#679]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-apl3/igt@gem_ctx_persistence@rcs0-mixed-process.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-apl6/igt@gem_ctx_persistence@rcs0-mixed-process.html

  * igt@gem_ctx_persistence@vcs1-queued:
    - shard-iclb:         [SKIP][71] ([fdo#109276] / [fdo#112080]) -> [PASS][72] +2 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_ctx_shared@q-smoketest-bsd2:
    - shard-tglb:         [INCOMPLETE][73] ([i915#461] / [i915#472]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb4/igt@gem_ctx_shared@q-smoketest-bsd2.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb1/igt@gem_ctx_shared@q-smoketest-bsd2.html

  * igt@gem_eio@kms:
    - shard-snb:          [INCOMPLETE][75] ([i915#82]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-snb6/igt@gem_eio@kms.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-snb1/igt@gem_eio@kms.html
    - shard-tglb:         [INCOMPLETE][77] ([i915#472] / [i915#476]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb3/igt@gem_eio@kms.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb1/igt@gem_eio@kms.html

  * igt@gem_exec_await@wide-all:
    - shard-tglb:         [INCOMPLETE][79] ([fdo#111736] / [i915#472]) -> [PASS][80] +2 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb3/igt@gem_exec_await@wide-all.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb4/igt@gem_exec_await@wide-all.html

  * igt@gem_exec_create@forked:
    - shard-tglb:         [INCOMPLETE][81] ([fdo#108838] / [i915#472]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb7/igt@gem_exec_create@forked.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb5/igt@gem_exec_create@forked.html

  * igt@gem_exec_parallel@vcs0-fds:
    - shard-tglb:         [INCOMPLETE][83] ([i915#470] / [i915#472]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb3/igt@gem_exec_parallel@vcs0-fds.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb3/igt@gem_exec_parallel@vcs0-fds.html

  * igt@gem_exec_reloc@basic-gtt-wc-active:
    - shard-skl:          [DMESG-WARN][85] ([i915#109]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl6/igt@gem_exec_reloc@basic-gtt-wc-active.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl6/igt@gem_exec_reloc@basic-gtt-wc-active.html

  * igt@gem_exec_schedule@preempt-queue-bsd:
    - shard-iclb:         [SKIP][87] ([fdo#112146]) -> [PASS][88] +2 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1:
    - shard-tglb:         [INCOMPLETE][89] ([fdo#111677] / [i915#472]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb7/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html

  * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
    - shard-kbl:          [TIMEOUT][91] ([fdo#112271] / [i915#530]) -> [PASS][92] +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-kbl4/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-kbl3/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-skl:          [TIMEOUT][93] ([fdo#112271] / [i915#530]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@i915_pm_rpm@debugfs-read:
    - shard-skl:          [INCOMPLETE][95] ([i915#151]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl9/igt@i915_pm_rpm@debugfs-read.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl4/igt@i915_pm_rpm@debugfs-read.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - shard-kbl:          [INCOMPLETE][97] ([fdo#103665] / [i915#151]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-kbl3/igt@i915_pm_rpm@system-suspend-modeset.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-kbl6/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][99] ([i915#180]) -> [PASS][100] +2 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][101] ([IGT#5]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][103] ([i915#79]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [DMESG-WARN][105] ([i915#180]) -> [PASS][106] +2 similar issues
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_tiling@flip-changes-tiling-yf:
    - shard-skl:          [FAIL][107] ([i915#699]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl1/igt@kms_flip_tiling@flip-changes-tiling-yf.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl3/igt@kms_flip_tiling@flip-changes-tiling-yf.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-tglb:         [FAIL][109] ([i915#49]) -> [PASS][110] +5 similar issues
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
    - shard-tglb:         [SKIP][111] ([i915#668]) -> [PASS][112] +1 similar issue
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb5/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][113] ([fdo#108145]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [SKIP][115] ([fdo#109441]) -> [PASS][116] +4 similar issues
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@perf_pmu@busy-accuracy-98-vcs1:
    - shard-iclb:         [SKIP][117] ([fdo#112080]) -> [PASS][118] +2 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb5/igt@perf_pmu@busy-accuracy-98-vcs1.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb1/igt@perf_pmu@busy-accuracy-98-vcs1.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][119] ([fdo#109276]) -> [PASS][120] +17 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [FAIL][121] ([i915#454]) -> [SKIP][122] ([i915#468])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7757/shard-tglb8/igt@i915_pm_dc@dc6-psr.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/shard-tglb1/igt@i915_pm_dc@dc6-psr.html

  
  [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108838]: https://bugs.freedesktop.org/show_bug.cgi?id=108838
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#461]: https://gitlab.freedesktop.org/drm/intel/issues/461
  [i915#463]: https://gitlab.freedesktop.org/drm/intel/issues/463
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
  [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
  [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
  [i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
  [i915#56]: https://gitlab.freedesktop.org/drm/intel/issues/56
  [i915#570]: https://gitlab.freedesktop.org/drm/intel/issues/570
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
  [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7757 -> Patchwork_16135

  CI-20190529: 20190529
  CI_DRM_7757: 181f4cf3bdbbf2a8a67e406ef16f1cdc957379b6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5370: a98fb02cc2816a48eec374392d9b6941abb6af2c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16135: f6fdaaaf5313aeac850412cb2d728a5735ab4b5f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16135/index.html
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Re: [Intel-gfx] [PATCH rebased 2/3] drm/i915/dc3co: Check for DC3C0 exit state instead of sleep

[Anshuman Gupta]

On 2020-01-16 at 10:54:20 -0800, José Roberto de Souza wrote:
> DC3C0 could have already exit so no need to always sleep, so lets
> read the register with the state.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 21561acfa3ac..1075e4edd2b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -807,7 +807,7 @@ static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
>  	/*
>  	 * Delay of 200us DC3CO Exit time B.Spec 49196
>  	 */
> -	usleep_range(200, 210);
> +	intel_de_wait_for_set(dev_priv, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 1);
It is not documented in B.Specs to wait for DC3CO status, and this DC3CO status bit is
just for DEBUG purpose.
what if, it have never reached DC3CO due to PSR2 edp link is never gets to sleep
i.e 9th bit of PSR2_STATUS, it is going to wait for entire 1ms with this patch.
Lets say if DC3CO is already exited and we land here in disallow sequence, B.Specs
sequence first clear the DC3CO status bit before disabling it, so then also
it is going to wait for entire 1ms with this patch.
I think wait_for_us() will be better choice if, we want to wait for DC3CO exit status
rahter then plain sleep.
And while reviewing B.Specs there is recent change that we also need to disable 
PSR2 in DC3CO dsiallow sequence (Not related to this patch).
Thanks,
Anshuman Gupta.

>  }
>  
>  static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> -- 
> 2.25.0
> 
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Re: [Intel-gfx] [PATCH rebased 1/3] drm/i915/dc3co: Do the full calculation of DC3CO exit only once

[Anshuman Gupta]

Looks good to me.
On 2020-01-16 at 10:54:19 -0800, José Roberto de Souza wrote:
> This will calculaet the DC3CO exit delay only once per full modeset.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1d2fd1a8925a..e64e0c4c80dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -802,7 +802,9 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>  	dev_priv->psr.busy_frontbuffer_bits = 0;
>  	dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>  	dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
> -	dev_priv->psr.dc3co_exit_delay = intel_get_frame_time_us(crtc_state);
> +	/* DC5/DC6 required idle frames = 6 */
> +	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> +	dev_priv->psr.dc3co_exit_delay = val;
>  	dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
>  
>  	/*
> @@ -1277,8 +1279,6 @@ static void
>  tgl_dc3co_flush(struct drm_i915_private *dev_priv,
>  		unsigned int frontbuffer_bits, enum fb_op_origin origin)
>  {
> -	u32 delay;
> -
>  	mutex_lock(&dev_priv->psr.lock);
>  
>  	if (!dev_priv->psr.dc3co_enabled)
> @@ -1296,10 +1296,8 @@ tgl_dc3co_flush(struct drm_i915_private *dev_priv,
>  		goto unlock;
>  
>  	tgl_psr2_enable_dc3co(dev_priv);
> -	/* DC5/DC6 required idle frames = 6 */
> -	delay = 6 * dev_priv->psr.dc3co_exit_delay;
>  	mod_delayed_work(system_wq, &dev_priv->psr.idle_work,
> -			 usecs_to_jiffies(delay));
> +			 dev_priv->psr.dc3co_exit_delay);
>  
>  unlock:
>  	mutex_unlock(&dev_priv->psr.lock);
> -- 
> 2.25.0
> 
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Re: [Intel-gfx] [PATCH rebased 3/3] drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be changed

[Anshuman Gupta]

On 2020-01-16 at 10:54:21 -0800, José Roberto de Souza wrote:
> A recent change in BSpec allow us to change EXTLINE while transcoder
> is enabled so this allow us to change it even when doing the first
> fastset after taking over previous hardware state set by BIOS.
> BIOS don't enable PSR, so if sink supports PSR it will be enabled on
> the first fastset, so moving the EXTLINE compute and set to PSR flows
> allow us to simplfy a bunch of code.
> 
> This will save a lot of time in all the IGT tests that uses CRC, as
> when PSR2 is enabled CRCs are not generated, so we switch to PSR1, so
> the previous code would compute dc3co_exitline=0 causing a full
> modeset that would shutdown pipe, enable and train link.
> 
> BSpec: 49196
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c     | 86 --------------------
>  drivers/gpu/drm/i915/display/intel_display.c |  1 -
>  drivers/gpu/drm/i915/display/intel_psr.c     | 47 +++++++++++
>  3 files changed, 47 insertions(+), 87 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 32ea3c7e8b62..a31375f43f2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3347,86 +3347,6 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
>  	POSTING_READ(intel_dp->regs.dp_tp_ctl);
>  }
>  
> -static void
> -tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
> -	u32 val;
> -
> -	if (!cstate->dc3co_exitline)
> -		return;
> -
> -	val = I915_READ(EXITLINE(cstate->cpu_transcoder));
> -	val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
> -	I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
> -}
> -
> -static void
> -tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
> -{
> -	u32 val, exit_scanlines;
> -	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
> -
> -	if (!cstate->dc3co_exitline)
> -		return;
> -
> -	exit_scanlines = cstate->dc3co_exitline;
> -	exit_scanlines <<= EXITLINE_SHIFT;
> -	val = I915_READ(EXITLINE(cstate->cpu_transcoder));
> -	val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
> -	val |= exit_scanlines;
> -	val |= EXITLINE_ENABLE;
> -	I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
> -}
> -
> -static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
> -					      struct intel_crtc_state *cstate)
> -{
> -	u32 exit_scanlines;
> -	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
> -	u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay;
> -
> -	cstate->dc3co_exitline = 0;
> -
> -	if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
> -		return;
> -
> -	/* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
> -	if (to_intel_crtc(cstate->uapi.crtc)->pipe != PIPE_A ||
> -	    encoder->port != PORT_A)
> -		return;
> -
> -	if (!cstate->has_psr2 || !cstate->hw.active)
> -		return;
> -
> -	/*
> -	 * DC3CO Exit time 200us B.Spec 49196
> -	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
> -	 */
> -	exit_scanlines =
> -		intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1;
> -
> -	if (WARN_ON(exit_scanlines > crtc_vdisplay))
> -		return;
> -
> -	cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
> -	DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline);
> -}
> -
> -static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
> -{
> -	u32 val;
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -
> -	if (INTEL_GEN(dev_priv) < 12)
> -		return;
> -
> -	val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
> -
> -	if (val & EXITLINE_ENABLE)
> -		crtc_state->dc3co_exitline = val & EXITLINE_MASK;
> -}
> -
>  static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
>  				  const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state *conn_state)
> @@ -3439,7 +3359,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
>  	int level = intel_ddi_dp_level(intel_dp);
>  	enum transcoder transcoder = crtc_state->cpu_transcoder;
>  
> -	tgl_set_psr2_transcoder_exitline(crtc_state);
>  	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
>  				 crtc_state->lane_count, is_mst);
>  
> @@ -3826,7 +3745,6 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
>  						  dig_port->ddi_io_power_domain);
>  
>  	intel_ddi_clk_disable(encoder);
> -	tgl_clear_psr2_transcoder_exitline(old_crtc_state);
>  }
>  
>  static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
> @@ -4410,9 +4328,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  		break;
>  	}
>  
> -	if (encoder->type == INTEL_OUTPUT_EDP)
> -		tgl_dc3co_exitline_get_config(pipe_config);
> -
>  	pipe_config->has_audio =
>  		intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
>  
> @@ -4494,7 +4409,6 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
>  		ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
>  	} else {
>  		ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
> -		tgl_dc3co_exitline_compute_config(encoder, pipe_config);
>  	}
>  
>  	if (ret)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index dd03987cc24f..165b54fb2d59 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13576,7 +13576,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  
>  	PIPE_CONF_CHECK_I(pixel_multiplier);
>  	PIPE_CONF_CHECK_I(output_format);
> -	PIPE_CONF_CHECK_I(dc3co_exitline);
>  	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
>  	if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
>  	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index e64e0c4c80dc..c56cdb1c8fb6 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -600,6 +600,37 @@ static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
>  	tgl_psr2_disable_dc3co(dev_priv);
>  }
>  
> +static void
> +tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
> +				  struct intel_crtc_state *crtc_state)
> +{
> +	const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	u32 exit_scanlines;
> +
> +	if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
> +		return;
> +
> +	/* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
> +	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A ||
> +	    dig_port->base.port != PORT_A)
> +		return;
> +
> +	/*
> +	 * DC3CO Exit time 200us B.Spec 49196
> +	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
> +	 */
> +	exit_scanlines =
> +		intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
> +
> +	if (WARN_ON(exit_scanlines > crtc_vdisplay))
> +		return;
> +
> +	crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
> +	DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", crtc_state->dc3co_exitline);
> +}
> +
>  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  				    struct intel_crtc_state *crtc_state)
>  {
> @@ -671,6 +702,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  		return false;
>  	}
>  
> +	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
>  	return true;
>  }
>  
> @@ -788,6 +820,21 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  	I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
>  
>  	psr_irq_control(dev_priv);
> +
> +	if (INTEL_GEN(dev_priv) >= 12 && dev_priv->psr.psr2_enabled) {
As i recalled earlier, i had commented to check for dc3co flag instead
of psr2 flag to program exitline, what is the advantage we are getting here
to program exitline if dc3co_exitline is zero? 
Thanks,
Anshuman Gupta.
> +		u32 val;
> +
> +		/*
> +		 * TODO: if future platforms supports DC3CO in more than one
> +		 * transcoder, EXITLINE will need to be unset when disabling PSR
> +		 */
> +		val = I915_READ(EXITLINE(cpu_transcoder));
> +		val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
> +		val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
> +		if (crtc_state->dc3co_exitline)
> +			val |= EXITLINE_ENABLE;
> +		I915_WRITE(EXITLINE(cpu_transcoder), val);
> +	}
>  }
>  
>  static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> -- 
> 2.25.0
> 
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