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From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Matt Roper" <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev4)
Date: Mon, 04 May 2020 23:10:57 -0000	[thread overview]
Message-ID: <158863385704.5818.3219638168519352538@emeril.freedesktop.org> (raw)
In-Reply-To: <20200504225227.464666-1-matthew.d.roper@intel.com>

== Series Details ==

Series: Introduce Rocket Lake (rev4)
URL   : https://patchwork.freedesktop.org/series/76826/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e6bef4e2c937 drm/i915/rkl: Add RKL platform info and PCI ids
-:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#35: FILE: drivers/gpu/drm/i915/i915_drv.h:1522:
+#define IS_RKL_REVID(p, since, until) \
+	(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))

-:102: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#102: FILE: include/drm/i915_pciids.h:609:
+#define INTEL_RKL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4C80, info), \
+	INTEL_VGA_DEVICE(0x4C8A, info), \
+	INTEL_VGA_DEVICE(0x4C8B, info), \
+	INTEL_VGA_DEVICE(0x4C8C, info), \
+	INTEL_VGA_DEVICE(0x4C90, info), \
+	INTEL_VGA_DEVICE(0x4C9A, info)

-:102: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#102: FILE: include/drm/i915_pciids.h:609:
+#define INTEL_RKL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4C80, info), \
+	INTEL_VGA_DEVICE(0x4C8A, info), \
+	INTEL_VGA_DEVICE(0x4C8B, info), \
+	INTEL_VGA_DEVICE(0x4C8C, info), \
+	INTEL_VGA_DEVICE(0x4C90, info), \
+	INTEL_VGA_DEVICE(0x4C9A, info)

total: 1 errors, 0 warnings, 2 checks, 69 lines checked
803b4f04888a x86/gpu: add RKL stolen memory support
630f1d4d8718 drm/i915/rkl: Re-use TGL GuC/HuC firmware
90f79585717f drm/i915/rkl: Load DMC firmware for Rocket Lake
1c85ab4847be drm/i915/rkl: Add PCH support
dc4048963014 drm/i915/rkl: Update memory bandwidth parameters
a445dde7ad9f drm/i915/rkl: Limit number of universal planes to 5
f02fc9990788 drm/i915/rkl: Add power well support
fda2d4b25173 drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
-:36: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#36: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:5261:
+		min_buddy = max_buddy = 0;

total: 0 errors, 0 warnings, 1 checks, 84 lines checked
7846d1a805b9 drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
02aa4c0c4f8f drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
1c3381316fe1 drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
a8c3d67dc688 drm/i915/rkl: Setup ports/phys
196dbf07dad1 drm/i915/rkl: provide port/phy mapping for vbt
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#17: 
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]

total: 0 errors, 1 warnings, 0 checks, 104 lines checked
3c2d8a199e89 drm/i915/rkl: Add DDC pin mapping
b8b1dbd88b20 drm/i915/rkl: Don't try to access transcoder D
6906840e8b24 drm/i915/rkl: Don't try to read out DSI transcoders
5018930e1944 drm/i915/rkl: Handle comp master/slave relationships for PHYs
69bfbb9c7a02 drm/i915/rkl: Add DPLL4 support
8b97223a1c60 drm/i915/rkl: Handle HTI
-:92: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#92: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:274:
+{
+

-:154: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#154: FILE: drivers/gpu/drm/i915/i915_reg.h:2903:
+#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*phy + 2)
                                  	         ^

-:154: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'phy' may be better as '(phy)' to avoid precedence issues
#154: FILE: drivers/gpu/drm/i915/i915_reg.h:2903:
+#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*phy + 2)

-:155: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#155: FILE: drivers/gpu/drm/i915/i915_reg.h:2904:
+#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*phy + 1)
                                    	         ^

-:155: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'phy' may be better as '(phy)' to avoid precedence issues
#155: FILE: drivers/gpu/drm/i915/i915_reg.h:2904:
+#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*phy + 1)

total: 0 errors, 0 warnings, 5 checks, 116 lines checked
0126c509f30f drm/i915/rkl: Disable PSR2
9b58f54fa37e drm/i915/rkl: Add initial workarounds

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  parent reply	other threads:[~2020-05-04 23:10 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids Matt Roper
2020-05-07 11:18   ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support Matt Roper
2020-05-06 11:51   ` Srivatsa, Anusha
2020-05-19 23:57     ` Lucas De Marchi
2020-05-20  9:30       ` Borislav Petkov
2020-05-20 17:49         ` Lucas De Marchi
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/rkl: Re-use TGL GuC/HuC firmware Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/rkl: Load DMC firmware for Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/rkl: Add PCH support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters Matt Roper
2020-05-07 12:24   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5 Matt Roper
2020-05-07 12:10   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support Matt Roper
2020-05-05  4:50   ` Anshuman Gupta
2020-05-05 14:39     ` Matt Roper
2020-05-05 16:09       ` Imre Deak
2020-05-06 12:13         ` Anshuman Gupta
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 09/22] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Matt Roper
2020-05-06 13:49   ` Srivatsa, Anusha
2020-05-06 16:49     ` Matt Roper
2020-05-07 11:22       ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 11/22] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs Matt Roper
2020-05-07 11:38   ` Srivatsa, Anusha
2020-05-07 11:59   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 13/22] drm/i915/rkl: Setup ports/phys Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
2020-05-07 12:04   ` Ville Syrjälä
2020-05-07 18:05     ` Matt Roper
2020-05-08  9:44       ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping Matt Roper
2020-05-06  9:19   ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D Matt Roper
2020-05-06 20:34   ` Matt Roper
2020-05-06 21:21   ` [Intel-gfx] [PATCH v3 " Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-05-07 11:58   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
2020-05-06  9:20   ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/rkl: Handle HTI Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/rkl: Disable PSR2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/rkl: Add initial workarounds Matt Roper
2020-05-04 23:10 ` Patchwork [this message]
2020-05-04 23:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Rocket Lake (rev4) Patchwork
2020-05-05 13:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-05-06 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev5) Patchwork
2020-05-06 22:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-07  2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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