* [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches
@ 2021-01-25 14:07 Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 01/10] x86/gpu: Add Alderlake-S stolen memory support Aditya Swarup
` (18 more replies)
0 siblings, 19 replies; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
This patch revises all the changes suggested in rev 3 of
Introduce Alderlake-S series for first 10 patches.
https://patchwork.freedesktop.org/patch/405772/?series=82917&rev=3
Most of the patches have already been reviewed and are good for merge.
I will resend rest of the series once we have focussed reviews on the
pending patches.
Please ignore the patch:
x86/gpu: Add Alderlake-S stolen memory support
as it was picked up to prevent compilation issues and maintaining
sequence of patches.
The correct location for picking the latest revision of that patch is
here:
https://patchwork.freedesktop.org/series/86239/
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Aditya Swarup (5):
drm/i915/adl_s: Configure DPLL for ADL-S
drm/i915/adl_s: Configure Port clock registers for ADL-S
drm/i915/adl_s: Initialize display for ADL-S
drm/i915/adl_s: Add adl-s ddc pin mapping
drm/i915/adl_s: Add vbt port and aux channel settings for adls
Anusha Srivatsa (3):
drm/i915/adl_s: Add PCH support
drm/i915/adl_s: Add Interrupt Support
drm/i915/adl_s: Add PHYs for Alderlake S
Caz Yokoyama (1):
x86/gpu: Add Alderlake-S stolen memory support
Matt Roper (1):
drm/i915/adl_s: Update combo PHY master/slave relationships
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/display/intel_bios.c | 70 +++++++++++++++----
.../gpu/drm/i915/display/intel_combo_phy.c | 11 ++-
drivers/gpu/drm/i915/display/intel_ddi.c | 62 ++++++++++------
drivers/gpu/drm/i915/display/intel_display.c | 31 +++++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 ++++++++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +++++-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++
drivers/gpu/drm/i915/i915_irq.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++--
drivers/gpu/drm/i915/intel_pch.c | 8 ++-
drivers/gpu/drm/i915/intel_pch.h | 3 +
12 files changed, 246 insertions(+), 55 deletions(-)
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 01/10] x86/gpu: Add Alderlake-S stolen memory support
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
@ 2021-01-25 14:07 ` Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 02/10] drm/i915/adl_s: Add PCH support Aditya Swarup
` (17 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Caz Yokoyama <caz.yokoyama@intel.com>
Alderlake-S is a Gen 12 based hybrid processor architeture. As it
belongs to Gen 12 family, it uses the same GTT stolen memory settings
like its predecessors - ICL(Gen 11) and TGL(Gen 12). This patch inherits
the gen11 and gen 9 quirks for determining base and size of stolen
memory.
Note that this patch depends on commit 0883d63b19bb
("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
Bspec: 52055
Bspec: 49589
Bspec: 49636
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
arch/x86/kernel/early-quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index a4b5af03dcc1..6edd1e2ee8af 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -551,6 +551,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
INTEL_EHL_IDS(&gen11_early_ops),
INTEL_TGL_12_IDS(&gen11_early_ops),
INTEL_RKL_IDS(&gen11_early_ops),
+ INTEL_ADLS_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 02/10] drm/i915/adl_s: Add PCH support
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 01/10] x86/gpu: Add Alderlake-S stolen memory support Aditya Swarup
@ 2021-01-25 14:07 ` Aditya Swarup
2021-01-25 17:39 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 03/10] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
` (16 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Add support for Alderpoint(ADP) PCH used with Alderlake-S.
v2:
- Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup)
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_pch.c | 8 +++++++-
drivers/gpu/drm/i915/intel_pch.h | 3 +++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index ecaf314d60b6..4813207fc053 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
return PCH_JSP;
+ case INTEL_PCH_ADP_DEVICE_ID_TYPE:
+ drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
+ drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv));
+ return PCH_ADP;
default:
return PCH_NONE;
}
@@ -156,7 +160,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
* make an educated guess as to which PCH is really there.
*/
- if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
+ else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
else if (IS_JSL_EHL(dev_priv))
id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 06d2cd50af0b..7318377503b0 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -26,6 +26,7 @@ enum intel_pch {
PCH_JSP, /* Jasper Lake PCH */
PCH_MCC, /* Mule Creek Canyon PCH */
PCH_TGP, /* Tiger Lake PCH */
+ PCH_ADP, /* Alder Lake PCH */
/* Fake PCHs, functionality handled on the same PCI dev */
PCH_DG1 = 1024,
@@ -53,12 +54,14 @@ enum intel_pch {
#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380
#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
+#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 03/10] drm/i915/adl_s: Add Interrupt Support
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 01/10] x86/gpu: Add Alderlake-S stolen memory support Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 02/10] drm/i915/adl_s: Add PCH support Aditya Swarup
@ 2021-01-25 14:07 ` Aditya Swarup
2021-01-25 17:46 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 04/10] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
` (15 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
ADLS follows ICP/TGP like interrupts.
v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 33019cf0e630..6568e7e9fe2a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -209,8 +209,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
if (HAS_PCH_DG1(dev_priv))
hpd->pch_hpd = hpd_sde_dg1;
- else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
- HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
hpd->pch_hpd = hpd_icp;
else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
hpd->pch_hpd = hpd_spt;
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 04/10] drm/i915/adl_s: Add PHYs for Alderlake S
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (2 preceding siblings ...)
2021-01-25 14:07 ` [Intel-gfx] [PATCH 03/10] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
@ 2021-01-25 14:07 ` Aditya Swarup
2021-01-25 17:51 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 05/10] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
` (14 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Alderlake-S has 5 combo phys, add reg definitions for
combo phys and update the port to phy helper for ADL-S.
v2:
- Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc()
and return false for platforms RKL,DG1 and ADLS.(mdroper)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++-----
drivers/gpu/drm/i915/i915_reg.h | 5 ++++-
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7ec7d94b8cdb..acf06feffd3e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5668,6 +5668,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
+ else if (IS_ALDERLAKE_S(dev_priv))
+ return phy <= PHY_E;
else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_JSL_EHL(dev_priv))
@@ -5680,11 +5682,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
- return false;
- else if (INTEL_GEN(dev_priv) >= 12)
+ if (IS_TIGERLAKE(dev_priv))
return phy >= PHY_D && phy <= PHY_I;
- else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
+ else if (IS_ICELAKE(dev_priv))
return phy >= PHY_C && phy <= PHY_F;
else
return false;
@@ -5692,7 +5692,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
+ if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
+ return PHY_B + port - PORT_TC1;
+ else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
return PHY_C + port - PORT_TC1;
else if (IS_JSL_EHL(i915) && port == PORT_D)
return PHY_A;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b9bbc6bacb1..0fe499840b82 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1874,10 +1874,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _ICL_COMBOPHY_B 0x6C000
#define _EHL_COMBOPHY_C 0x160000
#define _RKL_COMBOPHY_D 0x161000
+#define _ADL_COMBOPHY_E 0x16B000
+
#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
_ICL_COMBOPHY_B, \
_EHL_COMBOPHY_C, \
- _RKL_COMBOPHY_D)
+ _RKL_COMBOPHY_D, \
+ _ADL_COMBOPHY_E)
/* CNL/ICL Port CL_DW registers */
#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 05/10] drm/i915/adl_s: Configure DPLL for ADL-S
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (3 preceding siblings ...)
2021-01-25 14:07 ` [Intel-gfx] [PATCH 04/10] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
@ 2021-01-25 14:07 ` Aditya Swarup
2021-01-25 18:45 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 06/10] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
` (13 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
Add changes for configuring DPLL for ADL-S
- Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
- Extend CNL macro to choose DPLL_ENABLE
for ADL-S.
- Select CFGCR0 and CFGCR1 for ADL-S plls.
On BSpec: 53720 PLL arrangement dig for adls:
DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1)
v2 (Lucas): add missing update_ref_clks
Bspec: 50288
Bspec: 50289
Bspec: 49443
v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield
for DPLL3_USED.(mdroper)
Bspec: 53707
v4: BSpec 53723 has been updated with note - DPLL2 is
controlled by DPLL4 CFGCR 0/1.(mdroper)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++-
2 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f6ad257a260e..529b1d569af2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3559,7 +3559,13 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL3) |
+ BIT(DPLL_ID_DG1_DPLL2) |
+ BIT(DPLL_ID_ICL_DPLL1) |
+ BIT(DPLL_ID_ICL_DPLL0);
+ } else if (IS_DG1(dev_priv)) {
if (port == PORT_D || port == PORT_E) {
dpll_mask =
BIT(DPLL_ID_DG1_DPLL2) |
@@ -3865,7 +3871,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id));
+ } else if (IS_DG1(dev_priv)) {
hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
} else if (IS_ROCKETLAKE(dev_priv)) {
@@ -3921,7 +3930,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg;
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
+ cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
+ } else if (IS_DG1(dev_priv)) {
cfgcr0_reg = DG1_DPLL_CFGCR0(id);
cfgcr1_reg = DG1_DPLL_CFGCR1(id);
} else if (IS_ROCKETLAKE(dev_priv)) {
@@ -4384,6 +4396,22 @@ static const struct intel_dpll_mgr dg1_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info adls_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+ { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr adls_pll_mgr = {
+ .dpll_info = adls_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .update_ref_clks = icl_update_dpll_ref_clks,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4397,7 +4425,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_DG1(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ dpll_mgr = &adls_pll_mgr;
+ else if (IS_DG1(dev_priv))
dpll_mgr = &dg1_pll_mgr;
else if (IS_ROCKETLAKE(dev_priv))
dpll_mgr = &rkl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0fe499840b82..339532222d7c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2930,7 +2930,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
#define HDPORT_STATE _MMIO(0x45050)
-#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
+#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
#define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
#define HDPORT_ENABLED REG_BIT(0)
@@ -10394,11 +10394,14 @@ enum skl_power_gate {
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
+#define _ADLS_DPLL2_ENABLE 0x46018
+#define _ADLS_DPLL3_ENABLE 0x46030
#define PLL_ENABLE (1 << 31)
#define PLL_LOCK (1 << 30)
#define PLL_POWER_ENABLE (1 << 27)
#define PLL_POWER_STATE (1 << 26)
-#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
+#define CNL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+ _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
#define TBT_PLL_ENABLE _MMIO(0x46020)
@@ -10644,6 +10647,21 @@ enum skl_power_gate {
_DG1_DPLL2_CFGCR1, \
_DG1_DPLL3_CFGCR1)
+/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
+#define _ADLS_DPLL3_CFGCR0 0x1642C0
+#define _ADLS_DPLL4_CFGCR0 0x164294
+#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _ADLS_DPLL4_CFGCR0, \
+ _ADLS_DPLL3_CFGCR0)
+
+#define _ADLS_DPLL3_CFGCR1 0x1642C4
+#define _ADLS_DPLL4_CFGCR1 0x164298
+#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _ADLS_DPLL4_CFGCR1, \
+ _ADLS_DPLL3_CFGCR1)
+
#define _DKL_PHY1_BASE 0x168000
#define _DKL_PHY2_BASE 0x169000
#define _DKL_PHY3_BASE 0x16A000
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 06/10] drm/i915/adl_s: Configure Port clock registers for ADL-S
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (4 preceding siblings ...)
2021-01-25 14:07 ` [Intel-gfx] [PATCH 05/10] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
@ 2021-01-25 14:07 ` Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 07/10] drm/i915/adl_s: Initialize display " Aditya Swarup
` (12 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
Add changes to configure port clock registers for ADL-S. Combo phy port
clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.
The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
translates to
DDI A -> DDIA
DDI B -> USBC1
DDI I -> USBC2
For DPCLKA_CFGCR1
DDI J -> USBC3
DDI K -> USBC4
Bspec: 50287
Bspec: 53812
Bspec: 53723
v2: Replace I915_READ() with intel_de_read().(Jani)
v3:
- Use reg variable to assign ADLS specific registers inorder to replace
branching with intel_de_read/write() calls.(mdroper)
- Reuse icl_get_ddi_pll() for ADLS to fix issue with updating active
dpll on driver load.(aswarup)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 62 +++++++++++++-------
drivers/gpu/drm/i915/display/intel_display.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 23 +++++++-
3 files changed, 72 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d4c09a1aa06e..91d8e3cc0d9f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3160,25 +3160,30 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- u32 val;
+ u32 val, mask, sel;
+ i915_reg_t reg;
+
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ reg = ADLS_DPCLKA_CFGCR(phy);
+ mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
+ sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
+ } else if (IS_ROCKETLAKE(dev_priv)) {
+ reg = ICL_DPCLKA_CFGCR0;
+ mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ } else {
+ reg = ICL_DPCLKA_CFGCR0;
+ mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ }
mutex_lock(&dev_priv->dpll.lock);
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ val = intel_de_read(dev_priv, reg);
drm_WARN_ON(&dev_priv->drm,
(val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
if (intel_phy_is_combo(dev_priv, phy)) {
- u32 mask, sel;
-
- if (IS_ROCKETLAKE(dev_priv)) {
- mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
- } else {
- mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
- }
-
/*
* Even though this register references DDIs, note that we
* want to pass the PHY rather than the port (DDI). For
@@ -3191,12 +3196,12 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
*/
val &= ~mask;
val |= sel;
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
- intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ intel_de_write(dev_priv, reg, val);
+ intel_de_posting_read(dev_priv, reg);
}
val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+ intel_de_write(dev_priv, reg, val);
mutex_unlock(&dev_priv->dpll.lock);
}
@@ -3219,12 +3224,19 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
u32 val;
+ i915_reg_t reg;
mutex_lock(&dev_priv->dpll.lock);
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ if (IS_ALDERLAKE_S(dev_priv))
+ reg = ADLS_DPCLKA_CFGCR(phy);
+ else
+ reg = ICL_DPCLKA_CFGCR0;
+
+ val = intel_de_read(dev_priv, reg);
val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+
+ intel_de_write(dev_priv, reg, val);
mutex_unlock(&dev_priv->dpll.lock);
}
@@ -3264,13 +3276,21 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
u32 port_mask, bool ddi_clk_needed)
{
enum port port;
+ bool ddi_clk_off;
u32 val;
+ i915_reg_t reg;
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_port_masked(port, port_mask) {
enum phy phy = intel_port_to_phy(dev_priv, port);
- bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
- phy);
+
+ if (IS_ALDERLAKE_S(dev_priv))
+ reg = ADLS_DPCLKA_CFGCR(phy);
+ else
+ reg = ICL_DPCLKA_CFGCR0;
+
+ val = intel_de_read(dev_priv, reg);
+ ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
+ phy);
if (ddi_clk_needed == !ddi_clk_off)
continue;
@@ -3286,7 +3306,7 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
"PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
phy_name(phy));
val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+ intel_de_write(dev_priv, reg, val);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index acf06feffd3e..83ac0a7a59f0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8592,20 +8592,27 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
struct intel_shared_dpll *pll;
enum intel_dpll_id id;
bool pll_active;
+ i915_reg_t reg;
u32 temp;
if (intel_phy_is_combo(dev_priv, phy)) {
u32 mask, shift;
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ reg = ADLS_DPCLKA_CFGCR(phy);
+ mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
+ shift = ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
+ } else if (IS_ROCKETLAKE(dev_priv)) {
+ reg = ICL_DPCLKA_CFGCR0;
mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
} else {
+ reg = ICL_DPCLKA_CFGCR0;
mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
}
- temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
+ temp = intel_de_read(dev_priv, reg) & mask;
id = temp >> shift;
port_dpll_id = ICL_PORT_DPLL_DEFAULT;
} else if (intel_phy_is_tc(dev_priv, phy)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 339532222d7c..6be725a9e46f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10356,7 +10356,7 @@ enum skl_power_gate {
/* ICL Clocks */
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
(tc_port) + 12 : \
@@ -10391,6 +10391,27 @@ enum skl_power_gate {
#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \
(((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy))
+/* ADLS Clocks */
+#define _ADLS_DPCLKA_CFGCR0 0x164280
+#define _ADLS_DPCLKA_CFGCR1 0x1642BC
+#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
+ _ADLS_DPCLKA_CFGCR0, \
+ _ADLS_DPCLKA_CFGCR1)
+#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
+/* ADLS DPCLKA_CFGCR0 DDI mask */
+#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
+#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
+#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
+/* ADLS DPCLKA_CFGCR1 DDI mask */
+#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
+#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
+#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
+ ADLS_DPCLKA_DDIA_SEL_MASK, \
+ ADLS_DPCLKA_DDIB_SEL_MASK, \
+ ADLS_DPCLKA_DDII_SEL_MASK, \
+ ADLS_DPCLKA_DDIJ_SEL_MASK, \
+ ADLS_DPCLKA_DDIK_SEL_MASK)
+
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 07/10] drm/i915/adl_s: Initialize display for ADL-S
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (5 preceding siblings ...)
2021-01-25 14:07 ` [Intel-gfx] [PATCH 06/10] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
@ 2021-01-25 14:07 ` Aditya Swarup
2021-01-25 18:47 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 08/10] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
` (11 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
Initialize display outputs for ADL-S. ADL-S has 5 display
outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
v2:
- Use PORT_TCx instead of PORT_D,E.. to stay consistent
with other platforms.(mdroper)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 83ac0a7a59f0..eaec5cd1a144 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13897,7 +13897,13 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_TC1);
+ intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC3);
+ intel_ddi_init(dev_priv, PORT_TC4);
+ } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_TC1);
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 08/10] drm/i915/adl_s: Add adl-s ddc pin mapping
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (6 preceding siblings ...)
2021-01-25 14:07 ` [Intel-gfx] [PATCH 07/10] drm/i915/adl_s: Initialize display " Aditya Swarup
@ 2021-01-25 14:07 ` Aditya Swarup
2021-01-25 18:54 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 09/10] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
` (10 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
Combo PHY A still uses the old ddc pin mapping.
From VBT, ddc pin info suggests the following mapping:
VBT DRIVER
DDI B->ddc_pin=2 should translate to PORT_D->0x9
DDI C->ddc_pin=3 should translate to PORT_E->0xa
DDI D->ddc_pin=4 should translate to PORT_F->0xb
DDI E->ddc_pin=5 should translate to PORT_G->0xc
Adding pin map to facilitate this translation as we cannot use existing
icl ddc pin map due to conflict with DDI B and DDI C info.
Bspec:20124
v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing
depends on the PCH being used rather than the platform.(mdroper)
v3:
- Modify adls_port_to_ddc_pin() to make PHY_A the special case for
check, else return pin mapping based on correct arithmetic with phy
offset. Remove redundant platform checks and use HAS_PCH_ADP() instead
of IS_ALDERLAKE_S() in intel_hdmi_ddc_pin().(mdroper)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++++
3 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 987cf509337f..e575e584e6d5 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1630,12 +1630,23 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = {
[RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
};
+static const u8 adls_ddc_pin_map[] = {
+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+ [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
+ [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
+ [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
+ [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
+};
+
static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
{
const u8 *ddc_pin_map;
int n_entries;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+ if (HAS_PCH_ADP(dev_priv)) {
+ ddc_pin_map = adls_ddc_pin_map;
+ n_entries = ARRAY_SIZE(adls_ddc_pin_map);
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
return vbt_pin;
} else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index d5f4b40a8460..66e1ac3887c6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3138,6 +3138,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
return intel_port_to_phy(dev_priv, port) + 1;
}
+static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+
+ WARN_ON(port == PORT_B || port == PORT_C);
+
+ /*
+ * Pin mapping for ADL-S requires TC pins for all combo phy outputs
+ * except first combo output.
+ */
+ if (phy == PHY_A)
+ return GMBUS_PIN_1_BXT;
+
+ return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3175,7 +3191,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
return ddc_pin;
}
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ if (HAS_PCH_ADP(dev_priv))
+ ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
else if (IS_ROCKETLAKE(dev_priv))
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 187ec573de59..6d10fa037751 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -327,6 +327,10 @@ enum vbt_gmbus_ddi {
ICL_DDC_BUS_PORT_4,
TGL_DDC_BUS_PORT_5,
TGL_DDC_BUS_PORT_6,
+ ADLS_DDC_BUS_PORT_TC1 = 0x2,
+ ADLS_DDC_BUS_PORT_TC2,
+ ADLS_DDC_BUS_PORT_TC3,
+ ADLS_DDC_BUS_PORT_TC4
};
#define DP_AUX_A 0x40
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 09/10] drm/i915/adl_s: Add vbt port and aux channel settings for adls
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (7 preceding siblings ...)
2021-01-25 14:07 ` [Intel-gfx] [PATCH 08/10] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
@ 2021-01-25 14:07 ` Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 10/10] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
` (9 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.
- Add ADLS specific port mappings for vbt port dvo settings.
- Select appropriate AUX CH specific to ADLS based on port mapping.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 57 ++++++++++++++++++-----
1 file changed, 46 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index e575e584e6d5..04337ac6f8c4 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1719,8 +1719,26 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
+ /*
+ * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,
+ * PORT_F and PORT_G, we need to map that to correct VBT sections.
+ */
+ static const int adls_port_mapping[][3] = {
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+ [PORT_B] = { -1 },
+ [PORT_C] = { -1 },
+ [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+ [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+ [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
+ };
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
+ ARRAY_SIZE(adls_port_mapping[0]),
+ adls_port_mapping,
+ dvo_port);
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
ARRAY_SIZE(rkl_port_mapping[0]),
rkl_port_mapping,
@@ -2672,27 +2690,44 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
return aux_ch;
}
+ /*
+ * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
+ * map to DDI A,B,TC1,TC2 respectively.
+ *
+ * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E
+ * map to DDI A,TC1,TC2,TC3,TC4 respectively.
+ */
switch (info->alternate_aux_channel) {
case DP_AUX_A:
aux_ch = AUX_CH_A;
break;
case DP_AUX_B:
- aux_ch = AUX_CH_B;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC1;
+ else
+ aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
- /*
- * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
- * map to DDI A,B,TC1,TC2 respectively.
- */
- aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
- AUX_CH_USBC1 : AUX_CH_C;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC2;
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ aux_ch = AUX_CH_USBC1;
+ else
+ aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
- aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
- AUX_CH_USBC2 : AUX_CH_D;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC3;
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ aux_ch = AUX_CH_USBC2;
+ else
+ aux_ch = AUX_CH_D;
break;
case DP_AUX_E:
- aux_ch = AUX_CH_E;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC4;
+ else
+ aux_ch = AUX_CH_E;
break;
case DP_AUX_F:
aux_ch = AUX_CH_F;
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 10/10] drm/i915/adl_s: Update combo PHY master/slave relationships
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (8 preceding siblings ...)
2021-01-25 14:07 ` [Intel-gfx] [PATCH 09/10] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
@ 2021-01-25 14:07 ` Aditya Swarup
2021-01-25 17:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alderlake-S platform enabling patches Patchwork
` (8 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Aditya Swarup @ 2021-01-25 14:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Matt Roper <matthew.d.roper@intel.com>
ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.
Bspec: 49291
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 996ae0608a62..dd45cbafcf42 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -246,14 +246,21 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
* RKL,DG1:
* A(master) -> B(slave)
* C(master) -> D(slave)
+ * ADL-S:
+ * A(master) -> B(slave), C(slave)
+ * D(master) -> E(slave)
*
* We must set the IREFGEN bit for any PHY acting as a master
* to another PHY.
*/
- if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
+ if (phy == PHY_A)
return true;
+ else if (IS_ALDERLAKE_S(dev_priv))
+ return phy == PHY_D;
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ return phy == PHY_C;
- return phy == PHY_A;
+ return false;
}
static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 02/10] drm/i915/adl_s: Add PCH support
2021-01-25 14:07 ` [Intel-gfx] [PATCH 02/10] drm/i915/adl_s: Add PCH support Aditya Swarup
@ 2021-01-25 17:39 ` Lucas De Marchi
0 siblings, 0 replies; 27+ messages in thread
From: Lucas De Marchi @ 2021-01-25 17:39 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx
On Mon, Jan 25, 2021 at 06:07:45AM -0800, Aditya Swarup wrote:
>From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
>Add support for Alderpoint(ADP) PCH used with Alderlake-S.
>
>v2:
>- Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup)
>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Caz Yokoyama <caz.yokoyama@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/intel_pch.c | 8 +++++++-
> drivers/gpu/drm/i915/intel_pch.h | 3 +++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
>index ecaf314d60b6..4813207fc053 100644
>--- a/drivers/gpu/drm/i915/intel_pch.c
>+++ b/drivers/gpu/drm/i915/intel_pch.c
>@@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
> drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
> drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
> return PCH_JSP;
>+ case INTEL_PCH_ADP_DEVICE_ID_TYPE:
>+ drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
>+ drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv));
>+ return PCH_ADP;
> default:
> return PCH_NONE;
> }
>@@ -156,7 +160,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
> * make an educated guess as to which PCH is really there.
> */
>
>- if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
>+ if (IS_ALDERLAKE_S(dev_priv))
>+ id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
>+ else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
> id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
> else if (IS_JSL_EHL(dev_priv))
> id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
>diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
>index 06d2cd50af0b..7318377503b0 100644
>--- a/drivers/gpu/drm/i915/intel_pch.h
>+++ b/drivers/gpu/drm/i915/intel_pch.h
>@@ -26,6 +26,7 @@ enum intel_pch {
> PCH_JSP, /* Jasper Lake PCH */
> PCH_MCC, /* Mule Creek Canyon PCH */
> PCH_TGP, /* Tiger Lake PCH */
>+ PCH_ADP, /* Alder Lake PCH */
>
> /* Fake PCHs, functionality handled on the same PCI dev */
> PCH_DG1 = 1024,
>@@ -53,12 +54,14 @@ enum intel_pch {
> #define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380
> #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
> #define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
>+#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
> #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
>
> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
>+#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
> #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
> #define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
> #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
>--
>2.27.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alderlake-S platform enabling patches
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (9 preceding siblings ...)
2021-01-25 14:07 ` [Intel-gfx] [PATCH 10/10] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
@ 2021-01-25 17:42 ` Patchwork
2021-01-25 17:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (7 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-25 17:42 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: Alderlake-S platform enabling patches
URL : https://patchwork.freedesktop.org/series/86260/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7d5293a71979 x86/gpu: Add Alderlake-S stolen memory support
9c6ff305711e drm/i915/adl_s: Add PCH support
5f6060c32665 drm/i915/adl_s: Add Interrupt Support
cc0c6ffe9192 drm/i915/adl_s: Add PHYs for Alderlake S
ed39c7a3e949 drm/i915/adl_s: Configure DPLL for ADL-S
bc2af1bd65e7 drm/i915/adl_s: Configure Port clock registers for ADL-S
ffa1c9a2e683 drm/i915/adl_s: Initialize display for ADL-S
d1dd456e53b6 drm/i915/adl_s: Add adl-s ddc pin mapping
7a27ec2a8473 drm/i915/adl_s: Add vbt port and aux channel settings for adls
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10:
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.
total: 0 errors, 1 warnings, 0 checks, 81 lines checked
e081829e52d7 drm/i915/adl_s: Update combo PHY master/slave relationships
_______________________________________________
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Alderlake-S platform enabling patches
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (10 preceding siblings ...)
2021-01-25 17:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alderlake-S platform enabling patches Patchwork
@ 2021-01-25 17:43 ` Patchwork
2021-01-25 18:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (6 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-25 17:43 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: Alderlake-S platform enabling patches
URL : https://patchwork.freedesktop.org/series/86260/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1327:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 03/10] drm/i915/adl_s: Add Interrupt Support
2021-01-25 14:07 ` [Intel-gfx] [PATCH 03/10] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
@ 2021-01-25 17:46 ` Lucas De Marchi
0 siblings, 0 replies; 27+ messages in thread
From: Lucas De Marchi @ 2021-01-25 17:46 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx
On Mon, Jan 25, 2021 at 06:07:46AM -0800, Aditya Swarup wrote:
>From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
>ADLS follows ICP/TGP like interrupts.
>
>v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas)
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Cc: José Roberto de Souza <jose.souza@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
I think the commit message is a little too short... this is only adding
the hpd pins, but apparently it's the only thing needed to differentiate
irq-wise.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/i915_irq.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 33019cf0e630..6568e7e9fe2a 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -209,8 +209,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>
> if (HAS_PCH_DG1(dev_priv))
> hpd->pch_hpd = hpd_sde_dg1;
>- else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
>- HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> hpd->pch_hpd = hpd_icp;
> else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
> hpd->pch_hpd = hpd_spt;
>--
>2.27.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 04/10] drm/i915/adl_s: Add PHYs for Alderlake S
2021-01-25 14:07 ` [Intel-gfx] [PATCH 04/10] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
@ 2021-01-25 17:51 ` Lucas De Marchi
0 siblings, 0 replies; 27+ messages in thread
From: Lucas De Marchi @ 2021-01-25 17:51 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx
On Mon, Jan 25, 2021 at 06:07:47AM -0800, Aditya Swarup wrote:
>From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
>Alderlake-S has 5 combo phys, add reg definitions for
>combo phys and update the port to phy helper for ADL-S.
>
>v2:
>- Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc()
>and return false for platforms RKL,DG1 and ADLS.(mdroper)
changelog here is missing v3: fix intel_phy_is_tc breakage for DG1
but only for completeness... I remembered there was an issue in this
patch but I was not finding what it was and went to check. This one lgtm
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++-----
> drivers/gpu/drm/i915/i915_reg.h | 5 ++++-
> 2 files changed, 11 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 7ec7d94b8cdb..acf06feffd3e 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -5668,6 +5668,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
> {
> if (phy == PHY_NONE)
> return false;
>+ else if (IS_ALDERLAKE_S(dev_priv))
>+ return phy <= PHY_E;
> else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> return phy <= PHY_D;
> else if (IS_JSL_EHL(dev_priv))
>@@ -5680,11 +5682,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>
> bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> {
>- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
>- return false;
>- else if (INTEL_GEN(dev_priv) >= 12)
>+ if (IS_TIGERLAKE(dev_priv))
> return phy >= PHY_D && phy <= PHY_I;
>- else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
>+ else if (IS_ICELAKE(dev_priv))
> return phy >= PHY_C && phy <= PHY_F;
> else
> return false;
>@@ -5692,7 +5692,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>
> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> {
>- if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
>+ if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
>+ return PHY_B + port - PORT_TC1;
>+ else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
> return PHY_C + port - PORT_TC1;
> else if (IS_JSL_EHL(i915) && port == PORT_D)
> return PHY_A;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 8b9bbc6bacb1..0fe499840b82 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -1874,10 +1874,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _ICL_COMBOPHY_B 0x6C000
> #define _EHL_COMBOPHY_C 0x160000
> #define _RKL_COMBOPHY_D 0x161000
>+#define _ADL_COMBOPHY_E 0x16B000
>+
> #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
> _ICL_COMBOPHY_B, \
> _EHL_COMBOPHY_C, \
>- _RKL_COMBOPHY_D)
>+ _RKL_COMBOPHY_D, \
>+ _ADL_COMBOPHY_E)
>
> /* CNL/ICL Port CL_DW registers */
> #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
>--
>2.27.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Alderlake-S platform enabling patches
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (11 preceding siblings ...)
2021-01-25 17:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-01-25 18:13 ` Patchwork
2021-01-25 23:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (5 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-25 18:13 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2981 bytes --]
== Series Details ==
Series: Alderlake-S platform enabling patches
URL : https://patchwork.freedesktop.org/series/86260/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9680 -> Patchwork_19488
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/index.html
Known issues
------------
Here are the changes found in Patchwork_19488 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#2411] / [i915#402])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
* igt@gem_sync@basic-each:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/fi-tgl-y/igt@gem_sync@basic-each.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/fi-tgl-y/igt@gem_sync@basic-each.html
#### Possible fixes ####
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (39 -> 35)
------------------------------
Missing (4): fi-ctg-p8600 fi-jsl-1 fi-ilk-m540 fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9680 -> Patchwork_19488
CI-20190529: 20190529
CI_DRM_9680: 9e03236ed9687144929d42404341384cc1e501b7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5971: abef2b7d6ff30f3b948b3e5d39653debb73083f3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19488: e081829e52d7d775cfbb5645d807aeaa13ba3756 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e081829e52d7 drm/i915/adl_s: Update combo PHY master/slave relationships
7a27ec2a8473 drm/i915/adl_s: Add vbt port and aux channel settings for adls
d1dd456e53b6 drm/i915/adl_s: Add adl-s ddc pin mapping
ffa1c9a2e683 drm/i915/adl_s: Initialize display for ADL-S
bc2af1bd65e7 drm/i915/adl_s: Configure Port clock registers for ADL-S
ed39c7a3e949 drm/i915/adl_s: Configure DPLL for ADL-S
cc0c6ffe9192 drm/i915/adl_s: Add PHYs for Alderlake S
5f6060c32665 drm/i915/adl_s: Add Interrupt Support
9c6ff305711e drm/i915/adl_s: Add PCH support
7d5293a71979 x86/gpu: Add Alderlake-S stolen memory support
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/index.html
[-- Attachment #1.2: Type: text/html, Size: 3823 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 05/10] drm/i915/adl_s: Configure DPLL for ADL-S
2021-01-25 14:07 ` [Intel-gfx] [PATCH 05/10] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
@ 2021-01-25 18:45 ` Lucas De Marchi
0 siblings, 0 replies; 27+ messages in thread
From: Lucas De Marchi @ 2021-01-25 18:45 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx
On Mon, Jan 25, 2021 at 06:07:48AM -0800, Aditya Swarup wrote:
>Add changes for configuring DPLL for ADL-S
>- Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
>- Extend CNL macro to choose DPLL_ENABLE
> for ADL-S.
>- Select CFGCR0 and CFGCR1 for ADL-S plls.
>
>On BSpec: 53720 PLL arrangement dig for adls:
>DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
>DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1)
>
>v2 (Lucas): add missing update_ref_clks
>
>Bspec: 50288
>Bspec: 50289
>Bspec: 49443
>
>v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield
>for DPLL3_USED.(mdroper)
>
>Bspec: 53707
>
>v4: BSpec 53723 has been updated with note - DPLL2 is
>controlled by DPLL4 CFGCR 0/1.(mdroper)
>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++-
> 2 files changed, 54 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>index f6ad257a260e..529b1d569af2 100644
>--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>@@ -3559,7 +3559,13 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>
> icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>
>- if (IS_DG1(dev_priv)) {
>+ if (IS_ALDERLAKE_S(dev_priv)) {
>+ dpll_mask =
>+ BIT(DPLL_ID_DG1_DPLL3) |
>+ BIT(DPLL_ID_DG1_DPLL2) |
>+ BIT(DPLL_ID_ICL_DPLL1) |
>+ BIT(DPLL_ID_ICL_DPLL0);
I think mixing the namespace when it's not just an extension to the
other platform, it's a bit confusing. Why not DPLL_ID_DG1_* or even
creating your own DPLL_ID_ADLS_*.
Anyway, this seems a minor thing to block the patch. The rest looks ok.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>+ } else if (IS_DG1(dev_priv)) {
> if (port == PORT_D || port == PORT_E) {
> dpll_mask =
> BIT(DPLL_ID_DG1_DPLL2) |
>@@ -3865,7 +3871,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> if (!(val & PLL_ENABLE))
> goto out;
>
>- if (IS_DG1(dev_priv)) {
>+ if (IS_ALDERLAKE_S(dev_priv)) {
>+ hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id));
>+ hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id));
>+ } else if (IS_DG1(dev_priv)) {
> hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
> hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
> } else if (IS_ROCKETLAKE(dev_priv)) {
>@@ -3921,7 +3930,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
> const enum intel_dpll_id id = pll->info->id;
> i915_reg_t cfgcr0_reg, cfgcr1_reg;
>
>- if (IS_DG1(dev_priv)) {
>+ if (IS_ALDERLAKE_S(dev_priv)) {
>+ cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
>+ cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
>+ } else if (IS_DG1(dev_priv)) {
> cfgcr0_reg = DG1_DPLL_CFGCR0(id);
> cfgcr1_reg = DG1_DPLL_CFGCR1(id);
> } else if (IS_ROCKETLAKE(dev_priv)) {
>@@ -4384,6 +4396,22 @@ static const struct intel_dpll_mgr dg1_pll_mgr = {
> .dump_hw_state = icl_dump_hw_state,
> };
>
>+static const struct dpll_info adls_plls[] = {
>+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
>+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
>+ { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
>+ { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
>+ { },
>+};
>+
>+static const struct intel_dpll_mgr adls_pll_mgr = {
>+ .dpll_info = adls_plls,
>+ .get_dplls = icl_get_dplls,
>+ .put_dplls = icl_put_dplls,
>+ .update_ref_clks = icl_update_dpll_ref_clks,
>+ .dump_hw_state = icl_dump_hw_state,
>+};
>+
> /**
> * intel_shared_dpll_init - Initialize shared DPLLs
> * @dev: drm device
>@@ -4397,7 +4425,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
> const struct dpll_info *dpll_info;
> int i;
>
>- if (IS_DG1(dev_priv))
>+ if (IS_ALDERLAKE_S(dev_priv))
>+ dpll_mgr = &adls_pll_mgr;
>+ else if (IS_DG1(dev_priv))
> dpll_mgr = &dg1_pll_mgr;
> else if (IS_ROCKETLAKE(dev_priv))
> dpll_mgr = &rkl_pll_mgr;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 0fe499840b82..339532222d7c 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2930,7 +2930,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
>
> #define HDPORT_STATE _MMIO(0x45050)
>-#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
>+#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
> #define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
> #define HDPORT_ENABLED REG_BIT(0)
>
>@@ -10394,11 +10394,14 @@ enum skl_power_gate {
> /* CNL PLL */
> #define DPLL0_ENABLE 0x46010
> #define DPLL1_ENABLE 0x46014
>+#define _ADLS_DPLL2_ENABLE 0x46018
>+#define _ADLS_DPLL3_ENABLE 0x46030
> #define PLL_ENABLE (1 << 31)
> #define PLL_LOCK (1 << 30)
> #define PLL_POWER_ENABLE (1 << 27)
> #define PLL_POWER_STATE (1 << 26)
>-#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
>+#define CNL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
>+ _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
>
> #define TBT_PLL_ENABLE _MMIO(0x46020)
>
>@@ -10644,6 +10647,21 @@ enum skl_power_gate {
> _DG1_DPLL2_CFGCR1, \
> _DG1_DPLL3_CFGCR1)
>
>+/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
>+#define _ADLS_DPLL3_CFGCR0 0x1642C0
>+#define _ADLS_DPLL4_CFGCR0 0x164294
>+#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
>+ _TGL_DPLL1_CFGCR0, \
>+ _ADLS_DPLL4_CFGCR0, \
>+ _ADLS_DPLL3_CFGCR0)
>+
>+#define _ADLS_DPLL3_CFGCR1 0x1642C4
>+#define _ADLS_DPLL4_CFGCR1 0x164298
>+#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
>+ _TGL_DPLL1_CFGCR1, \
>+ _ADLS_DPLL4_CFGCR1, \
>+ _ADLS_DPLL3_CFGCR1)
>+
> #define _DKL_PHY1_BASE 0x168000
> #define _DKL_PHY2_BASE 0x169000
> #define _DKL_PHY3_BASE 0x16A000
>--
>2.27.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 07/10] drm/i915/adl_s: Initialize display for ADL-S
2021-01-25 14:07 ` [Intel-gfx] [PATCH 07/10] drm/i915/adl_s: Initialize display " Aditya Swarup
@ 2021-01-25 18:47 ` Lucas De Marchi
0 siblings, 0 replies; 27+ messages in thread
From: Lucas De Marchi @ 2021-01-25 18:47 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx
On Mon, Jan 25, 2021 at 06:07:50AM -0800, Aditya Swarup wrote:
>Initialize display outputs for ADL-S. ADL-S has 5 display
>outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
>
>v2:
>- Use PORT_TCx instead of PORT_D,E.. to stay consistent
> with other platforms.(mdroper)
>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 83ac0a7a59f0..eaec5cd1a144 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -13897,7 +13897,13 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
>- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
>+ if (IS_ALDERLAKE_S(dev_priv)) {
>+ intel_ddi_init(dev_priv, PORT_A);
>+ intel_ddi_init(dev_priv, PORT_TC1);
>+ intel_ddi_init(dev_priv, PORT_TC2);
>+ intel_ddi_init(dev_priv, PORT_TC3);
>+ intel_ddi_init(dev_priv, PORT_TC4);
>+ } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_TC1);
>--
>2.27.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 08/10] drm/i915/adl_s: Add adl-s ddc pin mapping
2021-01-25 14:07 ` [Intel-gfx] [PATCH 08/10] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
@ 2021-01-25 18:54 ` Lucas De Marchi
0 siblings, 0 replies; 27+ messages in thread
From: Lucas De Marchi @ 2021-01-25 18:54 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx
On Mon, Jan 25, 2021 at 06:07:51AM -0800, Aditya Swarup wrote:
>ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
>Combo PHY A still uses the old ddc pin mapping.
>
>From VBT, ddc pin info suggests the following mapping:
>VBT DRIVER
>DDI B->ddc_pin=2 should translate to PORT_D->0x9
>DDI C->ddc_pin=3 should translate to PORT_E->0xa
>DDI D->ddc_pin=4 should translate to PORT_F->0xb
>DDI E->ddc_pin=5 should translate to PORT_G->0xc
>
>Adding pin map to facilitate this translation as we cannot use existing
>icl ddc pin map due to conflict with DDI B and DDI C info.
>
>Bspec:20124
>
>v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing
>depends on the PCH being used rather than the platform.(mdroper)
>
>v3:
>- Modify adls_port_to_ddc_pin() to make PHY_A the special case for
> check, else return pin mapping based on correct arithmetic with phy
> offset. Remove redundant platform checks and use HAS_PCH_ADP() instead
> of IS_ALDERLAKE_S() in intel_hdmi_ddc_pin().(mdroper)
>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++++
> 3 files changed, 35 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>index 987cf509337f..e575e584e6d5 100644
>--- a/drivers/gpu/drm/i915/display/intel_bios.c
>+++ b/drivers/gpu/drm/i915/display/intel_bios.c
>@@ -1630,12 +1630,23 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = {
> [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
> };
>
>+static const u8 adls_ddc_pin_map[] = {
>+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
>+ [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
>+ [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
>+ [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
>+ [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
>+};
>+
> static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> {
> const u8 *ddc_pin_map;
> int n_entries;
>
>- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
>+ if (HAS_PCH_ADP(dev_priv)) {
>+ ddc_pin_map = adls_ddc_pin_map;
>+ n_entries = ARRAY_SIZE(adls_ddc_pin_map);
>+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
> return vbt_pin;
> } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
> ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
>diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
>index d5f4b40a8460..66e1ac3887c6 100644
>--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
>+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
>@@ -3138,6 +3138,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
> return intel_port_to_phy(dev_priv, port) + 1;
> }
>
>+static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
>+{
>+ enum phy phy = intel_port_to_phy(dev_priv, port);
>+
>+ WARN_ON(port == PORT_B || port == PORT_C);
>+
>+ /*
>+ * Pin mapping for ADL-S requires TC pins for all combo phy outputs
>+ * except first combo output.
>+ */
>+ if (phy == PHY_A)
>+ return GMBUS_PIN_1_BXT;
>+
>+ return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
>+}
>+
> static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
> enum port port)
> {
>@@ -3175,7 +3191,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
> return ddc_pin;
> }
>
>- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>+ if (HAS_PCH_ADP(dev_priv))
>+ ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
>+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
> else if (IS_ROCKETLAKE(dev_priv))
> ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
>diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>index 187ec573de59..6d10fa037751 100644
>--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>@@ -327,6 +327,10 @@ enum vbt_gmbus_ddi {
> ICL_DDC_BUS_PORT_4,
> TGL_DDC_BUS_PORT_5,
> TGL_DDC_BUS_PORT_6,
>+ ADLS_DDC_BUS_PORT_TC1 = 0x2,
>+ ADLS_DDC_BUS_PORT_TC2,
>+ ADLS_DDC_BUS_PORT_TC3,
>+ ADLS_DDC_BUS_PORT_TC4
> };
>
> #define DP_AUX_A 0x40
>--
>2.27.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Alderlake-S platform enabling patches
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (12 preceding siblings ...)
2021-01-25 18:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-01-25 23:26 ` Patchwork
2021-01-26 0:05 ` Aditya Swarup
2021-01-26 3:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alderlake-S platform enabling patches (rev2) Patchwork
` (4 subsequent siblings)
18 siblings, 1 reply; 27+ messages in thread
From: Patchwork @ 2021-01-25 23:26 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30259 bytes --]
== Series Details ==
Series: Alderlake-S platform enabling patches
URL : https://patchwork.freedesktop.org/series/86260/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9680_full -> Patchwork_19488_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19488_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19488_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19488_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@absolute-wf_vblank-interruptible@b-edp1:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/shard-tglb2/igt@kms_flip@absolute-wf_vblank-interruptible@b-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/shard-tglb6/igt@kms_flip@absolute-wf_vblank-interruptible@b-edp1.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_persistence@many-contexts}:
- shard-tglb: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/shard-tglb3/igt@gem_ctx_persistence@many-contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/shard-tglb1/igt@gem_ctx_persistence@many-contexts.html
* {igt@sysfs_clients@busy@bcs0}:
- shard-kbl: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/shard-kbl1/igt@sysfs_clients@busy@bcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/shard-kbl3/igt@sysfs_clients@busy@bcs0.html
New tests
---------
New tests have been introduced between CI_DRM_9680_full and Patchwork_19488_full:
### New IGT tests (1749) ###
* igt@core_auth@many-magics:
- Statuses : 6 pass(s)
- Exec time: [0.15, 0.87] s
* igt@core_getclient:
- Statuses : 7 pass(s)
- Exec time: [0.07, 0.18] s
* igt@core_getstats:
- Statuses : 6 pass(s)
- Exec time: [0.07, 0.25] s
* igt@core_getversion:
- Statuses : 7 pass(s)
- Exec time: [0.07, 0.17] s
* igt@core_setmaster_vs_auth:
- Statuses : 7 pass(s)
- Exec time: [0.07, 0.21] s
* igt@debugfs_test@read_all_entries_display_off:
- Statuses : 6 pass(s)
- Exec time: [0.07, 1.16] s
* igt@debugfs_test@read_all_entries_display_on:
- Statuses :
- Exec time: [None] s
* igt@drm_import_export@flink:
- Statuses : 7 pass(s)
- Exec time: [10.74, 10.75] s
* igt@drm_import_export@import-close-race-flink:
- Statuses : 7 pass(s)
- Exec time: [10.74, 10.76] s
* igt@drm_import_export@import-close-race-prime:
- Statuses : 7 pass(s)
- Exec time: [10.74] s
* igt@drm_import_export@prime:
- Statuses : 7 pass(s)
- Exec time: [10.74, 10.75] s
* igt@drm_read@empty-block:
- Statuses : 2 pass(s)
- Exec time: [1.0] s
* igt@drm_read@empty-nonblock:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@drm_read@fault-buffer:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@drm_read@invalid-buffer:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@drm_read@short-buffer-block:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@drm_read@short-buffer-nonblock:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@dumb_buffer@create-clear:
- Statuses : 7 pass(s)
- Exec time: [37.35, 48.34] s
* igt@dumb_buffer@create-valid-dumb:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@dumb_buffer@invalid-bpp:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@dumb_buffer@map-invalid-size:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@dumb_buffer@map-uaf:
- Statuses : 7 pass(s)
- Exec time: [0.02, 0.10] s
* igt@dumb_buffer@map-valid:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_bad_reloc@negative-reloc-bltcopy:
- Statuses : 7 pass(s)
- Exec time: [0.35, 4.13] s
* igt@gem_blits@basic:
- Statuses : 7 pass(s)
- Exec time: [1.43, 14.05] s
* igt@gem_busy@close-race:
- Statuses : 5 pass(s)
- Exec time: [21.73, 22.33] s
* igt@gem_caching@read-writes:
- Statuses : 7 pass(s)
- Exec time: [4.43, 23.0] s
* igt@gem_caching@reads:
- Statuses : 6 pass(s)
- Exec time: [0.66, 5.85] s
* igt@gem_caching@writes:
- Statuses : 7 pass(s)
- Exec time: [2.29, 13.28] s
* igt@gem_close@basic:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_close@many-handles-one-vma:
- Statuses : 7 pass(s)
- Exec time: [0.02, 0.10] s
* igt@gem_create@create-invalid-size:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_create@create-valid-nonaligned:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_bad_destroy@double-destroy:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_ctx_bad_destroy@invalid-ctx:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_bad_destroy@invalid-default-ctx:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_bad_destroy@invalid-pad:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_ctx_exec@basic-invalid-context:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_ctx_freq@sysfs:
- Statuses : 7 pass(s)
- Exec time: [4.81, 4.94] s
* igt@gem_ctx_param@basic:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@basic-default:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@get-priority-new-ctx:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.00] s
* igt@gem_ctx_param@invalid-ctx-get:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@invalid-ctx-set:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@invalid-param-get:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@invalid-param-set:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@invalid-size-get:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@invalid-size-set:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@non-root-set:
- Statuses : 6 pass(s)
- Exec time: [0.01, 0.04] s
* igt@gem_ctx_param@non-root-set-no-zeromap:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.04] s
* igt@gem_ctx_param@root-set:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@root-set-no-zeromap-disabled:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_ctx_param@root-set-no-zeromap-enabled:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@set-priority-invalid-size:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@set-priority-not-supported:
- Statuses : 2 pass(s) 5 skip(s)
- Exec time: [0.0] s
* igt@gem_ctx_param@set-priority-range:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.06] s
* igt@gem_eio@banned:
- Statuses : 7 pass(s)
- Exec time: [0.05, 0.42] s
* igt@gem_eio@execbuf:
- Statuses : 7 pass(s)
- Exec time: [0.02, 0.07] s
* igt@gem_eio@hibernate:
- Statuses : 7 pass(s)
- Exec time: [12.63, 15.24] s
* igt@gem_eio@in-flight-10ms:
- Statuses : 7 pass(s)
- Exec time: [0.45, 2.37] s
* igt@gem_eio@in-flight-1us:
- Statuses : 7 pass(s)
- Exec time: [0.37, 2.36] s
* igt@gem_eio@in-flight-contexts-10ms:
- Statuses : 7 pass(s)
- Exec time: [1.24, 36.49] s
* igt@gem_eio@in-flight-contexts-1us:
- Statuses : 7 pass(s)
- Exec time: [1.07, 36.60] s
* igt@gem_eio@in-flight-contexts-immediate:
- Statuses : 6 pass(s)
- Exec time: [2.36, 36.54] s
* igt@gem_eio@in-flight-external:
- Statuses : 7 pass(s)
- Exec time: [0.03, 0.24] s
* igt@gem_eio@in-flight-immediate:
- Statuses : 7 pass(s)
- Exec time: [0.40, 2.18] s
* igt@gem_eio@in-flight-internal-10ms:
- Statuses : 7 pass(s)
- Exec time: [0.04, 0.28] s
* igt@gem_eio@in-flight-internal-1us:
- Statuses : 7 pass(s)
- Exec time: [0.03, 0.27] s
* igt@gem_eio@in-flight-internal-immediate:
- Statuses : 7 pass(s)
- Exec time: [0.03, 0.26] s
* igt@gem_eio@in-flight-suspend:
- Statuses : 7 pass(s)
- Exec time: [0.98, 2.43] s
* igt@gem_eio@reset-stress:
- Statuses : 7 pass(s)
- Exec time: [28.52, 39.12] s
* igt@gem_eio@suspend:
- Statuses : 7 pass(s)
- Exec time: [10.97, 12.60] s
* igt@gem_eio@throttle:
- Statuses : 7 pass(s)
- Exec time: [0.02, 0.09] s
* igt@gem_eio@unwedge-stress:
- Statuses : 7 pass(s)
- Exec time: [28.41, 40.02] s
* igt@gem_eio@wait-10ms:
- Statuses : 7 pass(s)
- Exec time: [0.03, 0.15] s
* igt@gem_eio@wait-1us:
- Statuses : 7 pass(s)
- Exec time: [0.03, 0.15] s
* igt@gem_eio@wait-immediate:
- Statuses : 6 pass(s)
- Exec time: [0.02, 0.14] s
* igt@gem_eio@wait-wedge-10ms:
- Statuses : 7 pass(s)
- Exec time: [0.04, 0.27] s
* igt@gem_eio@wait-wedge-1us:
- Statuses : 7 pass(s)
- Exec time: [0.03, 0.27] s
* igt@gem_eio@wait-wedge-immediate:
- Statuses : 7 pass(s)
- Exec time: [0.04, 0.25] s
* igt@gem_exec_alignment@single:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_await@wide-all:
- Statuses : 7 pass(s)
- Exec time: [21.80, 22.50] s
* igt@gem_exec_await@wide-contexts:
- Statuses : 6 pass(s)
- Exec time: [21.61, 22.31] s
* igt@gem_exec_balancer@bonded-chain:
- Statuses : 4 pass(s) 2 skip(s)
- Exec time: [0.0, 7.20] s
* igt@gem_exec_balancer@bonded-semaphore:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 4.50] s
* igt@gem_exec_balancer@hang:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 4.59] s
* igt@gem_exec_capture@userptr:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.05] s
* igt@gem_exec_create@forked:
- Statuses : 5 pass(s)
- Exec time: [20.06, 20.14] s
* igt@gem_exec_create@madvise:
- Statuses : 7 pass(s)
- Exec time: [20.04, 20.08] s
* igt@gem_exec_fence@basic-busy-all:
- Statuses : 6 pass(s)
- Exec time: [0.01, 0.03] s
* igt@gem_exec_fence@basic-wait-all:
- Statuses : 6 pass(s)
- Exec time: [0.01, 0.03] s
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- Statuses : 4 pass(s) 3 skip(s)
- Exec time: [0.0, 6.07] s
* igt@gem_exec_flush@basic-batch-kernel-default-uc:
- Statuses : 6 pass(s)
- Exec time: [5.64, 6.04] s
* igt@gem_exec_flush@basic-batch-kernel-default-wb:
- Statuses : 7 pass(s)
- Exec time: [5.62, 6.07] s
* igt@gem_exec_flush@basic-uc-pro-default:
- Statuses : 2 pass(s)
- Exec time: [5.42, 5.43] s
* igt@gem_exec_flush@basic-uc-prw-default:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_flush@basic-uc-ro-default:
- Statuses : 7 pass(s)
- Exec time: [5.40, 5.46] s
* igt@gem_exec_flush@basic-uc-rw-default:
- Statuses : 6 pass(s)
- Exec time: [5.42, 5.47] s
* igt@gem_exec_flush@basic-uc-set-default:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.47] s
* igt@gem_exec_flush@basic-wb-pro-default:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.47] s
* igt@gem_exec_flush@basic-wb-prw-default:
- Statuses : 6 pass(s)
- Exec time: [5.41, 5.48] s
* igt@gem_exec_flush@basic-wb-ro-before-default:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.46] s
* igt@gem_exec_flush@basic-wb-ro-default:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.48] s
* igt@gem_exec_flush@basic-wb-rw-before-default:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.46] s
* igt@gem_exec_flush@basic-wb-rw-default:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.48] s
* igt@gem_exec_flush@basic-wb-set-default:
- Statuses : 7 pass(s)
- Exec time: [5.41, 5.47] s
* igt@gem_exec_nop@basic-parallel:
- Statuses : 7 pass(s)
- Exec time: [2.78, 3.33] s
* igt@gem_exec_nop@basic-sequential:
- Statuses : 6 pass(s)
- Exec time: [2.77, 3.35] s
* igt@gem_exec_nop@basic-series:
- Statuses : 7 pass(s)
- Exec time: [2.75, 3.29] s
* igt@gem_exec_parallel@basic:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_parallel@contexts:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_parallel@fds:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_params@batch-first:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_params@cliprects-invalid:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_params@cliprects_ptr-dirt:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_params@dr1-dirt:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@dr4-dirt:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@invalid-bsd-ring:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@invalid-bsd1-flag-on-blt:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@invalid-bsd1-flag-on-render:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_params@invalid-bsd1-flag-on-vebox:
- Statuses : 6 pass(s) 1 skip(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@invalid-bsd2-flag-on-blt:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@invalid-bsd2-flag-on-render:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@invalid-bsd2-flag-on-vebox:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_params@invalid-fence-in:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@invalid-flag:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@invalid-ring:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@invalid-ring2:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@no-blt:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_params@no-bsd:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_params@no-vebox:
- Statuses : 1 pass(s) 4 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_params@rel-constants-invalid:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_params@rel-constants-invalid-rel-gen5:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_params@rel-constants-invalid-ring:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_params@rs-invalid:
- Statuses : 6 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_params@rsvd2-dirt:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_params@secure-non-master:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_params@secure-non-root:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_params@sol-reset-invalid:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_params@sol-reset-not-gen7:
- Statuses : 6 pass(s) 1 skip(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_reloc@basic-active:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_reloc@basic-cpu:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.03] s
* igt@gem_exec_reloc@basic-cpu-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.17] s
* igt@gem_exec_reloc@basic-cpu-gtt:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_reloc@basic-cpu-gtt-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
- Statuses : 6 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_reloc@basic-cpu-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_reloc@basic-cpu-read:
- Statuses : 5 pass(s)
- Exec time: [0.00, 0.03] s
* igt@gem_exec_reloc@basic-cpu-read-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-cpu-read-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_reloc@basic-cpu-wc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.03] s
* igt@gem_exec_reloc@basic-cpu-wc-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-cpu-wc-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-gtt:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-gtt-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.18] s
* igt@gem_exec_reloc@basic-gtt-cpu:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-gtt-cpu-active:
- Statuses : 6 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-gtt-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_reloc@basic-gtt-read:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-gtt-read-active:
- Statuses : 6 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-gtt-read-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-gtt-wc:
- Statuses : 6 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-gtt-wc-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-gtt-wc-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-range:
- Statuses : 6 pass(s)
- Exec time: [0.01, 0.11] s
* igt@gem_exec_reloc@basic-range-active:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.16] s
* igt@gem_exec_reloc@basic-softpin:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_reloc@basic-wc:
- Statuses : 5 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-wc-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-wc-cpu:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.03] s
* igt@gem_exec_reloc@basic-wc-cpu-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.17] s
* igt@gem_exec_reloc@basic-wc-cpu-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_reloc@basic-wc-gtt:
- Statuses : 6 pass(s)
- Exec time: [0.00, 0.03] s
* igt@gem_exec_reloc@basic-wc-gtt-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.17] s
* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-wc-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-wc-read:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.03] s
* igt@gem_exec_reloc@basic-wc-read-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-wc-read-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_reloc@basic-write-cpu:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-write-cpu-active:
- Statuses : 5 pass(s)
- Exec time: [0.11, 0.17] s
* igt@gem_exec_reloc@basic-write-cpu-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_reloc@basic-write-gtt:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-write-gtt-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-write-gtt-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.02] s
* igt@gem_exec_reloc@basic-write-read:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-write-read-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-write-read-noreloc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_reloc@basic-write-wc:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_exec_reloc@basic-write-wc-active:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.16] s
* igt@gem_exec_reloc@basic-write-wc-noreloc:
- Statuses : 6 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_exec_schedule@smoketest-all:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 32.30] s
* igt@gem_exec_suspend@basic:
- Statuses : 7 pass(s)
- Exec time: [0.18, 1.50] s
* igt@gem_exec_suspend@basic-s3-devices:
- Statuses : 7 pass(s)
- Exec time: [6.42, 11.25] s
* igt@gem_exec_suspend@basic-s4-devices:
- Statuses : 7 pass(s)
- Exec time: [7.13, 11.87] s
* igt@gem_fence_thrash@bo-copy:
- Statuses : 7 pass(s)
- Exec time: [1.13, 1.72] s
* igt@gem_fence_thrash@bo-write-verify-none:
- Statuses : 7 pass(s)
- Exec time: [1.11, 1.23] s
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- Statuses : 7 pass(s)
- Exec time: [1.21, 3.19] s
* igt@gem_fence_thrash@bo-write-verify-threaded-x:
- Statuses :
- Exec time: [None] s
* igt@gem_fence_thrash@bo-write-verify-threaded-y:
- Statuses :
- Exec time: [None] s
* igt@gem_fence_thrash@bo-write-verify-x:
- Statuses : 7 pass(s)
- Exec time: [1.09, 1.30] s
* igt@gem_fence_thrash@bo-write-verify-y:
- Statuses : 7 pass(s)
- Exec time: [1.11, 1.33] s
* igt@gem_fenced_exec_thrash@2-spare-fences:
- Statuses : 7 pass(s)
- Exec time: [2.15, 2.17] s
* igt@gem_fenced_exec_thrash@no-spare-fences:
- Statuses : 7 pass(s)
- Exec time: [2.15, 2.17] s
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- Statuses : 7 pass(s)
- Exec time: [2.16, 2.19] s
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- Statuses : 7 pass(s)
- Exec time: [2.15, 2.18] s
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- Statuses : 7 pass(s)
- Exec time: [2.15, 2.18] s
* igt@gem_fenced_exec_thrash@too-many-fences:
- Statuses : 6 pass(s)
- Exec time: [2.15, 2.17] s
* igt@gem_flink_race@flink_close:
- Statuses : 7 pass(s)
- Exec time: [5.01, 5.02] s
* igt@gem_flink_race@flink_name:
- Statuses : 7 pass(s)
- Exec time: [5.37, 5.38] s
* igt@gem_gpgpu_fill:
- Statuses : 1 pass(s) 1 skip(s)
- Exec time: [0.09, 0.10] s
* igt@gem_gtt_cpu_tlb:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.25] s
* igt@gem_linear_blits@interruptible:
- Statuses : 7 pass(s)
- Exec time: [1.88, 23.96] s
* igt@gem_linear_blits@normal:
- Statuses : 7 pass(s)
- Exec time: [1.54, 18.93] s
* igt@gem_madvise@dontneed-after-mmap:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.02] s
* igt@gem_madvise@dontneed-before-exec:
- Statuses : 6 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_madvise@dontneed-before-mmap:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_madvise@dontneed-before-pwrite:
- Statuses : 7 pass(s)
- Exec time: [0.00] s
* igt@gem_media_fill:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.08, 0.18] s
* igt@gem_mmap@bad-object:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_mmap@basic-small-bo:
- Statuses : 7 pass(s)
- Exec time: [0.59, 2.98] s
* igt@gem_mmap@big-bo:
- Statuses : 6 pass(s)
- Exec time: [0.66, 2.44] s
* igt@gem_mmap@short-mmap:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@gem_mmap_gtt@basic-copy:
- Statuses : 7 pass(s)
- Exec time: [0.17, 0.85] s
* igt@gem_mmap_gtt@basic-read:
- Statuses : 6 pass(s)
- Exec time: [0.03, 0.13] s
* igt@gem_mmap_gtt@basic-read-write:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.05] s
* igt@gem_mmap_gtt@basic-read-write-distinct:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.06] s
* igt@gem_mmap_gtt@basic-short:
- Statuses : 7 pass(s)
- Exec time: [0.02, 0.07] s
* igt@gem_mmap_gtt@basic-small-bo:
- Statuses :
- Exec time: [None] s
* igt@gem_mmap_gtt@basic-small-bo-tiledx:
- Statuses : 7 pass(s)
- Exec time: [0.27, 0.85] s
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- Statuses : 7 pass(s)
- Exec time: [0.23, 0.83] s
* igt@gem_mmap_gtt@basic-small-copy:
- Statuses : 7 pass(s)
- Exec time: [0.46, 3.17] s
* igt@gem_mmap_gtt@basic-small-copy-odd:
- Statuses : 7 pass(s)
- Exec time: [0.71, 4.06] s
* igt@gem_mmap_gtt@basic-small-copy-xy:
- Statuses : 6 pass(s)
- Exec time: [0.85, 4.46] s
* igt@gem_mmap_gtt@basic-wc:
- Statuses : 6 pass(s)
- Exec time: [0.64] s
* igt@gem_mmap_gtt@basic-write:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.47] s
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.31] s
* igt@gem_mmap_gtt@basic-write-gtt:
- Statuses : 7 pass(s)
- Exec time: [0.10, 0.81] s
* igt@gem_mmap_gtt@basic-write-read:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.05] s
* igt@gem_mmap_gtt@basic-write-read-distinct:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.05] s
* igt@gem_mmap_gtt@big-bo:
- Statuses : 7 pass(s)
- Exec time: [0.26, 1.03] s
* igt@gem_mmap_gtt@big-bo-tiledx:
- Statuses : 7 pass(s)
- Exec time: [0.48, 1.89] s
* igt@gem_mmap_gtt@big-bo-tiledy:
- Statuses : 7 pass(s)
- Exec time: [0.30, 1.96] s
* igt@gem_mmap_gtt@big-copy:
- Statuses : 7 pass(s)
- Exec time: [1.34, 11.15] s
* igt@gem_mmap_gtt@big-copy-odd:
- Statuses : 7 pass(s)
- Exec time: [1.53, 12.43] s
* igt@gem_mmap_gtt@big-copy-xy:
- Statuses : 7 pass(s)
- Exec time: [1.55, 16.45] s
* igt@gem_mmap_gtt@coherency:
- Statuses : 3 pass(s) 4 skip(s)
- Exec time: [0.0, 0.18] s
* igt@gem_mmap_gtt@fault-concurrent:
- Statuses : 7 pass(s)
- Exec time: [2.49, 3.89] s
* igt@gem_mmap_gtt@hang:
- Statuses : 7 pass(s)
- Exec time: [5.42, 5.49] s
* igt@gem_mmap_gtt@medium-copy:
- Statuses : 7 pass(s)
- Exec time: [0.94, 6.64] s
* igt@gem_mmap_gtt@medium-copy-odd:
- Statuses : 7 pass(s)
- Exec time: [0.82, 6.23] s
* igt@gem_mmap_gtt@medium-copy-xy:
- Statuses : 7 pass(s)
- Exec time: [0.93, 8.30] s
* igt@gem_mmap_gtt@zero-extend:
- Statuses : 7 pass(s)
- Exec time: [0.0] s
* igt@gem_mmap_offset@bad-extensions:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_mmap_offset@bad-flags:
- Statuses :
- Exec time: [None] s
* igt@gem_mmap_offset@bad-object:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_mmap_offset@basic-uaf:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_mmap_offset@clear:
- Statuses : 7 pass(s)
- Exec time: [22.06, 61.06] s
* igt@gem_mmap_offset@close-race:
- Statuses : 7 pass(s)
- Exec time: [20.06, 20.10] s
* igt@gem_mmap_offset@isolation:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_mmap_offset@open-flood:
- Statuses : 7 pass(s)
- Exec time: [21.50, 21.58] s
* igt@gem_mmap_offset@pf-nonblock:
- Statuses : 7 pass(s)
- Exec time: [0.00, 0.01] s
* igt@gem_mmap_wc@close:
- Statuses : 7 pass(s)
- Exec time: [0.04, 0.19] s
* igt@gem_mmap_wc@coherency:
- Statuses : 7 pass(s)
- Exec time: [0.09, 0.22] s
* igt@gem_mmap_wc@copy:
- Statuses : 7 pass(s)
- Exec time: [0.15, 0.41] s
* igt@gem_mmap_wc@fault-concurrent:
- Statuses : 7 pass(s)
- Exec time: [0.55, 2.33] s
* igt@gem_mmap_wc@invalid-flags:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_mmap_wc@read:
- Statuses : 7 pass(s)
- Exec time: [0.05, 0.27] s
* igt@gem_mmap_wc@read-write:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.06] s
* igt@gem_mmap_wc@read-write-distinct:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.06] s
* igt@gem_mmap_wc@set-cache-level:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_mmap_wc@write:
- Statuses : 7 pass(s)
- Exec time: [0.07, 0.25] s
* igt@gem_mmap_wc@write-cpu-read-wc:
- Statuses : 7 pass(s)
- Exec time: [0.11, 0.35] s
* igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
- Statuses : 7 pass(s)
- Exec time: [0.10, 0.33] s
* igt@gem_mmap_wc@write-gtt-read-wc:
- Statuses : 7 pass(s)
- Exec time: [0.10, 0.56] s
* igt@gem_mmap_wc@write-read:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.06] s
* igt@gem_mmap_wc@write-read-distinct:
- Statuses : 7 pass(s)
- Exec time: [0.01, 0.06] s
* igt@gem_partial_pwrite_pread@reads:
- Statuses : 7 pass(s)
- Exec time: [0.65, 5.50] s
* igt@gem_partial_pwrite_pread@reads-display:
- Statuses : 7 pass(s)
- Exec time: [0.64, 5.81] s
* igt@gem_partial_pwrite_pread@reads-snoop:
- Statuses : 7 pass(s)
- Exec time: [0.66, 5.63] s
* igt@gem_partial_pwrite_pread@reads-uncached:
- Statuses : 7 pass(s)
- Exec time: [0.65, 5.54] s
* igt@gem_partial_pwrite_pread@write:
- Statuses : 7 pass(s)
- Exec time: [3.20, 13.18] s
* igt@gem_partial_pwrite_pread@write-display:
- Statuses : 2 pass(s)
- Exec time: [3.22, 3.27] s
* igt@gem_partial_pwrite_pread@write-snoop:
- Statuses : 6 pass(s)
- Exec time: [3.19, 13.42] s
* igt@gem_partial_pwrite_pread@write-uncached:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/index.html
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Alderlake-S platform enabling patches
2021-01-25 23:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-01-26 0:05 ` Aditya Swarup
0 siblings, 0 replies; 27+ messages in thread
From: Aditya Swarup @ 2021-01-26 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
On 1/25/21 3:26 PM, Patchwork wrote:
> == Series Details ==
>
> Series: Alderlake-S platform enabling patches
> URL : https://patchwork.freedesktop.org/series/86260/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9680_full -> Patchwork_19488_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_19488_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_19488_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_19488_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@kms_flip@absolute-wf_vblank-interruptible@b-edp1:
> - shard-tglb: [PASS][1] -> [INCOMPLETE][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/shard-tglb2/igt@kms_flip@absolute-wf_vblank-interruptible@b-edp1.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/shard-tglb6/igt@kms_flip@absolute-wf_vblank-interruptible@b-edp1.html
This failure is unrelated to the patch series. Every patch in the series is protected by platform specific checks related to Alderlake-S
and shouldn't affect TGL execution. Seems to be a one off.
aswarup
>
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@gem_ctx_persistence@many-contexts}:
> - shard-tglb: [PASS][3] -> [FAIL][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/shard-tglb3/igt@gem_ctx_persistence@many-contexts.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/shard-tglb1/igt@gem_ctx_persistence@many-contexts.html
>
> * {igt@sysfs_clients@busy@bcs0}:
> - shard-kbl: [PASS][5] -> [FAIL][6]
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/shard-kbl1/igt@sysfs_clients@busy@bcs0.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/shard-kbl3/igt@sysfs_clients@busy@bcs0.html
>
>
> New tests
> ---------
>
> New tests have been introduced between CI_DRM_9680_full and Patchwork_19488_full:
>
> ### New IGT tests (1749) ###
>
> * igt@core_auth@many-magics:
> - Statuses : 6 pass(s)
> - Exec time: [0.15, 0.87] s
>
> * igt@core_getclient:
> - Statuses : 7 pass(s)
> - Exec time: [0.07, 0.18] s
>
> * igt@core_getstats:
> - Statuses : 6 pass(s)
> - Exec time: [0.07, 0.25] s
>
> * igt@core_getversion:
> - Statuses : 7 pass(s)
> - Exec time: [0.07, 0.17] s
>
> * igt@core_setmaster_vs_auth:
> - Statuses : 7 pass(s)
> - Exec time: [0.07, 0.21] s
>
> * igt@debugfs_test@read_all_entries_display_off:
> - Statuses : 6 pass(s)
> - Exec time: [0.07, 1.16] s
>
> * igt@debugfs_test@read_all_entries_display_on:
> - Statuses :
> - Exec time: [None] s
>
> * igt@drm_import_export@flink:
> - Statuses : 7 pass(s)
> - Exec time: [10.74, 10.75] s
>
> * igt@drm_import_export@import-close-race-flink:
> - Statuses : 7 pass(s)
> - Exec time: [10.74, 10.76] s
>
> * igt@drm_import_export@import-close-race-prime:
> - Statuses : 7 pass(s)
> - Exec time: [10.74] s
>
> * igt@drm_import_export@prime:
> - Statuses : 7 pass(s)
> - Exec time: [10.74, 10.75] s
>
> * igt@drm_read@empty-block:
> - Statuses : 2 pass(s)
> - Exec time: [1.0] s
>
> * igt@drm_read@empty-nonblock:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@drm_read@fault-buffer:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@drm_read@invalid-buffer:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@drm_read@short-buffer-block:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@drm_read@short-buffer-nonblock:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@dumb_buffer@create-clear:
> - Statuses : 7 pass(s)
> - Exec time: [37.35, 48.34] s
>
> * igt@dumb_buffer@create-valid-dumb:
> - Statuses : 6 pass(s)
> - Exec time: [0.0] s
>
> * igt@dumb_buffer@invalid-bpp:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@dumb_buffer@map-invalid-size:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@dumb_buffer@map-uaf:
> - Statuses : 7 pass(s)
> - Exec time: [0.02, 0.10] s
>
> * igt@dumb_buffer@map-valid:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_bad_reloc@negative-reloc-bltcopy:
> - Statuses : 7 pass(s)
> - Exec time: [0.35, 4.13] s
>
> * igt@gem_blits@basic:
> - Statuses : 7 pass(s)
> - Exec time: [1.43, 14.05] s
>
> * igt@gem_busy@close-race:
> - Statuses : 5 pass(s)
> - Exec time: [21.73, 22.33] s
>
> * igt@gem_caching@read-writes:
> - Statuses : 7 pass(s)
> - Exec time: [4.43, 23.0] s
>
> * igt@gem_caching@reads:
> - Statuses : 6 pass(s)
> - Exec time: [0.66, 5.85] s
>
> * igt@gem_caching@writes:
> - Statuses : 7 pass(s)
> - Exec time: [2.29, 13.28] s
>
> * igt@gem_close@basic:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_close@many-handles-one-vma:
> - Statuses : 7 pass(s)
> - Exec time: [0.02, 0.10] s
>
> * igt@gem_create@create-invalid-size:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_create@create-valid-nonaligned:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_bad_destroy@double-destroy:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_ctx_bad_destroy@invalid-ctx:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_bad_destroy@invalid-default-ctx:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_bad_destroy@invalid-pad:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_ctx_exec@basic-invalid-context:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_ctx_freq@sysfs:
> - Statuses : 7 pass(s)
> - Exec time: [4.81, 4.94] s
>
> * igt@gem_ctx_param@basic:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@basic-default:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@get-priority-new-ctx:
> - Statuses : 5 pass(s) 2 skip(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_ctx_param@invalid-ctx-get:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@invalid-ctx-set:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@invalid-param-get:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@invalid-param-set:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@invalid-size-get:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@invalid-size-set:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@non-root-set:
> - Statuses : 6 pass(s)
> - Exec time: [0.01, 0.04] s
>
> * igt@gem_ctx_param@non-root-set-no-zeromap:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.04] s
>
> * igt@gem_ctx_param@root-set:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@root-set-no-zeromap-disabled:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_ctx_param@root-set-no-zeromap-enabled:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@set-priority-invalid-size:
> - Statuses : 5 pass(s) 2 skip(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@set-priority-not-supported:
> - Statuses : 2 pass(s) 5 skip(s)
> - Exec time: [0.0] s
>
> * igt@gem_ctx_param@set-priority-range:
> - Statuses : 5 pass(s) 2 skip(s)
> - Exec time: [0.0, 0.06] s
>
> * igt@gem_eio@banned:
> - Statuses : 7 pass(s)
> - Exec time: [0.05, 0.42] s
>
> * igt@gem_eio@execbuf:
> - Statuses : 7 pass(s)
> - Exec time: [0.02, 0.07] s
>
> * igt@gem_eio@hibernate:
> - Statuses : 7 pass(s)
> - Exec time: [12.63, 15.24] s
>
> * igt@gem_eio@in-flight-10ms:
> - Statuses : 7 pass(s)
> - Exec time: [0.45, 2.37] s
>
> * igt@gem_eio@in-flight-1us:
> - Statuses : 7 pass(s)
> - Exec time: [0.37, 2.36] s
>
> * igt@gem_eio@in-flight-contexts-10ms:
> - Statuses : 7 pass(s)
> - Exec time: [1.24, 36.49] s
>
> * igt@gem_eio@in-flight-contexts-1us:
> - Statuses : 7 pass(s)
> - Exec time: [1.07, 36.60] s
>
> * igt@gem_eio@in-flight-contexts-immediate:
> - Statuses : 6 pass(s)
> - Exec time: [2.36, 36.54] s
>
> * igt@gem_eio@in-flight-external:
> - Statuses : 7 pass(s)
> - Exec time: [0.03, 0.24] s
>
> * igt@gem_eio@in-flight-immediate:
> - Statuses : 7 pass(s)
> - Exec time: [0.40, 2.18] s
>
> * igt@gem_eio@in-flight-internal-10ms:
> - Statuses : 7 pass(s)
> - Exec time: [0.04, 0.28] s
>
> * igt@gem_eio@in-flight-internal-1us:
> - Statuses : 7 pass(s)
> - Exec time: [0.03, 0.27] s
>
> * igt@gem_eio@in-flight-internal-immediate:
> - Statuses : 7 pass(s)
> - Exec time: [0.03, 0.26] s
>
> * igt@gem_eio@in-flight-suspend:
> - Statuses : 7 pass(s)
> - Exec time: [0.98, 2.43] s
>
> * igt@gem_eio@reset-stress:
> - Statuses : 7 pass(s)
> - Exec time: [28.52, 39.12] s
>
> * igt@gem_eio@suspend:
> - Statuses : 7 pass(s)
> - Exec time: [10.97, 12.60] s
>
> * igt@gem_eio@throttle:
> - Statuses : 7 pass(s)
> - Exec time: [0.02, 0.09] s
>
> * igt@gem_eio@unwedge-stress:
> - Statuses : 7 pass(s)
> - Exec time: [28.41, 40.02] s
>
> * igt@gem_eio@wait-10ms:
> - Statuses : 7 pass(s)
> - Exec time: [0.03, 0.15] s
>
> * igt@gem_eio@wait-1us:
> - Statuses : 7 pass(s)
> - Exec time: [0.03, 0.15] s
>
> * igt@gem_eio@wait-immediate:
> - Statuses : 6 pass(s)
> - Exec time: [0.02, 0.14] s
>
> * igt@gem_eio@wait-wedge-10ms:
> - Statuses : 7 pass(s)
> - Exec time: [0.04, 0.27] s
>
> * igt@gem_eio@wait-wedge-1us:
> - Statuses : 7 pass(s)
> - Exec time: [0.03, 0.27] s
>
> * igt@gem_eio@wait-wedge-immediate:
> - Statuses : 7 pass(s)
> - Exec time: [0.04, 0.25] s
>
> * igt@gem_exec_alignment@single:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_exec_await@wide-all:
> - Statuses : 7 pass(s)
> - Exec time: [21.80, 22.50] s
>
> * igt@gem_exec_await@wide-contexts:
> - Statuses : 6 pass(s)
> - Exec time: [21.61, 22.31] s
>
> * igt@gem_exec_balancer@bonded-chain:
> - Statuses : 4 pass(s) 2 skip(s)
> - Exec time: [0.0, 7.20] s
>
> * igt@gem_exec_balancer@bonded-semaphore:
> - Statuses : 5 pass(s) 2 skip(s)
> - Exec time: [0.0, 4.50] s
>
> * igt@gem_exec_balancer@hang:
> - Statuses : 5 pass(s) 2 skip(s)
> - Exec time: [0.0, 4.59] s
>
> * igt@gem_exec_capture@userptr:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.05] s
>
> * igt@gem_exec_create@forked:
> - Statuses : 5 pass(s)
> - Exec time: [20.06, 20.14] s
>
> * igt@gem_exec_create@madvise:
> - Statuses : 7 pass(s)
> - Exec time: [20.04, 20.08] s
>
> * igt@gem_exec_fence@basic-busy-all:
> - Statuses : 6 pass(s)
> - Exec time: [0.01, 0.03] s
>
> * igt@gem_exec_fence@basic-wait-all:
> - Statuses : 6 pass(s)
> - Exec time: [0.01, 0.03] s
>
> * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
> - Statuses : 4 pass(s) 3 skip(s)
> - Exec time: [0.0, 6.07] s
>
> * igt@gem_exec_flush@basic-batch-kernel-default-uc:
> - Statuses : 6 pass(s)
> - Exec time: [5.64, 6.04] s
>
> * igt@gem_exec_flush@basic-batch-kernel-default-wb:
> - Statuses : 7 pass(s)
> - Exec time: [5.62, 6.07] s
>
> * igt@gem_exec_flush@basic-uc-pro-default:
> - Statuses : 2 pass(s)
> - Exec time: [5.42, 5.43] s
>
> * igt@gem_exec_flush@basic-uc-prw-default:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_exec_flush@basic-uc-ro-default:
> - Statuses : 7 pass(s)
> - Exec time: [5.40, 5.46] s
>
> * igt@gem_exec_flush@basic-uc-rw-default:
> - Statuses : 6 pass(s)
> - Exec time: [5.42, 5.47] s
>
> * igt@gem_exec_flush@basic-uc-set-default:
> - Statuses : 7 pass(s)
> - Exec time: [5.41, 5.47] s
>
> * igt@gem_exec_flush@basic-wb-pro-default:
> - Statuses : 7 pass(s)
> - Exec time: [5.41, 5.47] s
>
> * igt@gem_exec_flush@basic-wb-prw-default:
> - Statuses : 6 pass(s)
> - Exec time: [5.41, 5.48] s
>
> * igt@gem_exec_flush@basic-wb-ro-before-default:
> - Statuses : 7 pass(s)
> - Exec time: [5.41, 5.46] s
>
> * igt@gem_exec_flush@basic-wb-ro-default:
> - Statuses : 7 pass(s)
> - Exec time: [5.41, 5.48] s
>
> * igt@gem_exec_flush@basic-wb-rw-before-default:
> - Statuses : 7 pass(s)
> - Exec time: [5.41, 5.46] s
>
> * igt@gem_exec_flush@basic-wb-rw-default:
> - Statuses : 7 pass(s)
> - Exec time: [5.41, 5.48] s
>
> * igt@gem_exec_flush@basic-wb-set-default:
> - Statuses : 7 pass(s)
> - Exec time: [5.41, 5.47] s
>
> * igt@gem_exec_nop@basic-parallel:
> - Statuses : 7 pass(s)
> - Exec time: [2.78, 3.33] s
>
> * igt@gem_exec_nop@basic-sequential:
> - Statuses : 6 pass(s)
> - Exec time: [2.77, 3.35] s
>
> * igt@gem_exec_nop@basic-series:
> - Statuses : 7 pass(s)
> - Exec time: [2.75, 3.29] s
>
> * igt@gem_exec_parallel@basic:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_exec_parallel@contexts:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_exec_parallel@fds:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_exec_params@batch-first:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_params@cliprects-invalid:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_params@cliprects_ptr-dirt:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_params@dr1-dirt:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@dr4-dirt:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@invalid-bsd-ring:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@invalid-bsd1-flag-on-blt:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@invalid-bsd1-flag-on-render:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_params@invalid-bsd1-flag-on-vebox:
> - Statuses : 6 pass(s) 1 skip(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@invalid-bsd2-flag-on-blt:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@invalid-bsd2-flag-on-render:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@invalid-bsd2-flag-on-vebox:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_exec_params@invalid-fence-in:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@invalid-flag:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@invalid-ring:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@invalid-ring2:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@no-blt:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_exec_params@no-bsd:
> - Statuses : 7 skip(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_params@no-vebox:
> - Statuses : 1 pass(s) 4 skip(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_params@rel-constants-invalid:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_params@rel-constants-invalid-rel-gen5:
> - Statuses : 6 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_params@rel-constants-invalid-ring:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_params@rs-invalid:
> - Statuses : 6 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_params@rsvd2-dirt:
> - Statuses : 7 skip(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_params@secure-non-master:
> - Statuses : 7 skip(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_params@secure-non-root:
> - Statuses : 7 skip(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_params@sol-reset-invalid:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_params@sol-reset-not-gen7:
> - Statuses : 6 pass(s) 1 skip(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_reloc@basic-active:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_exec_reloc@basic-cpu:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.03] s
>
> * igt@gem_exec_reloc@basic-cpu-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.17] s
>
> * igt@gem_exec_reloc@basic-cpu-gtt:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_exec_reloc@basic-cpu-gtt-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
> - Statuses : 6 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_reloc@basic-cpu-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_reloc@basic-cpu-read:
> - Statuses : 5 pass(s)
> - Exec time: [0.00, 0.03] s
>
> * igt@gem_exec_reloc@basic-cpu-read-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-cpu-read-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_reloc@basic-cpu-wc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.03] s
>
> * igt@gem_exec_reloc@basic-cpu-wc-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-cpu-wc-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-gtt:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-gtt-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.18] s
>
> * igt@gem_exec_reloc@basic-gtt-cpu:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-gtt-cpu-active:
> - Statuses : 6 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-gtt-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_reloc@basic-gtt-read:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-gtt-read-active:
> - Statuses : 6 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-gtt-read-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-gtt-wc:
> - Statuses : 6 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-gtt-wc-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-gtt-wc-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-range:
> - Statuses : 6 pass(s)
> - Exec time: [0.01, 0.11] s
>
> * igt@gem_exec_reloc@basic-range-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.16] s
>
> * igt@gem_exec_reloc@basic-softpin:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_reloc@basic-wc:
> - Statuses : 5 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-wc-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-wc-cpu:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.03] s
>
> * igt@gem_exec_reloc@basic-wc-cpu-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.17] s
>
> * igt@gem_exec_reloc@basic-wc-cpu-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_reloc@basic-wc-gtt:
> - Statuses : 6 pass(s)
> - Exec time: [0.00, 0.03] s
>
> * igt@gem_exec_reloc@basic-wc-gtt-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.17] s
>
> * igt@gem_exec_reloc@basic-wc-gtt-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-wc-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-wc-read:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.03] s
>
> * igt@gem_exec_reloc@basic-wc-read-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-wc-read-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_reloc@basic-write-cpu:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-write-cpu-active:
> - Statuses : 5 pass(s)
> - Exec time: [0.11, 0.17] s
>
> * igt@gem_exec_reloc@basic-write-cpu-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_reloc@basic-write-gtt:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-write-gtt-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-write-gtt-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.02] s
>
> * igt@gem_exec_reloc@basic-write-read:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-write-read-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-write-read-noreloc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_reloc@basic-write-wc:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_exec_reloc@basic-write-wc-active:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.16] s
>
> * igt@gem_exec_reloc@basic-write-wc-noreloc:
> - Statuses : 6 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_exec_schedule@smoketest-all:
> - Statuses : 5 pass(s) 2 skip(s)
> - Exec time: [0.0, 32.30] s
>
> * igt@gem_exec_suspend@basic:
> - Statuses : 7 pass(s)
> - Exec time: [0.18, 1.50] s
>
> * igt@gem_exec_suspend@basic-s3-devices:
> - Statuses : 7 pass(s)
> - Exec time: [6.42, 11.25] s
>
> * igt@gem_exec_suspend@basic-s4-devices:
> - Statuses : 7 pass(s)
> - Exec time: [7.13, 11.87] s
>
> * igt@gem_fence_thrash@bo-copy:
> - Statuses : 7 pass(s)
> - Exec time: [1.13, 1.72] s
>
> * igt@gem_fence_thrash@bo-write-verify-none:
> - Statuses : 7 pass(s)
> - Exec time: [1.11, 1.23] s
>
> * igt@gem_fence_thrash@bo-write-verify-threaded-none:
> - Statuses : 7 pass(s)
> - Exec time: [1.21, 3.19] s
>
> * igt@gem_fence_thrash@bo-write-verify-threaded-x:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_fence_thrash@bo-write-verify-threaded-y:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_fence_thrash@bo-write-verify-x:
> - Statuses : 7 pass(s)
> - Exec time: [1.09, 1.30] s
>
> * igt@gem_fence_thrash@bo-write-verify-y:
> - Statuses : 7 pass(s)
> - Exec time: [1.11, 1.33] s
>
> * igt@gem_fenced_exec_thrash@2-spare-fences:
> - Statuses : 7 pass(s)
> - Exec time: [2.15, 2.17] s
>
> * igt@gem_fenced_exec_thrash@no-spare-fences:
> - Statuses : 7 pass(s)
> - Exec time: [2.15, 2.17] s
>
> * igt@gem_fenced_exec_thrash@no-spare-fences-busy:
> - Statuses : 7 pass(s)
> - Exec time: [2.16, 2.19] s
>
> * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
> - Statuses : 7 pass(s)
> - Exec time: [2.15, 2.18] s
>
> * igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
> - Statuses : 7 pass(s)
> - Exec time: [2.15, 2.18] s
>
> * igt@gem_fenced_exec_thrash@too-many-fences:
> - Statuses : 6 pass(s)
> - Exec time: [2.15, 2.17] s
>
> * igt@gem_flink_race@flink_close:
> - Statuses : 7 pass(s)
> - Exec time: [5.01, 5.02] s
>
> * igt@gem_flink_race@flink_name:
> - Statuses : 7 pass(s)
> - Exec time: [5.37, 5.38] s
>
> * igt@gem_gpgpu_fill:
> - Statuses : 1 pass(s) 1 skip(s)
> - Exec time: [0.09, 0.10] s
>
> * igt@gem_gtt_cpu_tlb:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.25] s
>
> * igt@gem_linear_blits@interruptible:
> - Statuses : 7 pass(s)
> - Exec time: [1.88, 23.96] s
>
> * igt@gem_linear_blits@normal:
> - Statuses : 7 pass(s)
> - Exec time: [1.54, 18.93] s
>
> * igt@gem_madvise@dontneed-after-mmap:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.02] s
>
> * igt@gem_madvise@dontneed-before-exec:
> - Statuses : 6 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_madvise@dontneed-before-mmap:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_madvise@dontneed-before-pwrite:
> - Statuses : 7 pass(s)
> - Exec time: [0.00] s
>
> * igt@gem_media_fill:
> - Statuses : 5 pass(s) 1 skip(s)
> - Exec time: [0.08, 0.18] s
>
> * igt@gem_mmap@bad-object:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_mmap@basic-small-bo:
> - Statuses : 7 pass(s)
> - Exec time: [0.59, 2.98] s
>
> * igt@gem_mmap@big-bo:
> - Statuses : 6 pass(s)
> - Exec time: [0.66, 2.44] s
>
> * igt@gem_mmap@short-mmap:
> - Statuses : 6 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_mmap_gtt@basic-copy:
> - Statuses : 7 pass(s)
> - Exec time: [0.17, 0.85] s
>
> * igt@gem_mmap_gtt@basic-read:
> - Statuses : 6 pass(s)
> - Exec time: [0.03, 0.13] s
>
> * igt@gem_mmap_gtt@basic-read-write:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.05] s
>
> * igt@gem_mmap_gtt@basic-read-write-distinct:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.06] s
>
> * igt@gem_mmap_gtt@basic-short:
> - Statuses : 7 pass(s)
> - Exec time: [0.02, 0.07] s
>
> * igt@gem_mmap_gtt@basic-small-bo:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_mmap_gtt@basic-small-bo-tiledx:
> - Statuses : 7 pass(s)
> - Exec time: [0.27, 0.85] s
>
> * igt@gem_mmap_gtt@basic-small-bo-tiledy:
> - Statuses : 7 pass(s)
> - Exec time: [0.23, 0.83] s
>
> * igt@gem_mmap_gtt@basic-small-copy:
> - Statuses : 7 pass(s)
> - Exec time: [0.46, 3.17] s
>
> * igt@gem_mmap_gtt@basic-small-copy-odd:
> - Statuses : 7 pass(s)
> - Exec time: [0.71, 4.06] s
>
> * igt@gem_mmap_gtt@basic-small-copy-xy:
> - Statuses : 6 pass(s)
> - Exec time: [0.85, 4.46] s
>
> * igt@gem_mmap_gtt@basic-wc:
> - Statuses : 6 pass(s)
> - Exec time: [0.64] s
>
> * igt@gem_mmap_gtt@basic-write:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.47] s
>
> * igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
> - Statuses : 5 pass(s) 2 skip(s)
> - Exec time: [0.0, 0.31] s
>
> * igt@gem_mmap_gtt@basic-write-gtt:
> - Statuses : 7 pass(s)
> - Exec time: [0.10, 0.81] s
>
> * igt@gem_mmap_gtt@basic-write-read:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.05] s
>
> * igt@gem_mmap_gtt@basic-write-read-distinct:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.05] s
>
> * igt@gem_mmap_gtt@big-bo:
> - Statuses : 7 pass(s)
> - Exec time: [0.26, 1.03] s
>
> * igt@gem_mmap_gtt@big-bo-tiledx:
> - Statuses : 7 pass(s)
> - Exec time: [0.48, 1.89] s
>
> * igt@gem_mmap_gtt@big-bo-tiledy:
> - Statuses : 7 pass(s)
> - Exec time: [0.30, 1.96] s
>
> * igt@gem_mmap_gtt@big-copy:
> - Statuses : 7 pass(s)
> - Exec time: [1.34, 11.15] s
>
> * igt@gem_mmap_gtt@big-copy-odd:
> - Statuses : 7 pass(s)
> - Exec time: [1.53, 12.43] s
>
> * igt@gem_mmap_gtt@big-copy-xy:
> - Statuses : 7 pass(s)
> - Exec time: [1.55, 16.45] s
>
> * igt@gem_mmap_gtt@coherency:
> - Statuses : 3 pass(s) 4 skip(s)
> - Exec time: [0.0, 0.18] s
>
> * igt@gem_mmap_gtt@fault-concurrent:
> - Statuses : 7 pass(s)
> - Exec time: [2.49, 3.89] s
>
> * igt@gem_mmap_gtt@hang:
> - Statuses : 7 pass(s)
> - Exec time: [5.42, 5.49] s
>
> * igt@gem_mmap_gtt@medium-copy:
> - Statuses : 7 pass(s)
> - Exec time: [0.94, 6.64] s
>
> * igt@gem_mmap_gtt@medium-copy-odd:
> - Statuses : 7 pass(s)
> - Exec time: [0.82, 6.23] s
>
> * igt@gem_mmap_gtt@medium-copy-xy:
> - Statuses : 7 pass(s)
> - Exec time: [0.93, 8.30] s
>
> * igt@gem_mmap_gtt@zero-extend:
> - Statuses : 7 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_mmap_offset@bad-extensions:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_mmap_offset@bad-flags:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_mmap_offset@bad-object:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_mmap_offset@basic-uaf:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_mmap_offset@clear:
> - Statuses : 7 pass(s)
> - Exec time: [22.06, 61.06] s
>
> * igt@gem_mmap_offset@close-race:
> - Statuses : 7 pass(s)
> - Exec time: [20.06, 20.10] s
>
> * igt@gem_mmap_offset@isolation:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_mmap_offset@open-flood:
> - Statuses : 7 pass(s)
> - Exec time: [21.50, 21.58] s
>
> * igt@gem_mmap_offset@pf-nonblock:
> - Statuses : 7 pass(s)
> - Exec time: [0.00, 0.01] s
>
> * igt@gem_mmap_wc@close:
> - Statuses : 7 pass(s)
> - Exec time: [0.04, 0.19] s
>
> * igt@gem_mmap_wc@coherency:
> - Statuses : 7 pass(s)
> - Exec time: [0.09, 0.22] s
>
> * igt@gem_mmap_wc@copy:
> - Statuses : 7 pass(s)
> - Exec time: [0.15, 0.41] s
>
> * igt@gem_mmap_wc@fault-concurrent:
> - Statuses : 7 pass(s)
> - Exec time: [0.55, 2.33] s
>
> * igt@gem_mmap_wc@invalid-flags:
> - Statuses : 7 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_mmap_wc@read:
> - Statuses : 7 pass(s)
> - Exec time: [0.05, 0.27] s
>
> * igt@gem_mmap_wc@read-write:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.06] s
>
> * igt@gem_mmap_wc@read-write-distinct:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.06] s
>
> * igt@gem_mmap_wc@set-cache-level:
> - Statuses : 2 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_mmap_wc@write:
> - Statuses : 7 pass(s)
> - Exec time: [0.07, 0.25] s
>
> * igt@gem_mmap_wc@write-cpu-read-wc:
> - Statuses : 7 pass(s)
> - Exec time: [0.11, 0.35] s
>
> * igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
> - Statuses : 7 pass(s)
> - Exec time: [0.10, 0.33] s
>
> * igt@gem_mmap_wc@write-gtt-read-wc:
> - Statuses : 7 pass(s)
> - Exec time: [0.10, 0.56] s
>
> * igt@gem_mmap_wc@write-read:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.06] s
>
> * igt@gem_mmap_wc@write-read-distinct:
> - Statuses : 7 pass(s)
> - Exec time: [0.01, 0.06] s
>
> * igt@gem_partial_pwrite_pread@reads:
> - Statuses : 7 pass(s)
> - Exec time: [0.65, 5.50] s
>
> * igt@gem_partial_pwrite_pread@reads-display:
> - Statuses : 7 pass(s)
> - Exec time: [0.64, 5.81] s
>
> * igt@gem_partial_pwrite_pread@reads-snoop:
> - Statuses : 7 pass(s)
> - Exec time: [0.66, 5.63] s
>
> * igt@gem_partial_pwrite_pread@reads-uncached:
> - Statuses : 7 pass(s)
> - Exec time: [0.65, 5.54] s
>
> * igt@gem_partial_pwrite_pread@write:
> - Statuses : 7 pass(s)
> - Exec time: [3.20, 13.18] s
>
> * igt@gem_partial_pwrite_pread@write-display:
> - Statuses : 2 pass(s)
> - Exec time: [3.22, 3.27] s
>
> * igt@gem_partial_pwrite_pread@write-snoop:
> - Statuses : 6 pass(s)
> - Exec time: [3.19, 13.42] s
>
> * igt@gem_partial_pwrite_pread@write-uncached:
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19488/index.html
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alderlake-S platform enabling patches (rev2)
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (13 preceding siblings ...)
2021-01-25 23:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-01-26 3:27 ` Patchwork
2021-01-26 3:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-26 3:27 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: Alderlake-S platform enabling patches (rev2)
URL : https://patchwork.freedesktop.org/series/86260/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aade12b92978 x86/gpu: Add Alderlake-S stolen memory support
300dcb516efb drm/i915/adl_s: Add PCH support
43ecfab3c2ba drm/i915/adl_s: Add Interrupt Support
6e5d01044438 drm/i915/adl_s: Add PHYs for Alderlake S
7c2a725093dc drm/i915/adl_s: Configure DPLL for ADL-S
0b554f3df487 drm/i915/adl_s: Configure Port clock registers for ADL-S
a3783d1bb097 drm/i915/adl_s: Initialize display for ADL-S
4d3692703ac0 drm/i915/adl_s: Add adl-s ddc pin mapping
a9a635f54fb2 drm/i915/adl_s: Add vbt port and aux channel settings for adls
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10:
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.
total: 0 errors, 1 warnings, 0 checks, 81 lines checked
0700ccc2b0ce drm/i915/adl_s: Update combo PHY master/slave relationships
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Alderlake-S platform enabling patches (rev2)
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (14 preceding siblings ...)
2021-01-26 3:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alderlake-S platform enabling patches (rev2) Patchwork
@ 2021-01-26 3:28 ` Patchwork
2021-01-26 3:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
18 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-26 3:28 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: Alderlake-S platform enabling patches (rev2)
URL : https://patchwork.freedesktop.org/series/86260/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1327:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Alderlake-S platform enabling patches (rev2)
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (15 preceding siblings ...)
2021-01-26 3:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-01-26 3:59 ` Patchwork
2021-01-26 10:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-26 15:09 ` [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Lucas De Marchi
18 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-26 3:59 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3049 bytes --]
== Series Details ==
Series: Alderlake-S platform enabling patches (rev2)
URL : https://patchwork.freedesktop.org/series/86260/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9682 -> Patchwork_19501
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/index.html
Known issues
------------
Here are the changes found in Patchwork_19501 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ringfill@basic-all:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/fi-tgl-y/igt@gem_ringfill@basic-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/fi-tgl-y/igt@gem_ringfill@basic-all.html
* igt@i915_selftest@live@execlists:
- fi-tgl-u2: [PASS][3] -> [INCOMPLETE][4] ([i915#2268])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/fi-tgl-u2/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/fi-tgl-u2/igt@i915_selftest@live@execlists.html
#### Possible fixes ####
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[i915#2268]: https://gitlab.freedesktop.org/drm/intel/issues/2268
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (40 -> 36)
------------------------------
Missing (4): fi-ctg-p8600 fi-jsl-1 fi-ilk-m540 fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9682 -> Patchwork_19501
CI-20190529: 20190529
CI_DRM_9682: 35ee6d505b478462c04952da1a4fbc03991af114 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5971: abef2b7d6ff30f3b948b3e5d39653debb73083f3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19501: 0700ccc2b0ce0d963275a5066fc1fa03d2d5ee79 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0700ccc2b0ce drm/i915/adl_s: Update combo PHY master/slave relationships
a9a635f54fb2 drm/i915/adl_s: Add vbt port and aux channel settings for adls
4d3692703ac0 drm/i915/adl_s: Add adl-s ddc pin mapping
a3783d1bb097 drm/i915/adl_s: Initialize display for ADL-S
0b554f3df487 drm/i915/adl_s: Configure Port clock registers for ADL-S
7c2a725093dc drm/i915/adl_s: Configure DPLL for ADL-S
6e5d01044438 drm/i915/adl_s: Add PHYs for Alderlake S
43ecfab3c2ba drm/i915/adl_s: Add Interrupt Support
300dcb516efb drm/i915/adl_s: Add PCH support
aade12b92978 x86/gpu: Add Alderlake-S stolen memory support
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/index.html
[-- Attachment #1.2: Type: text/html, Size: 3827 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Alderlake-S platform enabling patches (rev2)
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (16 preceding siblings ...)
2021-01-26 3:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-01-26 10:22 ` Patchwork
2021-01-26 15:09 ` [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Lucas De Marchi
18 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-26 10:22 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 12390 bytes --]
== Series Details ==
Series: Alderlake-S platform enabling patches (rev2)
URL : https://patchwork.freedesktop.org/series/86260/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9682_full -> Patchwork_19501_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_19501_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19501_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19501_full:
### IGT changes ###
#### Warnings ####
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [INCOMPLETE][1] ([i915#155]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-kbl2/igt@i915_suspend@debugfs-reader.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-kbl3/igt@i915_suspend@debugfs-reader.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_persistence@many-contexts}:
- shard-tglb: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-tglb8/igt@gem_ctx_persistence@many-contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-tglb1/igt@gem_ctx_persistence@many-contexts.html
Known issues
------------
Here are the changes found in Patchwork_19501_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#658])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb2/igt@feature_discovery@psr2.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb8/igt@feature_discovery@psr2.html
* igt@gem_ctx_persistence@close-replace-race:
- shard-kbl: [PASS][7] -> [TIMEOUT][8] ([i915#2918])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-kbl7/igt@gem_ctx_persistence@close-replace-race.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-kbl7/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-kbl4/igt@gem_exec_fair@basic-none@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-kbl2/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1610])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-glk6/igt@gem_exec_schedule@u-fairslice@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-glk4/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#118] / [i915#95])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-glk2/igt@gem_exec_whisper@basic-fds-forked-all.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-glk2/igt@gem_exec_whisper@basic-fds-forked-all.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2574])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-tglb8/igt@kms_async_flips@test-time-stamp.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-tglb7/igt@kms_async_flips@test-time-stamp.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1226])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb7/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb2/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109642] / [fdo#111068] / [i915#658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb2/igt@kms_psr2_su@page_flip.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb6/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][27] ([i915#2842]) -> [PASS][28] +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-glk: [FAIL][29] ([i915#2842]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][31] ([i915#2842]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [FAIL][33] ([i915#2842]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][35] ([i915#2849]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-glk: [DMESG-WARN][37] ([i915#1610]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-glk6/igt@gem_exec_schedule@u-fairslice@vcs0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-glk4/igt@gem_exec_schedule@u-fairslice@vcs0.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [FAIL][39] ([i915#2598]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][41] ([fdo#109441]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
#### Warnings ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][43] ([i915#2842]) -> [FAIL][44] ([i915#2852])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][45] ([i915#2684]) -> [WARN][46] ([i915#2681] / [i915#2684])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][47] ([i915#2681] / [i915#2684]) -> [WARN][48] ([i915#2684])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][49] ([i915#658]) -> [SKIP][50] ([i915#2920])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][51] ([i915#2920]) -> [SKIP][52] ([i915#658]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#2574]: https://gitlab.freedesktop.org/drm/intel/issues/2574
[i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2918]: https://gitlab.freedesktop.org/drm/intel/issues/2918
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9682 -> Patchwork_19501
CI-20190529: 20190529
CI_DRM_9682: 35ee6d505b478462c04952da1a4fbc03991af114 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5971: abef2b7d6ff30f3b948b3e5d39653debb73083f3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19501: 0700ccc2b0ce0d963275a5066fc1fa03d2d5ee79 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19501/index.html
[-- Attachment #1.2: Type: text/html, Size: 14776 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
` (17 preceding siblings ...)
2021-01-26 10:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-01-26 15:09 ` Lucas De Marchi
18 siblings, 0 replies; 27+ messages in thread
From: Lucas De Marchi @ 2021-01-26 15:09 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
I fixed a few checkpatch issues in the commit messages and pushed to
drm-intel topic/adl-s-enabling branch.
Thanks
Lucas De Marchi
On Mon, Jan 25, 2021 at 06:07:43AM -0800, Aditya Swarup wrote:
>This patch revises all the changes suggested in rev 3 of
>Introduce Alderlake-S series for first 10 patches.
>https://patchwork.freedesktop.org/patch/405772/?series=82917&rev=3
>
>Most of the patches have already been reviewed and are good for merge.
>I will resend rest of the series once we have focussed reviews on the
>pending patches.
>
>Please ignore the patch:
>x86/gpu: Add Alderlake-S stolen memory support
>as it was picked up to prevent compilation issues and maintaining
>sequence of patches.
>The correct location for picking the latest revision of that patch is
>here:
>https://patchwork.freedesktop.org/series/86239/
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>
>Aditya Swarup (5):
> drm/i915/adl_s: Configure DPLL for ADL-S
> drm/i915/adl_s: Configure Port clock registers for ADL-S
> drm/i915/adl_s: Initialize display for ADL-S
> drm/i915/adl_s: Add adl-s ddc pin mapping
> drm/i915/adl_s: Add vbt port and aux channel settings for adls
>
>Anusha Srivatsa (3):
> drm/i915/adl_s: Add PCH support
> drm/i915/adl_s: Add Interrupt Support
> drm/i915/adl_s: Add PHYs for Alderlake S
>
>Caz Yokoyama (1):
> x86/gpu: Add Alderlake-S stolen memory support
>
>Matt Roper (1):
> drm/i915/adl_s: Update combo PHY master/slave relationships
>
> arch/x86/kernel/early-quirks.c | 1 +
> drivers/gpu/drm/i915/display/intel_bios.c | 70 +++++++++++++++----
> .../gpu/drm/i915/display/intel_combo_phy.c | 11 ++-
> drivers/gpu/drm/i915/display/intel_ddi.c | 62 ++++++++++------
> drivers/gpu/drm/i915/display/intel_display.c | 31 +++++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 ++++++++--
> drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +++++-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++
> drivers/gpu/drm/i915/i915_irq.c | 3 +-
> drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++--
> drivers/gpu/drm/i915/intel_pch.c | 8 ++-
> drivers/gpu/drm/i915/intel_pch.h | 3 +
> 12 files changed, 246 insertions(+), 55 deletions(-)
>
>--
>2.27.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2021-01-26 15:09 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-25 14:07 [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 01/10] x86/gpu: Add Alderlake-S stolen memory support Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 02/10] drm/i915/adl_s: Add PCH support Aditya Swarup
2021-01-25 17:39 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 03/10] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
2021-01-25 17:46 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 04/10] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
2021-01-25 17:51 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 05/10] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
2021-01-25 18:45 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 06/10] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 07/10] drm/i915/adl_s: Initialize display " Aditya Swarup
2021-01-25 18:47 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 08/10] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
2021-01-25 18:54 ` Lucas De Marchi
2021-01-25 14:07 ` [Intel-gfx] [PATCH 09/10] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
2021-01-25 14:07 ` [Intel-gfx] [PATCH 10/10] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
2021-01-25 17:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alderlake-S platform enabling patches Patchwork
2021-01-25 17:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-25 18:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-25 23:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-01-26 0:05 ` Aditya Swarup
2021-01-26 3:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alderlake-S platform enabling patches (rev2) Patchwork
2021-01-26 3:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-26 3:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-26 10:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-26 15:09 ` [Intel-gfx] [PATCH 00/10] Alderlake-S platform enabling patches Lucas De Marchi
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