From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Matt Roper" <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✓ Fi.CI.BAT: success for Begin enabling Xe_HP SDV and DG2 platforms (rev10)
Date: Fri, 06 Aug 2021 18:42:49 -0000 [thread overview]
Message-ID: <162827536944.27549.8238498526476653144@emeril.freedesktop.org> (raw)
In-Reply-To: <20210805163647.801064-1-matthew.d.roper@intel.com>
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== Series Details ==
Series: Begin enabling Xe_HP SDV and DG2 platforms (rev10)
URL : https://patchwork.freedesktop.org/series/92135/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10457 -> Patchwork_20781
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20781/index.html
Known issues
------------
Here are the changes found in Patchwork_20781 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][1] ([i915#1888]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10457/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20781/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-icl-u2: [DMESG-FAIL][3] -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10457/fi-icl-u2/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20781/fi-icl-u2/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (37 -> 34)
------------------------------
Missing (3): fi-bdw-samus fi-bsw-cyan bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10457 -> Patchwork_20781
CI-20190529: 20190529
CI_DRM_10457: 7700f858b68060307b0a7d94377a5d8f64000e5d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6162: 2f32b9e0da5f1ac9529318dd5b836c8cf4d3c441 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20781: c5300668b502fff59ac563d2a7b22f2341bd8c95 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c5300668b502 drm/i915/dg2: Configure PCON in DP pre-enable path
23befa04925d drm/i915/dg2: Maintain backward-compatible nested batch behavior
8c7ca653ac33 drm/i915/dg2: Add new LRI reg offsets
8db8e3b6bca0 drm/i915/xehpsdv: Read correct RP_STATE_CAP register
9793162b05a6 drm/i915/xehpsdv: factor out function to read RP_STATE_CAP
9dd72d6a97d4 drm/i915/xehpsdv: Add compute DSS type
91cde6f62ffc drm/i915/dg2: Report INSTDONE_GEOM values in error state
0ebc963f011d drm/i915/xehp: Loop over all gslices for INSTDONE processing
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20781/index.html
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next prev parent reply other threads:[~2021-08-06 18:42 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-05 16:36 [Intel-gfx] [PATCH v5 0/9] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 1/9] drm/i915/dg2: Add support for new DG2-G11 revid 0x5 Matt Roper
2021-08-05 16:48 ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 2/9] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-08-11 0:18 ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 3/9] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 4/9] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-08-05 17:26 ` Lucas De Marchi
2021-08-06 17:29 ` [Intel-gfx] [PATCH v5.1 " Matt Roper
2021-08-11 0:17 ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 5/9] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-08-12 22:49 ` Souza, Jose
2021-08-12 23:14 ` Lucas De Marchi
2021-08-12 23:18 ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 6/9] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 7/9] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-08-25 0:03 ` Yokoyama, Caz
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 8/9] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-08-18 21:56 ` Srivatsa, Anusha
2021-08-23 9:26 ` Tvrtko Ursulin
2021-08-24 4:06 ` Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 9/9] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-08-10 21:51 ` Souza, Jose
2021-08-05 17:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev9) Patchwork
2021-08-05 17:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-05 18:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-06 7:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-08-06 18:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev10) Patchwork
2021-08-06 18:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-06 18:42 ` Patchwork [this message]
2021-08-06 23:49 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
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