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From: "Yokoyama, Caz" <caz.yokoyama@intel.com>
To: "Roper, Matthew D" <matthew.d.roper@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "Abodunrin, Akeem G" <akeem.g.abodunrin@intel.com>,
	"Wilson, Chris P" <chris.p.wilson@intel.com>,
	"Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
Subject: Re: [Intel-gfx] [PATCH v5 7/9] drm/i915/dg2: Add new LRI reg offsets
Date: Wed, 25 Aug 2021 00:03:28 +0000	[thread overview]
Message-ID: <a803574069b89a44e726540481ab10bd89b01739.camel@intel.com> (raw)
In-Reply-To: <20210805163647.801064-8-matthew.d.roper@intel.com>

Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
-caz

On Thu, 2021-08-05 at 09:36 -0700, Matt Roper wrote:
> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> 
> New LRI register offsets were introduced for DG2, this patch adds
> those extra registers, and create new register table for setting
> offsets
> to compare with HW generated context image - especially for gt_lrc
> test.
> Also updates general purpose register with scratch offset for DG2, in
> order to use it for live_lrc_fixed selftest.
> 
> Cc: Chris P Wilson <chris.p.wilson@intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 85
> ++++++++++++++++++++++++++++-
>  1 file changed, 83 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index bb4af4977920..6ba8daea2f56 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -226,6 +226,40 @@ static const u8 gen12_xcs_offsets[] = {
>  	END
>  };
>  
> +static const u8 dg2_xcs_offsets[] = {
> +	NOP(1),
> +	LRI(15, POSTED),
> +	REG16(0x244),
> +	REG(0x034),
> +	REG(0x030),
> +	REG(0x038),
> +	REG(0x03c),
> +	REG(0x168),
> +	REG(0x140),
> +	REG(0x110),
> +	REG(0x1c0),
> +	REG(0x1c4),
> +	REG(0x1c8),
> +	REG(0x180),
> +	REG16(0x2b4),
> +	REG(0x120),
> +	REG(0x124),
> +
> +	NOP(1),
> +	LRI(9, POSTED),
> +	REG16(0x3a8),
> +	REG16(0x28c),
> +	REG16(0x288),
> +	REG16(0x284),
> +	REG16(0x280),
> +	REG16(0x27c),
> +	REG16(0x278),
> +	REG16(0x274),
> +	REG16(0x270),
> +
> +	END
> +};
> +
>  static const u8 gen8_rcs_offsets[] = {
>  	NOP(1),
>  	LRI(14, POSTED),
> @@ -525,6 +559,49 @@ static const u8 xehp_rcs_offsets[] = {
>  	END
>  };
>  
> +static const u8 dg2_rcs_offsets[] = {
> +	NOP(1),
> +	LRI(15, POSTED),
> +	REG16(0x244),
> +	REG(0x034),
> +	REG(0x030),
> +	REG(0x038),
> +	REG(0x03c),
> +	REG(0x168),
> +	REG(0x140),
> +	REG(0x110),
> +	REG(0x1c0),
> +	REG(0x1c4),
> +	REG(0x1c8),
> +	REG(0x180),
> +	REG16(0x2b4),
> +	REG(0x120),
> +	REG(0x124),
> +
> +	NOP(1),
> +	LRI(9, POSTED),
> +	REG16(0x3a8),
> +	REG16(0x28c),
> +	REG16(0x288),
> +	REG16(0x284),
> +	REG16(0x280),
> +	REG16(0x27c),
> +	REG16(0x278),
> +	REG16(0x274),
> +	REG16(0x270),
> +
> +	LRI(3, POSTED),
> +	REG(0x1b0),
> +	REG16(0x5a8),
> +	REG16(0x5ac),
> +
> +	NOP(6),
> +	LRI(1, 0),
> +	REG(0x0c8),
> +
> +	END
> +};
> +
>  #undef END
>  #undef REG16
>  #undef REG
> @@ -543,7 +620,9 @@ static const u8 *reg_offsets(const struct
> intel_engine_cs *engine)
>  		   !intel_engine_has_relative_mmio(engine));
>  
>  	if (engine->class == RENDER_CLASS) {
> -		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> +		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> +			return dg2_rcs_offsets;
> +		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12,
> 50))
>  			return xehp_rcs_offsets;
>  		else if (GRAPHICS_VER(engine->i915) >= 12)
>  			return gen12_rcs_offsets;
> @@ -554,7 +633,9 @@ static const u8 *reg_offsets(const struct
> intel_engine_cs *engine)
>  		else
>  			return gen8_rcs_offsets;
>  	} else {
> -		if (GRAPHICS_VER(engine->i915) >= 12)
> +		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> +			return dg2_xcs_offsets;
> +		else if (GRAPHICS_VER(engine->i915) >= 12)
>  			return gen12_xcs_offsets;
>  		else if (GRAPHICS_VER(engine->i915) >= 9)
>  			return gen9_xcs_offsets;

  reply	other threads:[~2021-08-25  0:03 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-05 16:36 [Intel-gfx] [PATCH v5 0/9] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 1/9] drm/i915/dg2: Add support for new DG2-G11 revid 0x5 Matt Roper
2021-08-05 16:48   ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 2/9] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-08-11  0:18   ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 3/9] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 4/9] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-08-05 17:26   ` Lucas De Marchi
2021-08-06 17:29     ` [Intel-gfx] [PATCH v5.1 " Matt Roper
2021-08-11  0:17       ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 5/9] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-08-12 22:49   ` Souza, Jose
2021-08-12 23:14     ` Lucas De Marchi
2021-08-12 23:18       ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 6/9] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 7/9] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-08-25  0:03   ` Yokoyama, Caz [this message]
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 8/9] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-08-18 21:56   ` Srivatsa, Anusha
2021-08-23  9:26   ` Tvrtko Ursulin
2021-08-24  4:06     ` Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 9/9] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-08-10 21:51   ` Souza, Jose
2021-08-05 17:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev9) Patchwork
2021-08-05 17:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-05 18:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-06  7:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-08-06 18:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev10) Patchwork
2021-08-06 18:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-06 18:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-06 23:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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