From: Lucas De Marchi <lucas.demarchi@intel.com>
To: "Souza, Jose" <jose.souza@intel.com>
Cc: "Roper, Matthew D" <matthew.d.roper@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Subject: Re: [Intel-gfx] [PATCH v5 5/9] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP
Date: Thu, 12 Aug 2021 16:18:14 -0700 [thread overview]
Message-ID: <20210812231814.7yexelqyiprus4jk@ldmartin-desk2> (raw)
In-Reply-To: <20210812231411.toiiqfiw2r5mga5f@ldmartin-desk2>
On Thu, Aug 12, 2021 at 04:14:11PM -0700, Lucas De Marchi wrote:
>On Thu, Aug 12, 2021 at 03:49:17PM -0700, Jose Souza wrote:
>>On Thu, 2021-08-05 at 09:36 -0700, Matt Roper wrote:
>>>From: Lucas De Marchi <lucas.demarchi@intel.com>
>>>
>>>Instead of maintaining the same if ladder in 3 different places, add a
>>>function to read RP_STATE_CAP.
>>>
>>
>>gt_perf_status looks a good next candidate to have the same handling as rp_state_cap
>
>I was actually hoping to remove it:
>https://patchwork.freedesktop.org/patch/397131/
>
>Discussion there stalled though. +Joonas
and btw, the main reason for that patch is xehpsdv: we shouldn't
access any register from the MCHBAR mirror
Lucas De Marchi
next prev parent reply other threads:[~2021-08-12 23:18 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-05 16:36 [Intel-gfx] [PATCH v5 0/9] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 1/9] drm/i915/dg2: Add support for new DG2-G11 revid 0x5 Matt Roper
2021-08-05 16:48 ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 2/9] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-08-11 0:18 ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 3/9] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 4/9] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-08-05 17:26 ` Lucas De Marchi
2021-08-06 17:29 ` [Intel-gfx] [PATCH v5.1 " Matt Roper
2021-08-11 0:17 ` Lucas De Marchi
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 5/9] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-08-12 22:49 ` Souza, Jose
2021-08-12 23:14 ` Lucas De Marchi
2021-08-12 23:18 ` Lucas De Marchi [this message]
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 6/9] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 7/9] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-08-25 0:03 ` Yokoyama, Caz
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 8/9] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-08-18 21:56 ` Srivatsa, Anusha
2021-08-23 9:26 ` Tvrtko Ursulin
2021-08-24 4:06 ` Matt Roper
2021-08-05 16:36 ` [Intel-gfx] [PATCH v5 9/9] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-08-10 21:51 ` Souza, Jose
2021-08-05 17:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev9) Patchwork
2021-08-05 17:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-05 18:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-06 7:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-08-06 18:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev10) Patchwork
2021-08-06 18:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-06 18:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-06 23:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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