* [Intel-gfx] [PATCH v2 0/1] Adding definitions for VRR registers and bitfields
@ 2020-02-14 12:27 Aditya Swarup
2020-02-14 12:27 ` [Intel-gfx] [PATCH v2 1/1] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Aditya Swarup @ 2020-02-14 12:27 UTC (permalink / raw)
To: intel-gfx
Add definitions for configuring VRR registers for TGL.
Aditya Swarup (1):
drm/i915/tgl: Add definitions for VRR registers and bits
drivers/gpu/drm/i915/i915_reg.h | 90 +++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
--
2.25.0
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^ permalink raw reply [flat|nested] 5+ messages in thread* [Intel-gfx] [PATCH v2 1/1] drm/i915/tgl: Add definitions for VRR registers and bits 2020-02-14 12:27 [Intel-gfx] [PATCH v2 0/1] Adding definitions for VRR registers and bitfields Aditya Swarup @ 2020-02-14 12:27 ` Aditya Swarup 2020-02-27 23:07 ` Manasi Navare 2020-02-14 16:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Adding definitions for VRR registers and bitfields (rev2) Patchwork 2020-02-17 20:35 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2 siblings, 1 reply; 5+ messages in thread From: Aditya Swarup @ 2020-02-14 12:27 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Add definitions for registers grouped under Transcoder VRR function with necessary bitfields. Bspec: 49268 v2: Use REG_GENMASK, correct tabs/space indentation and move the definitions near the transcoder section.(Jani) Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 90 +++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b09c1d6dc0aa..ee169af7dda2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4319,6 +4319,96 @@ enum { #define EXITLINE_MASK REG_GENMASK(12, 0) #define EXITLINE_SHIFT 0 +/* VRR registers */ +#define _TRANS_VRR_CTL_A 0x60420 +#define _TRANS_VRR_CTL_B 0x61420 +#define _TRANS_VRR_CTL_C 0x62420 +#define _TRANS_VRR_CTL_D 0x63420 +#define TRANS_VRR_CTL(tran) _MMIO_TRANS2(tran, _TRANS_VRR_CTL_A) +#define VRR_CTL_VRR_ENABLE REG_BIT(31) +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +#define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3) +#define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0) + +#define _TRANS_VRR_VMAX_A 0x60424 +#define _TRANS_VRR_VMAX_B 0x61424 +#define _TRANS_VRR_VMAX_C 0x62424 +#define _TRANS_VRR_VMAX_D 0x63424 +#define TRANS_VRR_VMAX(tran) _MMIO_TRANS2(tran, _TRANS_VRR_VMAX_A) +#define VRR_VMAX_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_VMIN_A 0x60434 +#define _TRANS_VRR_VMIN_B 0x61434 +#define _TRANS_VRR_VMIN_C 0x62434 +#define _TRANS_VRR_VMIN_D 0x63434 +#define TRANS_VRR_VMIN(tran) _MMIO_TRANS2(tran, _TRANS_VRR_VMIN_A) +#define TRANS_VRR_VMIN_MASK REG_GENMASK(15, 0) + +#define _TRANS_VRR_VMAXSHIFT_A 0x60428 +#define _TRANS_VRR_VMAXSHIFT_B 0x61428 +#define _TRANS_VRR_VMAXSHIFT_C 0x62428 +#define _TRANS_VRR_VMAXSHIFT_D 0x63428 +#define TRANS_VRR_VMAXSHIFT(tran) _MMIO_TRANS2(tran, \ + _TRANS_VRR_VMAXSHIFT_A) +#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) +#define VRR_VMAXSHIFT_DEC REG_BIT(16) +#define TRANS_VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) + +#define _TRANS_VRR_STATUS_A 0x6042C +#define _TRANS_VRR_STATUS_B 0x6142C +#define _TRANS_VRR_STATUS_C 0x6242C +#define _TRANS_VRR_STATUS_D 0x6342C +#define TRANS_VRR_STATUS(tran) _MMIO_TRANS2(tran, _TRANS_VRR_STATUS_A) +#define VRR_STATUS_VMAX_REACHED REG_BIT(31) +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) +#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) +#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) +#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) +#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) +#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) +#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) +#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) +#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) +#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) + +#define _TRANS_VRR_VTOTAL_PREV_A 0x60480 +#define _TRANS_VRR_VTOTAL_PREV_B 0x61480 +#define _TRANS_VRR_VTOTAL_PREV_C 0x62480 +#define _TRANS_VRR_VTOTAL_PREV_D 0x63480 +#define TRANS_VRR_VTOTAL_PREV(tran) _MMIO_TRANS2(tran, \ + _TRANS_VRR_VTOTAL_PREV_A) +#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) +#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) +#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) +#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_FLIPLINE_A 0x60438 +#define _TRANS_VRR_FLIPLINE_B 0x61438 +#define _TRANS_VRR_FLIPLINE_C 0x62438 +#define _TRANS_VRR_FLIPLINE_D 0x63438 +#define TRANS_VRR_FLIPLINE(tran) _MMIO_TRANS2(tran, \ + _TRANS_VRR_FLIPLINE_A) +#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_STATUS2_A 0x6043C +#define _TRANS_VRR_STATUS2_B 0x6143C +#define _TRANS_VRR_STATUS2_C 0x6243C +#define _TRANS_VRR_STATUS2_D 0x6343C +#define TRANS_VRR_STATUS2(tran) _MMIO_TRANS2(tran, _TRANS_VRR_STATUS2_A) +#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) + +#define _TRANS_PUSH_A 0x60A70 +#define _TRANS_PUSH_B 0x61A70 +#define _TRANS_PUSH_C 0x62A70 +#define _TRANS_PUSH_D 0x63A70 +#define TRANS_PUSH(tran) _MMIO_TRANS2(tran, _TRANS_PUSH_A) +#define TRANS_PUSH_EN REG_BIT(31) +#define TRANS_PUSH_SEND REG_BIT(30) + /* * HSW+ eDP PSR registers * -- 2.25.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/1] drm/i915/tgl: Add definitions for VRR registers and bits 2020-02-14 12:27 ` [Intel-gfx] [PATCH v2 1/1] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup @ 2020-02-27 23:07 ` Manasi Navare 0 siblings, 0 replies; 5+ messages in thread From: Manasi Navare @ 2020-02-27 23:07 UTC (permalink / raw) To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx On Fri, Feb 14, 2020 at 04:27:51AM -0800, Aditya Swarup wrote: > Add definitions for registers grouped under Transcoder VRR function > with necessary bitfields. > > Bspec: 49268 > > v2: Use REG_GENMASK, correct tabs/space indentation and move the > definitions near the transcoder section.(Jani) > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 90 +++++++++++++++++++++++++++++++++ > 1 file changed, 90 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b09c1d6dc0aa..ee169af7dda2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4319,6 +4319,96 @@ enum { > #define EXITLINE_MASK REG_GENMASK(12, 0) > #define EXITLINE_SHIFT 0 > > +/* VRR registers */ > +#define _TRANS_VRR_CTL_A 0x60420 > +#define _TRANS_VRR_CTL_B 0x61420 > +#define _TRANS_VRR_CTL_C 0x62420 > +#define _TRANS_VRR_CTL_D 0x63420 > +#define TRANS_VRR_CTL(tran) _MMIO_TRANS2(tran, _TRANS_VRR_CTL_A) > +#define VRR_CTL_VRR_ENABLE REG_BIT(31) > +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) > +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) > +#define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3) > +#define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0) > + > +#define _TRANS_VRR_VMAX_A 0x60424 > +#define _TRANS_VRR_VMAX_B 0x61424 > +#define _TRANS_VRR_VMAX_C 0x62424 > +#define _TRANS_VRR_VMAX_D 0x63424 > +#define TRANS_VRR_VMAX(tran) _MMIO_TRANS2(tran, _TRANS_VRR_VMAX_A) > +#define VRR_VMAX_MASK REG_GENMASK(19, 0) > + > +#define _TRANS_VRR_VMIN_A 0x60434 > +#define _TRANS_VRR_VMIN_B 0x61434 > +#define _TRANS_VRR_VMIN_C 0x62434 > +#define _TRANS_VRR_VMIN_D 0x63434 > +#define TRANS_VRR_VMIN(tran) _MMIO_TRANS2(tran, _TRANS_VRR_VMIN_A) > +#define TRANS_VRR_VMIN_MASK REG_GENMASK(15, 0) Just use VRR_VMIN_MASK like VRR_CTL_ and VRR_VMAX_MASK > + > +#define _TRANS_VRR_VMAXSHIFT_A 0x60428 > +#define _TRANS_VRR_VMAXSHIFT_B 0x61428 > +#define _TRANS_VRR_VMAXSHIFT_C 0x62428 > +#define _TRANS_VRR_VMAXSHIFT_D 0x63428 > +#define TRANS_VRR_VMAXSHIFT(tran) _MMIO_TRANS2(tran, \ > + _TRANS_VRR_VMAXSHIFT_A) > +#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) > +#define VRR_VMAXSHIFT_DEC REG_BIT(16) > +#define TRANS_VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) Ditto, why have TRANS_VRR_ why not just VRR_VMAXSHIFT_INC_MASK? Everything else looks good. Regards Manasi > + > +#define _TRANS_VRR_STATUS_A 0x6042C > +#define _TRANS_VRR_STATUS_B 0x6142C > +#define _TRANS_VRR_STATUS_C 0x6242C > +#define _TRANS_VRR_STATUS_D 0x6342C > +#define TRANS_VRR_STATUS(tran) _MMIO_TRANS2(tran, _TRANS_VRR_STATUS_A) > +#define VRR_STATUS_VMAX_REACHED REG_BIT(31) > +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) > +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) > +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) > +#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) > +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) > +#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) > +#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) > +#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) > +#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) > +#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) > +#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) > +#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) > +#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) > + > +#define _TRANS_VRR_VTOTAL_PREV_A 0x60480 > +#define _TRANS_VRR_VTOTAL_PREV_B 0x61480 > +#define _TRANS_VRR_VTOTAL_PREV_C 0x62480 > +#define _TRANS_VRR_VTOTAL_PREV_D 0x63480 > +#define TRANS_VRR_VTOTAL_PREV(tran) _MMIO_TRANS2(tran, \ > + _TRANS_VRR_VTOTAL_PREV_A) > +#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) > +#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) > +#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) > +#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) > + > +#define _TRANS_VRR_FLIPLINE_A 0x60438 > +#define _TRANS_VRR_FLIPLINE_B 0x61438 > +#define _TRANS_VRR_FLIPLINE_C 0x62438 > +#define _TRANS_VRR_FLIPLINE_D 0x63438 > +#define TRANS_VRR_FLIPLINE(tran) _MMIO_TRANS2(tran, \ > + _TRANS_VRR_FLIPLINE_A) > +#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) > + > +#define _TRANS_VRR_STATUS2_A 0x6043C > +#define _TRANS_VRR_STATUS2_B 0x6143C > +#define _TRANS_VRR_STATUS2_C 0x6243C > +#define _TRANS_VRR_STATUS2_D 0x6343C > +#define TRANS_VRR_STATUS2(tran) _MMIO_TRANS2(tran, _TRANS_VRR_STATUS2_A) > +#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) > + > +#define _TRANS_PUSH_A 0x60A70 > +#define _TRANS_PUSH_B 0x61A70 > +#define _TRANS_PUSH_C 0x62A70 > +#define _TRANS_PUSH_D 0x63A70 > +#define TRANS_PUSH(tran) _MMIO_TRANS2(tran, _TRANS_PUSH_A) > +#define TRANS_PUSH_EN REG_BIT(31) > +#define TRANS_PUSH_SEND REG_BIT(30) > + > /* > * HSW+ eDP PSR registers > * > -- > 2.25.0 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Adding definitions for VRR registers and bitfields (rev2) 2020-02-14 12:27 [Intel-gfx] [PATCH v2 0/1] Adding definitions for VRR registers and bitfields Aditya Swarup 2020-02-14 12:27 ` [Intel-gfx] [PATCH v2 1/1] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup @ 2020-02-14 16:10 ` Patchwork 2020-02-17 20:35 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2020-02-14 16:10 UTC (permalink / raw) To: Aditya Swarup; +Cc: intel-gfx == Series Details == Series: Adding definitions for VRR registers and bitfields (rev2) URL : https://patchwork.freedesktop.org/series/73398/ State : success == Summary == CI Bug Log - changes from CI_DRM_7939 -> Patchwork_16572 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/index.html Known issues ------------ Here are the changes found in Patchwork_16572 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_close_race@basic-threads: - fi-byt-n2820: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/fi-byt-n2820/igt@gem_close_race@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/fi-byt-n2820/igt@gem_close_race@basic-threads.html #### Possible fixes #### * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][3] ([fdo#108569]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/fi-icl-y/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/fi-icl-y/igt@i915_selftest@live_execlists.html #### Warnings #### * igt@gem_close_race@basic-threads: - fi-byt-j1900: [INCOMPLETE][5] ([i915#45]) -> [TIMEOUT][6] ([fdo#112271] / [i915#1084] / [i915#816]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/fi-byt-j1900/igt@gem_close_race@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/fi-byt-j1900/igt@gem_close_race@basic-threads.html * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][7] ([i915#579]) -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (44 -> 45) ------------------------------ Additional (7): fi-hsw-peppy fi-glk-dsi fi-ivb-3770 fi-icl-u3 fi-bsw-kefka fi-skl-6600u fi-kbl-r Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7939 -> Patchwork_16572 CI-20190529: 20190529 CI_DRM_7939: cceb0c30a34af6ca96e35211ecdc5ca198d44e7e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5441: 534ca091fe4ffed916752165bc5becd7ff56cd84 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16572: b9a4767fb86a5f2e7c8d0f773961a3cfb3d0ce67 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b9a4767fb86a drm/i915/tgl: Add definitions for VRR registers and bits == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Adding definitions for VRR registers and bitfields (rev2) 2020-02-14 12:27 [Intel-gfx] [PATCH v2 0/1] Adding definitions for VRR registers and bitfields Aditya Swarup 2020-02-14 12:27 ` [Intel-gfx] [PATCH v2 1/1] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup 2020-02-14 16:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Adding definitions for VRR registers and bitfields (rev2) Patchwork @ 2020-02-17 20:35 ` Patchwork 2 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2020-02-17 20:35 UTC (permalink / raw) To: Aditya Swarup; +Cc: intel-gfx == Series Details == Series: Adding definitions for VRR registers and bitfields (rev2) URL : https://patchwork.freedesktop.org/series/73398/ State : success == Summary == CI Bug Log - changes from CI_DRM_7939_full -> Patchwork_16572_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_16572_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_busy@close-race: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] ([i915#977]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-tglb5/igt@gem_busy@close-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-tglb6/igt@gem_busy@close-race.html * igt@gem_caching@writes: - shard-hsw: [PASS][3] -> [FAIL][4] ([i915#694]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-hsw1/igt@gem_caching@writes.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-hsw7/igt@gem_caching@writes.html * igt@gem_ctx_isolation@vcs0-s3: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#69]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-skl10/igt@gem_ctx_isolation@vcs0-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-skl2/igt@gem_ctx_isolation@vcs0-s3.html * igt@gem_ctx_isolation@vecs0-s3: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-apl8/igt@gem_ctx_isolation@vecs0-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-apl8/igt@gem_ctx_isolation@vecs0-s3.html * igt@gem_ctx_shared@exec-shared-gtt-blt: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#616]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-tglb7/igt@gem_ctx_shared@exec-shared-gtt-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-tglb7/igt@gem_ctx_shared@exec-shared-gtt-blt.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([i915#677]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb7/igt@gem_exec_schedule@pi-distinct-iova-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb8/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb1/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#644]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-glk4/igt@gem_ppgtt@flink-and-close-vma-leak.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@i915_pm_rpm@modeset-stress-extra-wait: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#118] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-glk4/igt@i915_pm_rpm@modeset-stress-extra-wait.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-glk8/igt@i915_pm_rpm@modeset-stress-extra-wait.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-hsw: [PASS][21] -> [FAIL][22] ([i915#46]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-hsw1/igt@kms_flip@2x-flip-vs-expired-vblank.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-hsw1/igt@kms_flip@2x-flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#123] / [i915#69]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-skl7/igt@kms_frontbuffer_tracking@psr-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-skl1/igt@kms_frontbuffer_tracking@psr-suspend.html * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([IGT#6]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-skl6/igt@kms_plane_multiple@atomic-pipe-c-tiling-yf.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-skl5/igt@kms_plane_multiple@atomic-pipe-c-tiling-yf.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][27] -> [FAIL][28] ([i915#173]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb6/igt@kms_psr@no_drrs.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html * igt@kms_setmode@basic: - shard-kbl: [PASS][31] -> [FAIL][32] ([i915#31]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-kbl7/igt@kms_setmode@basic.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-kbl1/igt@kms_setmode@basic.html * igt@perf_pmu@busy-accuracy-2-vcs1: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#112080]) +8 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb4/igt@perf_pmu@busy-accuracy-2-vcs1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb6/igt@perf_pmu@busy-accuracy-2-vcs1.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109276]) +9 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html #### Possible fixes #### * igt@gem_busy@extended-parallel-vcs1: - shard-iclb: [SKIP][37] ([fdo#112080]) -> [PASS][38] +7 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb5/igt@gem_busy@extended-parallel-vcs1.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb4/igt@gem_busy@extended-parallel-vcs1.html * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +7 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-kbl6/igt@gem_ctx_isolation@rcs0-s3.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html * {igt@gem_ctx_persistence@close-replace-race}: - shard-glk: [FAIL][41] -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-glk8/igt@gem_ctx_persistence@close-replace-race.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-glk7/igt@gem_ctx_persistence@close-replace-race.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [SKIP][43] ([fdo#109276]) -> [PASS][44] +18 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb6/igt@gem_exec_schedule@independent-bsd2.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb1/igt@gem_exec_schedule@independent-bsd2.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [SKIP][45] ([fdo#112146]) -> [PASS][46] +4 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb6/igt@gem_exec_schedule@reorder-wide-bsd.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +5 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-apl6/igt@gem_workarounds@suspend-resume-context.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-apl4/igt@gem_workarounds@suspend-resume-context.html * igt@kms_flip@plain-flip-fb-recreate: - shard-kbl: [FAIL][49] ([i915#34]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-kbl4/igt@kms_flip@plain-flip-fb-recreate.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-kbl6/igt@kms_flip@plain-flip-fb-recreate.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu: - shard-tglb: [SKIP][51] ([i915#668]) -> [PASS][52] +8 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html * {igt@kms_hdr@bpc-switch-dpms}: - shard-skl: [FAIL][53] ([i915#1188]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][55] ([fdo#108145] / [i915#265]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][57] ([fdo#108145]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-glk: [FAIL][59] ([i915#899]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-x.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-x.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +3 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-apl: [FAIL][63] ([i915#31]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-apl1/igt@kms_setmode@basic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-apl8/igt@kms_setmode@basic.html #### Warnings #### * igt@gem_ctx_isolation@vcs1-nonpriv-switch: - shard-iclb: [SKIP][65] ([fdo#112080]) -> [FAIL][66] ([IGT#28]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html * igt@gem_tiled_blits@interruptible: - shard-hsw: [FAIL][67] ([i915#818]) -> [FAIL][68] ([i915#694]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7939/shard-hsw8/igt@gem_tiled_blits@interruptible.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/shard-hsw5/igt@gem_tiled_blits@interruptible.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28 [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#616]: https://gitlab.freedesktop.org/drm/intel/issues/616 [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818 [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [i915#977]: https://gitlab.freedesktop.org/drm/intel/issues/977 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7939 -> Patchwork_16572 CI-20190529: 20190529 CI_DRM_7939: cceb0c30a34af6ca96e35211ecdc5ca198d44e7e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5441: 534ca091fe4ffed916752165bc5becd7ff56cd84 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16572: b9a4767fb86a5f2e7c8d0f773961a3cfb3d0ce67 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16572/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-02-27 23:05 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-14 12:27 [Intel-gfx] [PATCH v2 0/1] Adding definitions for VRR registers and bitfields Aditya Swarup 2020-02-14 12:27 ` [Intel-gfx] [PATCH v2 1/1] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup 2020-02-27 23:07 ` Manasi Navare 2020-02-14 16:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Adding definitions for VRR registers and bitfields (rev2) Patchwork 2020-02-17 20:35 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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