* [Intel-gfx] [PATCH v5 1/7] drm/amd/display: Align macro name as per DP spec
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
@ 2020-03-16 10:37 ` Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 2/7] drm/dp: get/set phy compliance pattern Animesh Manna
` (12 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Animesh Manna @ 2020-03-16 10:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Deucher, Harry Wentland
[Why]:
Aligh with DP spec wanted to follow same naming convention.
[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
include/drm/drm_dp_helper.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9553755be286..324a7bf81446 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2530,7 +2530,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
/* get phy test pattern and pattern parameters from DP receiver */
core_link_read_dpcd(
link,
- DP_TEST_PHY_PATTERN,
+ DP_PHY_TEST_PATTERN,
&dpcd_test_pattern.raw,
sizeof(dpcd_test_pattern));
core_link_read_dpcd(
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c6119e4c169a..10ddb622a73e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -701,7 +701,7 @@
# define DP_TEST_CRC_SUPPORTED (1 << 5)
# define DP_TEST_COUNT_MASK 0xf
-#define DP_TEST_PHY_PATTERN 0x248
+#define DP_PHY_TEST_PATTERN 0x248
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
--
2.24.0
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [PATCH v5 2/7] drm/dp: get/set phy compliance pattern
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 1/7] drm/amd/display: Align macro name as per DP spec Animesh Manna
@ 2020-03-16 10:37 ` Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 3/7] drm/i915/dp: Made intel_dp_adjust_train() non-static Animesh Manna
` (11 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Animesh Manna @ 2020-03-16 10:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Harry Wentland
During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.
v2: As per review feedback from Manasi on RFC version,
- added dp revision as function argument in set_phy_pattern api.
- used int for link_rate and u8 for lane_count to align with existing code.
v3: As per review feedback from Harry,
- used sizeof() instead of magic number.
- corrected kernel-doc for drm_dp_phy_test_params structure.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 94 +++++++++++++++++++++++++++++++++
include/drm/drm_dp_helper.h | 31 +++++++++++
2 files changed, 125 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index c6fbe6e6bc9d..28e59d1ffa93 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1533,3 +1533,97 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
return num_bpc;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data)
+{
+ int err;
+ u8 rate, lanes;
+
+ err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
+ if (err < 0)
+ return err;
+ data->link_rate = drm_dp_bw_code_to_link_rate(rate);
+
+ err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
+ if (err < 0)
+ return err;
+ data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
+
+ if (lanes & DP_ENHANCED_FRAME_CAP)
+ data->enhanced_frame_cap = true;
+
+ err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
+ if (err < 0)
+ return err;
+
+ switch (data->phy_pattern) {
+ case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+ err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+ &data->custom80, sizeof(data->custom80));
+ if (err < 0)
+ return err;
+
+ break;
+ case DP_PHY_TEST_PATTERN_CP2520:
+ err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+ &data->hbr2_reset,
+ sizeof(data->hbr2_reset));
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data, u8 dp_rev)
+{
+ int err, i;
+ u8 link_config[2];
+ u8 test_pattern;
+
+ link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+ link_config[1] = data->num_lanes;
+ if (data->enhanced_frame_cap)
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+ if (err < 0)
+ return err;
+
+ test_pattern = data->phy_pattern;
+ if (dp_rev < 0x12) {
+ test_pattern = (test_pattern << 2) &
+ DP_LINK_QUAL_PATTERN_11_MASK;
+ err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
+ test_pattern);
+ if (err < 0)
+ return err;
+ } else {
+ for (i = 0; i < data->num_lanes; i++) {
+ err = drm_dp_dpcd_writeb(aux,
+ DP_LINK_QUAL_LANE0_SET + i,
+ test_pattern);
+ if (err < 0)
+ return err;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 10ddb622a73e..e22cf5b2f174 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -702,6 +702,15 @@
# define DP_TEST_COUNT_MASK 0xf
#define DP_PHY_TEST_PATTERN 0x248
+# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
+# define DP_PHY_TEST_PATTERN_NONE 0x0
+# define DP_PHY_TEST_PATTERN_D10_2 0x1
+# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
+# define DP_PHY_TEST_PATTERN_PRBS7 0x3
+# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
+# define DP_PHY_TEST_PATTERN_CP2520 0x5
+
+#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
@@ -1598,4 +1607,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
#endif
+/**
+ * struct drm_dp_phy_test_params - DP Phy Compliance parameters
+ * @link_rate: Requested Link rate from DPCD 0x219
+ * @num_lanes: Number of lanes requested by sing through DPCD 0x220
+ * @phy_pattern: DP Phy test pattern from DPCD 0x248
+ * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
+ * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
+ * @enhanced_frame_cap: flag for enhanced frame capability.
+ */
+struct drm_dp_phy_test_params {
+ int link_rate;
+ u8 num_lanes;
+ u8 phy_pattern;
+ u8 hbr2_reset[2];
+ u8 custom80[10];
+ bool enhanced_frame_cap;
+};
+
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data);
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data, u8 dp_rev);
#endif /* _DRM_DP_HELPER_H_ */
--
2.24.0
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [PATCH v5 3/7] drm/i915/dp: Made intel_dp_adjust_train() non-static
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 1/7] drm/amd/display: Align macro name as per DP spec Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 2/7] drm/dp: get/set phy compliance pattern Animesh Manna
@ 2020-03-16 10:37 ` Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 4/7] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
` (10 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Animesh Manna @ 2020-03-16 10:37 UTC (permalink / raw)
To: intel-gfx
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so have
made non-static function.
No functional change.
v1: initial patch.
v2:
- used "intel_dp" prefix in function name. (Jani)
- used array notation instead pointer for link_status. (Ville)
v3: Scrapped the initial patch, modified commit description accordingly.
- made non-static function and used intel_dp prefix. (Jani, Manasi)
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 9 ++++-----
drivers/gpu/drm/i915/display/intel_dp_link_training.h | 4 ++++
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a7defb37ab00..e4f1843170b7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,9 +34,8 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
link_status[3], link_status[4], link_status[5]);
}
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
- const u8 link_status[DP_LINK_STATUS_SIZE])
+void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+ const u8 link_status[DP_LINK_STATUS_SIZE])
{
u8 v = 0;
u8 p = 0;
@@ -219,7 +218,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
/* Update training set as requested by target */
- intel_get_adjust_train(intel_dp, link_status);
+ intel_dp_get_adjust_train(intel_dp, link_status);
if (!intel_dp_update_link_train(intel_dp)) {
drm_err(&i915->drm,
"failed to update link training\n");
@@ -338,7 +337,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
}
/* Update training set as requested by target */
- intel_get_adjust_train(intel_dp, link_status);
+ intel_dp_get_adjust_train(intel_dp, link_status);
if (!intel_dp_update_link_train(intel_dp)) {
drm_err(&i915->drm,
"failed to update link training\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 174566adcc92..01f1dabbb060 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -6,8 +6,12 @@
#ifndef __INTEL_DP_LINK_TRAINING_H__
#define __INTEL_DP_LINK_TRAINING_H__
+#include <drm/drm_dp_helper.h>
+
struct intel_dp;
+void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+ const u8 link_status[DP_LINK_STATUS_SIZE]);
void intel_dp_start_link_train(struct intel_dp *intel_dp);
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
--
2.24.0
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [PATCH v5 4/7] drm/i915/dp: Preparation for DP phy compliance auto test
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (2 preceding siblings ...)
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 3/7] drm/i915/dp: Made intel_dp_adjust_train() non-static Animesh Manna
@ 2020-03-16 10:37 ` Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 5/7] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna
` (9 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Animesh Manna @ 2020-03-16 10:37 UTC (permalink / raw)
To: intel-gfx
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 24 +++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5e00e611f077..42d0b102c2cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1238,6 +1238,7 @@ struct intel_dp_compliance_data {
u8 video_pattern;
u16 hdisplay, vdisplay;
u8 bpc;
+ struct drm_dp_phy_test_params phytest;
};
struct intel_dp_compliance {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0a417cd2af2b..16a4a48c8168 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5001,9 +5001,33 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
return test_result;
}
+static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
+{
+ struct drm_dp_phy_test_params *data =
+ &intel_dp->compliance.test_data.phytest;
+
+ if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
+ DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+ return DP_TEST_NAK;
+ }
+
+ /*
+ * link_mst is set to false to avoid executing mst related code
+ * during compliance testing.
+ */
+ intel_dp->link_mst = false;
+
+ return DP_TEST_ACK;
+}
+
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
u8 test_result = DP_TEST_NAK;
+
+ test_result = intel_dp_prepare_phytest(intel_dp);
+ if (test_result != DP_TEST_ACK)
+ DRM_ERROR("Phy test preparation failed\n");
+
return test_result;
}
--
2.24.0
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [PATCH v5 5/7] drm/i915/dp: Add debugfs entry for DP phy compliance
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (3 preceding siblings ...)
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 4/7] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
@ 2020-03-16 10:37 ` Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register Animesh Manna
` (8 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Animesh Manna @ 2020-03-16 10:37 UTC (permalink / raw)
To: intel-gfx
These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 1e6eb7f2f72d..ab20b7ea26f7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1326,6 +1326,16 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
intel_dp->compliance.test_data.vdisplay);
seq_printf(m, "bpc: %u\n",
intel_dp->compliance.test_data.bpc);
+ } else if (intel_dp->compliance.test_type ==
+ DP_TEST_LINK_PHY_TEST_PATTERN) {
+ seq_printf(m, "pattern: %d\n",
+ intel_dp->compliance.test_data.phytest.phy_pattern);
+ seq_printf(m, "Number of lanes: %d\n",
+ intel_dp->compliance.test_data.phytest.num_lanes);
+ seq_printf(m, "Link Rate: %d\n",
+ intel_dp->compliance.test_data.phytest.link_rate);
+ seq_printf(m, "level: %02x\n",
+ intel_dp->train_set[0]);
}
} else
seq_puts(m, "0");
@@ -1358,7 +1368,7 @@ static int i915_displayport_test_type_show(struct seq_file *m, void *data)
if (encoder && connector->status == connector_status_connected) {
intel_dp = enc_to_intel_dp(encoder);
- seq_printf(m, "%02lx", intel_dp->compliance.test_type);
+ seq_printf(m, "%02lx\n", intel_dp->compliance.test_type);
} else
seq_puts(m, "0");
}
--
2.24.0
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (4 preceding siblings ...)
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 5/7] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna
@ 2020-03-16 10:37 ` Animesh Manna
2020-03-17 0:13 ` Manasi Navare
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
` (7 subsequent siblings)
13 siblings, 1 reply; 26+ messages in thread
From: Animesh Manna @ 2020-03-16 10:37 UTC (permalink / raw)
To: intel-gfx
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
v1: Initial patch.
v2: used pipe instead of port in macro definition. [Manasi]
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 309cb7d96b35..e93b90e17573 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9792,6 +9792,26 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A 0x605F0
+#define DDI_DP_COMP_CTL_B 0x615F0
+#define DDI_DP_COMP_CTL(pipe) _MMIO_PORT(pipe, DDI_DP_COMP_CTL_A, \
+ DDI_DP_COMP_CTL_B)
+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A 0x605F4
+#define DDI_DP_COMP_PAT_B 0x615F4
+#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, DDI_DP_COMP_PAT_A, \
+ DDI_DP_COMP_PAT_B) + (i) * 4)
+
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
--
2.24.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register Animesh Manna
@ 2020-03-17 0:13 ` Manasi Navare
2020-03-18 6:35 ` [Intel-gfx] [PATCH v6 " Animesh Manna
0 siblings, 1 reply; 26+ messages in thread
From: Manasi Navare @ 2020-03-17 0:13 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
On Mon, Mar 16, 2020 at 04:07:58PM +0530, Animesh Manna wrote:
> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> compliance pattern.
>
> v1: Initial patch.
> v2: used pipe instead of port in macro definition. [Manasi]
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 309cb7d96b35..e93b90e17573 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9792,6 +9792,26 @@ enum skl_power_gate {
> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>
> +/* DDI DP Compliance Control */
> +#define DDI_DP_COMP_CTL_A 0x605F0
> +#define DDI_DP_COMP_CTL_B 0x615F0
> +#define DDI_DP_COMP_CTL(pipe) _MMIO_PORT(pipe, DDI_DP_COMP_CTL_A, \
> + DDI_DP_COMP_CTL_B)
Since its pipe based, please try to use _MMIO_PIPE2 like in the def
of PIPECONF
> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define DDI_DP_COMP_PAT_A 0x605F4
> +#define DDI_DP_COMP_PAT_B 0x615F4
> +#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, DDI_DP_COMP_PAT_A, \
> + DDI_DP_COMP_PAT_B) + (i) * 4)
Same here , see if you can use _MMIO_PIPE2 and if the offsets work corectly for
all 4 pipes _A, _B, _C, _D
In both cases, might not even need to define _B
Manasi
> +
> /* Sideband Interface (SBI) is programmed indirectly, via
> * SBI_ADDR, which contains the register offset; and SBI_DATA,
> * which contains the payload */
> --
> 2.24.0
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] [PATCH v6 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-17 0:13 ` Manasi Navare
@ 2020-03-18 6:35 ` Animesh Manna
2020-03-18 20:04 ` Manasi Navare
0 siblings, 1 reply; 26+ messages in thread
From: Animesh Manna @ 2020-03-18 6:35 UTC (permalink / raw)
To: intel-gfx
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
v1: Initial patch.
v2: used pipe instead of port in macro definition. [Manasi]
v3: used trans_offset for offset calculation. [Manasi]
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 309cb7d96b35..8b6c9fbfe74b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9792,6 +9792,22 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
+/* DDI DP Compliance Control */
+#define _DDI_DP_COMP_CTL_A 0x605F0
+#define DDI_DP_COMP_CTL(pipe) _MMIO_TRANS2(pipe, _DDI_DP_COMP_CTL_A)
+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define _DDI_DP_COMP_PAT_A 0x605F4
+#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_TRANS2(pipe, _DDI_DP_COMP_PAT_A) + (i) * 4)
+
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
--
2.24.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [PATCH v6 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-18 6:35 ` [Intel-gfx] [PATCH v6 " Animesh Manna
@ 2020-03-18 20:04 ` Manasi Navare
2020-03-19 6:39 ` Manna, Animesh
0 siblings, 1 reply; 26+ messages in thread
From: Manasi Navare @ 2020-03-18 20:04 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
On Wed, Mar 18, 2020 at 12:05:14PM +0530, Animesh Manna wrote:
> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> compliance pattern.
>
> v1: Initial patch.
> v2: used pipe instead of port in macro definition. [Manasi]
> v3: used trans_offset for offset calculation. [Manasi]
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 309cb7d96b35..8b6c9fbfe74b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9792,6 +9792,22 @@ enum skl_power_gate {
> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>
> +/* DDI DP Compliance Control */
> +#define _DDI_DP_COMP_CTL_A 0x605F0
> +#define DDI_DP_COMP_CTL(pipe) _MMIO_TRANS2(pipe, _DDI_DP_COMP_CTL_A)
Any reason why you couldnt use _MMIO_PIPE2 ?
> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define _DDI_DP_COMP_PAT_A 0x605F4
> +#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_TRANS2(pipe, _DDI_DP_COMP_PAT_A) + (i) * 4)
Why cant you use a simple _MMIO_PIPE2(pipe, _DDI_DP_COMP_PAT_A) ?
The offsets are same as the DP_COMP_CTL
Manasi
> +
> /* Sideband Interface (SBI) is programmed indirectly, via
> * SBI_ADDR, which contains the register offset; and SBI_DATA,
> * which contains the payload */
> --
> 2.24.0
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [PATCH v6 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-18 20:04 ` Manasi Navare
@ 2020-03-19 6:39 ` Manna, Animesh
2020-03-19 16:02 ` Ville Syrjälä
0 siblings, 1 reply; 26+ messages in thread
From: Manna, Animesh @ 2020-03-19 6:39 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On 19-03-2020 01:34, Manasi Navare wrote:
> On Wed, Mar 18, 2020 at 12:05:14PM +0530, Animesh Manna wrote:
>> DP_COMP_CTL and DP_COMP_PAT register used to program DP
>> compliance pattern.
>>
>> v1: Initial patch.
>> v2: used pipe instead of port in macro definition. [Manasi]
>> v3: used trans_offset for offset calculation. [Manasi]
>>
>> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 309cb7d96b35..8b6c9fbfe74b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9792,6 +9792,22 @@ enum skl_power_gate {
>> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
>> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>>
>> +/* DDI DP Compliance Control */
>> +#define _DDI_DP_COMP_CTL_A 0x605F0
>> +#define DDI_DP_COMP_CTL(pipe) _MMIO_TRANS2(pipe, _DDI_DP_COMP_CTL_A)
> Any reason why you couldnt use _MMIO_PIPE2 ?
As DP_COMP_CTL is part of transcoder register group, so I choose _MMIO_TRANS2 for calculation. Yes _MMIO_PIPE2 will also work as the offset difference between subsequent pipe is same (0x1000).
If the offset difference of subsequent transcoder register is different from the difference of subsequent pipe register we may have issue that time.
>
>> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
>> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
>> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
>> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
>> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
>> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
>> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
>> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
>> +
>> +/* DDI DP Compliance Pattern */
>> +#define _DDI_DP_COMP_PAT_A 0x605F4
>> +#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_TRANS2(pipe, _DDI_DP_COMP_PAT_A) + (i) * 4)
> Why cant you use a simple _MMIO_PIPE2(pipe, _DDI_DP_COMP_PAT_A) ?
> The offsets are same as the DP_COMP_CTL
Here extra parameter "i" needed for 80 bit custom pattern & as mentioned above DDI_DP_COMP_PAT is also part of transcoder register group,
so used _TRANS2 macro to calculate the offset then convert into mmio_reg.
Regards,
Animesh
>
> Manasi
>
>> +
>> /* Sideband Interface (SBI) is programmed indirectly, via
>> * SBI_ADDR, which contains the register offset; and SBI_DATA,
>> * which contains the payload */
>> --
>> 2.24.0
>>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [PATCH v6 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-19 6:39 ` Manna, Animesh
@ 2020-03-19 16:02 ` Ville Syrjälä
2020-03-19 21:51 ` Manasi Navare
0 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjälä @ 2020-03-19 16:02 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
On Thu, Mar 19, 2020 at 12:09:18PM +0530, Manna, Animesh wrote:
> On 19-03-2020 01:34, Manasi Navare wrote:
> > On Wed, Mar 18, 2020 at 12:05:14PM +0530, Animesh Manna wrote:
> >> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> >> compliance pattern.
> >>
> >> v1: Initial patch.
> >> v2: used pipe instead of port in macro definition. [Manasi]
> >> v3: used trans_offset for offset calculation. [Manasi]
> >>
> >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++
> >> 1 file changed, 16 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 309cb7d96b35..8b6c9fbfe74b 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -9792,6 +9792,22 @@ enum skl_power_gate {
> >> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> >> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
> >>
> >> +/* DDI DP Compliance Control */
> >> +#define _DDI_DP_COMP_CTL_A 0x605F0
> >> +#define DDI_DP_COMP_CTL(pipe) _MMIO_TRANS2(pipe, _DDI_DP_COMP_CTL_A)
> > Any reason why you couldnt use _MMIO_PIPE2 ?
>
> As DP_COMP_CTL is part of transcoder register group, so I choose _MMIO_TRANS2 for calculation. Yes _MMIO_PIPE2 will also work as the offset difference between subsequent pipe is same (0x1000).
The preference is:
1. _MMIO_PIPE()/etc. for evenly spaced things
2. _MMIO_PIPE2()/etc. for regular but not evenly spaced stuff
3. _PICK() where the above two fail
There are probably a few places that do violate that though.
We should probably fix those to not give people the wrong ideas.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [PATCH v6 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-19 16:02 ` Ville Syrjälä
@ 2020-03-19 21:51 ` Manasi Navare
2020-03-24 5:11 ` [Intel-gfx] [PATCH v7 " Animesh Manna
0 siblings, 1 reply; 26+ messages in thread
From: Manasi Navare @ 2020-03-19 21:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Mar 19, 2020 at 06:02:22PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 19, 2020 at 12:09:18PM +0530, Manna, Animesh wrote:
> > On 19-03-2020 01:34, Manasi Navare wrote:
> > > On Wed, Mar 18, 2020 at 12:05:14PM +0530, Animesh Manna wrote:
> > >> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> > >> compliance pattern.
> > >>
> > >> v1: Initial patch.
> > >> v2: used pipe instead of port in macro definition. [Manasi]
> > >> v3: used trans_offset for offset calculation. [Manasi]
> > >>
> > >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> > >> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > >> ---
> > >> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++
> > >> 1 file changed, 16 insertions(+)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > >> index 309cb7d96b35..8b6c9fbfe74b 100644
> > >> --- a/drivers/gpu/drm/i915/i915_reg.h
> > >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> > >> @@ -9792,6 +9792,22 @@ enum skl_power_gate {
> > >> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> > >> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
> > >>
> > >> +/* DDI DP Compliance Control */
> > >> +#define _DDI_DP_COMP_CTL_A 0x605F0
> > >> +#define DDI_DP_COMP_CTL(pipe) _MMIO_TRANS2(pipe, _DDI_DP_COMP_CTL_A)
> > > Any reason why you couldnt use _MMIO_PIPE2 ?
> >
> > As DP_COMP_CTL is part of transcoder register group, so I choose _MMIO_TRANS2 for calculation. Yes _MMIO_PIPE2 will also work as the offset difference between subsequent pipe is same (0x1000).
>
> The preference is:
> 1. _MMIO_PIPE()/etc. for evenly spaced things
> 2. _MMIO_PIPE2()/etc. for regular but not evenly spaced stuff
> 3. _PICK() where the above two fail
>
> There are probably a few places that do violate that though.
> We should probably fix those to not give people the wrong ideas.
>
So here since the offsets are regular, we could just use _MMIO_PIPE for both DP_COMP_CTL
and DP_COMP_PAT?
we could define _A and _B and just use _MMIO_PIPE
Animesh, please try to use this as suggested by Ville.
Regards
Manasi
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] [PATCH v7 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-19 21:51 ` Manasi Navare
@ 2020-03-24 5:11 ` Animesh Manna
2020-03-27 18:45 ` Manasi Navare
0 siblings, 1 reply; 26+ messages in thread
From: Animesh Manna @ 2020-03-24 5:11 UTC (permalink / raw)
To: intel-gfx
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
v1: Initial patch.
v2: used pipe instead of port in macro definition. [Manasi]
v3: used trans_offset for offset calculation. [Manasi]
v4: Used MMIO_PIPE for evenly spaced register offset instead
MMIO_PIPE2. [Ville]
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 309cb7d96b35..465862ed2cf8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9792,6 +9792,24 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
+/* DDI DP Compliance Control */
+#define _DDI_DP_COMP_CTL_A 0x605F0
+#define _DDI_DP_COMP_CTL_B 0x615F0
+#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define _DDI_DP_COMP_PAT_A 0x605F4
+#define _DDI_DP_COMP_PAT_B 0x615F4
+#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
+
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
--
2.24.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-24 5:11 ` [Intel-gfx] [PATCH v7 " Animesh Manna
@ 2020-03-27 18:45 ` Manasi Navare
2020-03-30 4:01 ` Manna, Animesh
0 siblings, 1 reply; 26+ messages in thread
From: Manasi Navare @ 2020-03-27 18:45 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
On Tue, Mar 24, 2020 at 10:41:11AM +0530, Animesh Manna wrote:
> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> compliance pattern.
>
> v1: Initial patch.
> v2: used pipe instead of port in macro definition. [Manasi]
> v3: used trans_offset for offset calculation. [Manasi]
> v4: Used MMIO_PIPE for evenly spaced register offset instead
> MMIO_PIPE2. [Ville]
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 309cb7d96b35..465862ed2cf8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9792,6 +9792,24 @@ enum skl_power_gate {
> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>
> +/* DDI DP Compliance Control */
> +#define _DDI_DP_COMP_CTL_A 0x605F0
> +#define _DDI_DP_COMP_CTL_B 0x615F0
> +#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
This looks good now.
> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define _DDI_DP_COMP_PAT_A 0x605F4
> +#define _DDI_DP_COMP_PAT_B 0x615F4
> +#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
I still dont understand why we need to use that i argument here and why cant just pipe give us the desired offset
with _MMIO_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) ?
IMO we should be able to use the above since even here the registers are evenly offseted (0x605F4, 0x615F4, 0x62F54, 0x63F54)
Regards
Manasi
> +
> /* Sideband Interface (SBI) is programmed indirectly, via
> * SBI_ADDR, which contains the register offset; and SBI_DATA,
> * which contains the payload */
> --
> 2.24.0
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-27 18:45 ` Manasi Navare
@ 2020-03-30 4:01 ` Manna, Animesh
2020-03-31 0:22 ` Manasi Navare
0 siblings, 1 reply; 26+ messages in thread
From: Manna, Animesh @ 2020-03-30 4:01 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On 28-03-2020 00:15, Manasi Navare wrote:
> On Tue, Mar 24, 2020 at 10:41:11AM +0530, Animesh Manna wrote:
>> DP_COMP_CTL and DP_COMP_PAT register used to program DP
>> compliance pattern.
>>
>> v1: Initial patch.
>> v2: used pipe instead of port in macro definition. [Manasi]
>> v3: used trans_offset for offset calculation. [Manasi]
>> v4: Used MMIO_PIPE for evenly spaced register offset instead
>> MMIO_PIPE2. [Ville]
>>
>> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 309cb7d96b35..465862ed2cf8 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9792,6 +9792,24 @@ enum skl_power_gate {
>> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
>> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>>
>> +/* DDI DP Compliance Control */
>> +#define _DDI_DP_COMP_CTL_A 0x605F0
>> +#define _DDI_DP_COMP_CTL_B 0x615F0
>> +#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
> This looks good now.
>
>> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
>> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
>> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
>> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
>> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
>> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
>> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
>> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
>> +
>> +/* DDI DP Compliance Pattern */
>> +#define _DDI_DP_COMP_PAT_A 0x605F4
>> +#define _DDI_DP_COMP_PAT_B 0x615F4
>> +#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
> I still dont understand why we need to use that i argument here and why cant just pipe give us the desired offset
> with _MMIO_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) ?
>
> IMO we should be able to use the above since even here the registers are evenly offseted (0x605F4, 0x615F4, 0x62F54, 0x63F54)
The offset you mentioned above is for respective pipe A,B,C,D. How we can write 80 bit custom pattern in it? For pipe A, need to write 0x605F4, 0x605F8, 0x605FC for writing 80 bit .. rt?
Regards,
Animesh
>
> Regards
> Manasi
>
>> +
>> /* Sideband Interface (SBI) is programmed indirectly, via
>> * SBI_ADDR, which contains the register offset; and SBI_DATA,
>> * which contains the payload */
>> --
>> 2.24.0
>>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/dp: Register definition for DP compliance register
2020-03-30 4:01 ` Manna, Animesh
@ 2020-03-31 0:22 ` Manasi Navare
0 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-03-31 0:22 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
On Mon, Mar 30, 2020 at 09:31:44AM +0530, Manna, Animesh wrote:
>
> On 28-03-2020 00:15, Manasi Navare wrote:
> >On Tue, Mar 24, 2020 at 10:41:11AM +0530, Animesh Manna wrote:
> >>DP_COMP_CTL and DP_COMP_PAT register used to program DP
> >>compliance pattern.
> >>
> >>v1: Initial patch.
> >>v2: used pipe instead of port in macro definition. [Manasi]
> >>v3: used trans_offset for offset calculation. [Manasi]
> >>v4: Used MMIO_PIPE for evenly spaced register offset instead
> >>MMIO_PIPE2. [Ville]
> >>
> >>Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >>Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >>---
> >> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
> >> 1 file changed, 18 insertions(+)
> >>
> >>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>index 309cb7d96b35..465862ed2cf8 100644
> >>--- a/drivers/gpu/drm/i915/i915_reg.h
> >>+++ b/drivers/gpu/drm/i915/i915_reg.h
> >>@@ -9792,6 +9792,24 @@ enum skl_power_gate {
> >> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> >> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
> >>+/* DDI DP Compliance Control */
> >>+#define _DDI_DP_COMP_CTL_A 0x605F0
> >>+#define _DDI_DP_COMP_CTL_B 0x615F0
> >>+#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
> >This looks good now.
> >
> >>+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> >>+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> >>+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> >>+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> >>+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> >>+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> >>+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> >>+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> >>+
> >>+/* DDI DP Compliance Pattern */
> >>+#define _DDI_DP_COMP_PAT_A 0x605F4
> >>+#define _DDI_DP_COMP_PAT_B 0x615F4
> >>+#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
> >I still dont understand why we need to use that i argument here and why cant just pipe give us the desired offset
> >with _MMIO_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) ?
> >
> >IMO we should be able to use the above since even here the registers are evenly offseted (0x605F4, 0x615F4, 0x62F54, 0x63F54)
>
> The offset you mentioned above is for respective pipe A,B,C,D. How we can write 80 bit custom pattern in it? For pipe A, need to write 0x605F4, 0x605F8, 0x605FC for writing 80 bit .. rt?
>
Ah okay its for making sure we write 32 bits at a time, got it thanks.
With that
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> Regards,
> Animesh
>
> >
> >Regards
> >Manasi
> >
> >>+
> >> /* Sideband Interface (SBI) is programmed indirectly, via
> >> * SBI_ADDR, which contains the register offset; and SBI_DATA,
> >> * which contains the payload */
> >>--
> >>2.24.0
> >>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v5 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (5 preceding siblings ...)
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register Animesh Manna
@ 2020-03-16 10:37 ` Animesh Manna
2020-04-06 15:09 ` Manasi Navare
2020-03-16 19:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev7) Patchwork
` (6 subsequent siblings)
13 siblings, 1 reply; 26+ messages in thread
From: Animesh Manna @ 2020-03-16 10:37 UTC (permalink / raw)
To: intel-gfx
This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.
v1: Initial patch.
v2: Fixes added during testing with test-scope. (Khaled/Clint/Manasi)
- pipe used as argument during registers programming instead of port.
- TRANS_CONF must be disable/enable as well during ddi disable/enable.
- harcoded PLTPAT 80 bit custom pattern as the DPR-100 does not set it
in the sink’s DPCDs
- TRANS_DDI_FUNC_CTL DDI_Select (Bits 27:30) need to reset/set during
disable/enable.
v3: used macros instead of numbers and some cosmetic changes. [Manasi]
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 147 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 148 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 16a4a48c8168..8846471a49b8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5020,6 +5020,151 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
return DP_TEST_ACK;
}
+static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_dp_phy_test_params *data =
+ &intel_dp->compliance.test_data.phytest;
+ struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+ enum pipe pipe = crtc->pipe;
+ u32 pattern_val;
+
+ switch (data->phy_pattern) {
+ case DP_PHY_TEST_PATTERN_NONE:
+ DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ break;
+ case DP_PHY_TEST_PATTERN_D10_2:
+ DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
+ break;
+ case DP_PHY_TEST_PATTERN_ERROR_COUNT:
+ DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ DDI_DP_COMP_CTL_ENABLE |
+ DDI_DP_COMP_CTL_SCRAMBLED_0);
+ break;
+ case DP_PHY_TEST_PATTERN_PRBS7:
+ DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
+ break;
+ case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+ /*
+ * FIXME: Ideally pattern should come from DPCD 0x250. As
+ * current firmware of DPR-100 could not set it, so hardcoding
+ * now for complaince test.
+ */
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
+ pattern_val = 0x3e0f83e0;
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+ pattern_val = 0x0f83e0f8;
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+ pattern_val = 0x0000f83e;
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ DDI_DP_COMP_CTL_ENABLE |
+ DDI_DP_COMP_CTL_CUSTOM80);
+ break;
+ case DP_PHY_TEST_PATTERN_CP2520:
+ /*
+ * FIXME: Ideally pattern should come from DPCD 0x24A. As
+ * current firmware of DPR-100 could not set it, so hardcoding
+ * now for complaince test.
+ */
+ DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
+ pattern_val = 0xFB;
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
+ pattern_val);
+ break;
+ default:
+ WARN(1, "Invalid Phy Test Pattern\n");
+ }
+}
+
+static void
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+ enum pipe pipe = crtc->pipe;
+ u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
+
+ trans_ddi_func_ctl_value = intel_de_read(dev_priv,
+ TRANS_DDI_FUNC_CTL(pipe));
+ trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
+ dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
+
+ trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
+ TGL_TRANS_DDI_PORT_MASK);
+ trans_conf_value &= ~PIPECONF_ENABLE;
+ dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
+
+ intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
+ intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
+ trans_ddi_func_ctl_value);
+ intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
+}
+
+static void
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum port port = intel_dig_port->base.port;
+ struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+ enum pipe pipe = crtc->pipe;
+ u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
+
+ trans_ddi_func_ctl_value = intel_de_read(dev_priv,
+ TRANS_DDI_FUNC_CTL(pipe));
+ trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
+ dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
+
+ trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
+ TGL_TRANS_DDI_SELECT_PORT(port);
+ trans_conf_value |= PIPECONF_ENABLE;
+ dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
+
+ intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
+ intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
+ intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
+ trans_ddi_func_ctl_value);
+}
+
+void intel_dp_process_phy_request(struct intel_dp *intel_dp)
+{
+ struct drm_dp_phy_test_params *data =
+ &intel_dp->compliance.test_data.phytest;
+ u8 link_status[DP_LINK_STATUS_SIZE];
+
+ if (!intel_dp_get_link_status(intel_dp, link_status)) {
+ DRM_DEBUG_KMS("failed to get link status\n");
+ return;
+ }
+
+ /* retrieve vswing & pre-emphasis setting */
+ intel_dp_get_adjust_train(intel_dp, link_status);
+
+ intel_dp_autotest_phy_ddi_disable(intel_dp);
+
+ intel_dp_set_signal_levels(intel_dp);
+
+ intel_dp_phy_pattern_update(intel_dp);
+
+ intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
+
+ drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
+ link_status[DP_DPCD_REV]);
+}
+
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
u8 test_result = DP_TEST_NAK;
@@ -5028,6 +5173,8 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
if (test_result != DP_TEST_ACK)
DRM_ERROR("Phy test preparation failed\n");
+ intel_dp_process_phy_request(intel_dp);
+
return test_result;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0c7be8ed1423..0d22a230b32d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -115,6 +115,7 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
bool intel_digital_port_connected(struct intel_encoder *encoder);
+void intel_dp_process_phy_request(struct intel_dp *intel_dp);
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [PATCH v5 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
@ 2020-04-06 15:09 ` Manasi Navare
0 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-04-06 15:09 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
On Mon, Mar 16, 2020 at 04:07:59PM +0530, Animesh Manna wrote:
> This patch process phy compliance request by programming requested
> vswing, pre-emphasis and test pattern.
>
> v1: Initial patch.
> v2: Fixes added during testing with test-scope. (Khaled/Clint/Manasi)
> - pipe used as argument during registers programming instead of port.
> - TRANS_CONF must be disable/enable as well during ddi disable/enable.
> - harcoded PLTPAT 80 bit custom pattern as the DPR-100 does not set it
> in the sink’s DPCDs
> - TRANS_DDI_FUNC_CTL DDI_Select (Bits 27:30) need to reset/set during
> disable/enable.
> v3: used macros instead of numbers and some cosmetic changes. [Manasi]
>
> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Looks good to me,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 147 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> 2 files changed, 148 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 16a4a48c8168..8846471a49b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5020,6 +5020,151 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
> return DP_TEST_ACK;
> }
>
> +static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_dp_phy_test_params *data =
> + &intel_dp->compliance.test_data.phytest;
> + struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> + enum pipe pipe = crtc->pipe;
> + u32 pattern_val;
> +
> + switch (data->phy_pattern) {
> + case DP_PHY_TEST_PATTERN_NONE:
> + DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
> + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
> + break;
> + case DP_PHY_TEST_PATTERN_D10_2:
> + DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
> + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
> + break;
> + case DP_PHY_TEST_PATTERN_ERROR_COUNT:
> + DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
> + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> + DDI_DP_COMP_CTL_ENABLE |
> + DDI_DP_COMP_CTL_SCRAMBLED_0);
> + break;
> + case DP_PHY_TEST_PATTERN_PRBS7:
> + DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
> + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
> + break;
> + case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
> + /*
> + * FIXME: Ideally pattern should come from DPCD 0x250. As
> + * current firmware of DPR-100 could not set it, so hardcoding
> + * now for complaince test.
> + */
> + DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
> + pattern_val = 0x3e0f83e0;
> + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
> + pattern_val = 0x0f83e0f8;
> + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
> + pattern_val = 0x0000f83e;
> + intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
> + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> + DDI_DP_COMP_CTL_ENABLE |
> + DDI_DP_COMP_CTL_CUSTOM80);
> + break;
> + case DP_PHY_TEST_PATTERN_CP2520:
> + /*
> + * FIXME: Ideally pattern should come from DPCD 0x24A. As
> + * current firmware of DPR-100 could not set it, so hardcoding
> + * now for complaince test.
> + */
> + DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
> + pattern_val = 0xFB;
> + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
> + pattern_val);
> + break;
> + default:
> + WARN(1, "Invalid Phy Test Pattern\n");
> + }
> +}
> +
> +static void
> +intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> + enum pipe pipe = crtc->pipe;
> + u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
> +
> + trans_ddi_func_ctl_value = intel_de_read(dev_priv,
> + TRANS_DDI_FUNC_CTL(pipe));
> + trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
> + dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
> +
> + trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
> + TGL_TRANS_DDI_PORT_MASK);
> + trans_conf_value &= ~PIPECONF_ENABLE;
> + dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
> +
> + intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
> + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
> + trans_ddi_func_ctl_value);
> + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
> +}
> +
> +static void
> +intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum port port = intel_dig_port->base.port;
> + struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> + enum pipe pipe = crtc->pipe;
> + u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
> +
> + trans_ddi_func_ctl_value = intel_de_read(dev_priv,
> + TRANS_DDI_FUNC_CTL(pipe));
> + trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
> + dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
> +
> + trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
> + TGL_TRANS_DDI_SELECT_PORT(port);
> + trans_conf_value |= PIPECONF_ENABLE;
> + dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
> +
> + intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
> + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
> + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
> + trans_ddi_func_ctl_value);
> +}
> +
> +void intel_dp_process_phy_request(struct intel_dp *intel_dp)
> +{
> + struct drm_dp_phy_test_params *data =
> + &intel_dp->compliance.test_data.phytest;
> + u8 link_status[DP_LINK_STATUS_SIZE];
> +
> + if (!intel_dp_get_link_status(intel_dp, link_status)) {
> + DRM_DEBUG_KMS("failed to get link status\n");
> + return;
> + }
> +
> + /* retrieve vswing & pre-emphasis setting */
> + intel_dp_get_adjust_train(intel_dp, link_status);
> +
> + intel_dp_autotest_phy_ddi_disable(intel_dp);
> +
> + intel_dp_set_signal_levels(intel_dp);
> +
> + intel_dp_phy_pattern_update(intel_dp);
> +
> + intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
> +
> + drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
> + link_status[DP_DPCD_REV]);
> +}
> +
> static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
> {
> u8 test_result = DP_TEST_NAK;
> @@ -5028,6 +5173,8 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
> if (test_result != DP_TEST_ACK)
> DRM_ERROR("Phy test preparation failed\n");
>
> + intel_dp_process_phy_request(intel_dp);
> +
> return test_result;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 0c7be8ed1423..0d22a230b32d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -115,6 +115,7 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state);
> bool intel_digital_port_connected(struct intel_encoder *encoder);
> +void intel_dp_process_phy_request(struct intel_dp *intel_dp);
>
> static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> {
> --
> 2.24.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev7)
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (6 preceding siblings ...)
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
@ 2020-03-16 19:33 ` Patchwork
2020-03-17 3:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (5 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-03-16 19:33 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DP Phy compliance auto test (rev7)
URL : https://patchwork.freedesktop.org/series/71121/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16976
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/index.html
Known issues
------------
Here are the changes found in Patchwork_16976 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-tgl-y: [FAIL][1] ([CI#94]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][3] ([i915#217]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
Participating hosts (48 -> 40)
------------------------------
Additional (2): fi-skl-6770hq fi-tgl-dsi
Missing (10): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-8700k fi-gdg-551 fi-cfl-8109u fi-skl-lmem fi-bdw-samus fi-byt-clapper fi-skl-6600u
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8137 -> Patchwork_16976
CI-20190529: 20190529
CI_DRM_8137: 5786b5e77cc17a1b494b9bdf3c3f29eedc2e2e7d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5510: e100092d50105463f58db531fa953c70cc58bb10 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16976: 4ad08d0aeb29717115dee440c00328a747dff267 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4ad08d0aeb29 drm/i915/dp: Program vswing, pre-emphasis, test-pattern
4b9c4eccdf1e drm/i915/dp: Register definition for DP compliance register
dd3763085c66 drm/i915/dp: Add debugfs entry for DP phy compliance
36b158155387 drm/i915/dp: Preparation for DP phy compliance auto test
c73615687108 drm/i915/dp: Made intel_dp_adjust_train() non-static
b1d667b9289e drm/dp: get/set phy compliance pattern
8fffd6e04a72 drm/amd/display: Align macro name as per DP spec
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for DP Phy compliance auto test (rev7)
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (7 preceding siblings ...)
2020-03-16 19:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev7) Patchwork
@ 2020-03-17 3:48 ` Patchwork
2020-03-18 8:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev8) Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-03-17 3:48 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DP Phy compliance auto test (rev7)
URL : https://patchwork.freedesktop.org/series/71121/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16976_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16976_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16976_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16976_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_parallel@bcs0-fds:
- shard-kbl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-kbl7/igt@gem_exec_parallel@bcs0-fds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-kbl6/igt@gem_exec_parallel@bcs0-fds.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_preempt_timeout@timeout@rcs0}:
- shard-skl: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-skl9/igt@sysfs_preempt_timeout@timeout@rcs0.html
Known issues
------------
Here are the changes found in Patchwork_16976_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-kbl: [PASS][4] -> [INCOMPLETE][5] ([i915#1402])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-kbl6/igt@gem_ctx_persistence@close-replace-race.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-kbl7/igt@gem_ctx_persistence@close-replace-race.html
- shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#1402])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-skl6/igt@gem_ctx_persistence@close-replace-race.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-skl8/igt@gem_ctx_persistence@close-replace-race.html
- shard-glk: [PASS][8] -> [INCOMPLETE][9] ([i915#1402] / [i915#58] / [k.org#198133])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-glk3/igt@gem_ctx_persistence@close-replace-race.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-glk8/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_exec_schedule@implicit-both-bsd1:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276] / [i915#677])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb4/igt@gem_exec_schedule@implicit-both-bsd1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb8/igt@gem_exec_schedule@implicit-both-bsd1.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#112146]) +4 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb8/igt@gem_exec_schedule@wide-bsd.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_exec_whisper@basic-fds-forked:
- shard-tglb: [PASS][14] -> [INCOMPLETE][15] ([i915#1318] / [i915#1401])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-tglb1/igt@gem_exec_whisper@basic-fds-forked.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-tglb2/igt@gem_exec_whisper@basic-fds-forked.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#644])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-glk4/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][18] -> [INCOMPLETE][19] ([i915#58] / [k.org#198133])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-glk2/igt@gen9_exec_parse@allowed-all.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-glk2/igt@gen9_exec_parse@allowed-all.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-apl6/igt@i915_suspend@sysfs-reader.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-apl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: [PASS][22] -> [FAIL][23] ([i915#34])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][24] -> [FAIL][25] ([i915#1188])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [PASS][26] -> [DMESG-WARN][27] ([i915#180]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][28] -> [SKIP][29] ([fdo#109441]) +3 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-glk: [PASS][30] -> [FAIL][31] ([i915#31])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-glk2/igt@kms_setmode@basic.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-glk2/igt@kms_setmode@basic.html
- shard-kbl: [PASS][32] -> [FAIL][33] ([i915#31])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-kbl7/igt@kms_setmode@basic.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-kbl3/igt@kms_setmode@basic.html
* igt@perf_pmu@init-busy-vcs1:
- shard-iclb: [PASS][34] -> [SKIP][35] ([fdo#112080]) +7 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb1/igt@perf_pmu@init-busy-vcs1.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb3/igt@perf_pmu@init-busy-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][36] -> [SKIP][37] ([fdo#109276]) +19 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][38] ([fdo#110854]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb8/igt@gem_exec_balancer@smoke.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb4/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_parallel@bcs0-fds:
- shard-apl: [FAIL][40] -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-apl6/igt@gem_exec_parallel@bcs0-fds.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-apl8/igt@gem_exec_parallel@bcs0-fds.html
- shard-tglb: [FAIL][42] -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-tglb3/igt@gem_exec_parallel@bcs0-fds.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-tglb7/igt@gem_exec_parallel@bcs0-fds.html
- shard-glk: [FAIL][44] -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-glk8/igt@gem_exec_parallel@bcs0-fds.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-glk9/igt@gem_exec_parallel@bcs0-fds.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [SKIP][46] ([fdo#112080]) -> [PASS][47] +16 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb8/igt@gem_exec_parallel@vcs1-fds.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@implicit-read-write-bsd1:
- shard-iclb: [SKIP][48] ([fdo#109276] / [i915#677]) -> [PASS][49] +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb5/igt@gem_exec_schedule@implicit-read-write-bsd1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb2/igt@gem_exec_schedule@implicit-read-write-bsd1.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [SKIP][50] ([fdo#112146]) -> [PASS][51] +5 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb4/igt@gem_exec_schedule@in-order-bsd.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb8/igt@gem_exec_schedule@in-order-bsd.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [SKIP][52] ([i915#677]) -> [PASS][53] +3 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb1/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb5/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-hsw: [DMESG-WARN][54] ([fdo#111870]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw7/igt@gem_userptr_blits@dmabuf-unsync.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-hsw6/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][56] ([i915#180]) -> [PASS][57] +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][58] ([i915#716]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-skl3/igt@gen9_exec_parse@allowed-single.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-skl10/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc5-dpms:
- shard-iclb: [FAIL][60] ([i915#447]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb6/igt@i915_pm_dc@dc5-dpms.html
* igt@i915_selftest@live@execlists:
- shard-skl: [INCOMPLETE][62] ([i915#656]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-skl3/igt@i915_selftest@live@execlists.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-skl5/igt@i915_selftest@live@execlists.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][64] ([i915#72]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-apl: [DMESG-WARN][66] ([i915#180]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][68] ([fdo#109441]) -> [PASS][69] +3 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][70] ([fdo#109276]) -> [PASS][71] +20 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb8/igt@prime_busy@hang-bsd2.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-iclb2/igt@prime_busy@hang-bsd2.html
* {igt@sysfs_timeslice_duration@timeout@rcs0}:
- shard-skl: [FAIL][72] -> [PASS][73] +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-skl10/igt@sysfs_timeslice_duration@timeout@rcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-skl1/igt@sysfs_timeslice_duration@timeout@rcs0.html
#### Warnings ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-tglb: [INCOMPLETE][74] ([i915#1402]) -> [TIMEOUT][75] ([i915#1340])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-tglb2/igt@gem_ctx_persistence@close-replace-race.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-tglb2/igt@gem_ctx_persistence@close-replace-race.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [SKIP][76] ([i915#468]) -> [FAIL][77] ([i915#454])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-tglb7/igt@i915_pm_dc@dc6-dpms.html
* igt@runner@aborted:
- shard-hsw: ([FAIL][78], [FAIL][79], [FAIL][80], [FAIL][81], [FAIL][82], [FAIL][83], [FAIL][84], [FAIL][85]) ([fdo#111870]) -> ([FAIL][86], [FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94]) ([fdo#111870] / [i915#478])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw6/igt@runner@aborted.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw7/igt@runner@aborted.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw6/igt@runner@aborted.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw2/igt@runner@aborted.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw1/igt@runner@aborted.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw5/igt@runner@aborted.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw5/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw2/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-hsw6/igt@runner@aborted.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-hsw4/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-hsw2/igt@runner@aborted.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-hsw6/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-hsw1/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-hsw1/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-hsw4/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-hsw6/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-hsw6/igt@runner@aborted.html
- shard-kbl: [FAIL][95] ([i915#92]) -> ([FAIL][96], [FAIL][97]) ([i915#1389] / [i915#1402] / [i915#92])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-kbl3/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-kbl4/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-kbl7/igt@runner@aborted.html
- shard-tglb: [FAIL][98] ([i915#1389]) -> [FAIL][99] ([i915#1318])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-tglb2/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-tglb2/igt@runner@aborted.html
- shard-skl: ([FAIL][100], [FAIL][101]) ([i915#69]) -> [FAIL][102] ([i915#1402] / [i915#69])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-skl3/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-skl3/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/shard-skl8/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1318]: https://gitlab.freedesktop.org/drm/intel/issues/1318
[i915#1340]: https://gitlab.freedesktop.org/drm/intel/issues/1340
[i915#1389]: https://gitlab.freedesktop.org/drm/intel/issues/1389
[i915#1401]: https://gitlab.freedesktop.org/drm/intel/issues/1401
[i915#1402]: https://gitlab.freedesktop.org/drm/intel/issues/1402
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8137 -> Patchwork_16976
CI-20190529: 20190529
CI_DRM_8137: 5786b5e77cc17a1b494b9bdf3c3f29eedc2e2e7d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5510: e100092d50105463f58db531fa953c70cc58bb10 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16976: 4ad08d0aeb29717115dee440c00328a747dff267 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16976/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev8)
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (8 preceding siblings ...)
2020-03-17 3:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-03-18 8:01 ` Patchwork
2020-03-18 10:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-03-18 8:01 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DP Phy compliance auto test (rev8)
URL : https://patchwork.freedesktop.org/series/71121/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8145 -> Patchwork_17003
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/index.html
Known issues
------------
Here are the changes found in Patchwork_17003 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@execlists:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] / [i915#656])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/fi-bxt-dsi/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/fi-bxt-dsi/igt@i915_selftest@live@execlists.html
#### Possible fixes ####
* igt@gem_exec_parallel@fds:
- fi-glk-dsi: [INCOMPLETE][3] ([i915#529] / [i915#58] / [k.org#198133]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/fi-glk-dsi/igt@gem_exec_parallel@fds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/fi-glk-dsi/igt@gem_exec_parallel@fds.html
* igt@i915_selftest@live@gem_contexts:
- fi-skl-lmem: [INCOMPLETE][5] ([i915#424]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@hangcheck:
- fi-bwr-2160: [INCOMPLETE][7] ([i915#489]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/fi-bwr-2160/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/fi-bwr-2160/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
[i915#529]: https://gitlab.freedesktop.org/drm/intel/issues/529
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (46 -> 41)
------------------------------
Missing (5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bsw-kefka fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8145 -> Patchwork_17003
CI-20190529: 20190529
CI_DRM_8145: 5e893da0b8c2bfec015c5eaa7981e1ffab1d7c9c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5518: ee05a571255783837b18d626c4dff6cd9613cee2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17003: af8eebf967773625d3357a6a78ab300562b524c9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
af8eebf96777 drm/i915/dp: Program vswing, pre-emphasis, test-pattern
7eec3cbabedf drm/i915/dp: Register definition for DP compliance register
f787b9132698 drm/i915/dp: Add debugfs entry for DP phy compliance
2c884afe7524 drm/i915/dp: Preparation for DP phy compliance auto test
be2a0a183afc drm/i915/dp: Made intel_dp_adjust_train() non-static
22b1b10eb6db drm/dp: get/set phy compliance pattern
66cfb3c26498 drm/amd/display: Align macro name as per DP spec
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for DP Phy compliance auto test (rev8)
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (9 preceding siblings ...)
2020-03-18 8:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev8) Patchwork
@ 2020-03-18 10:47 ` Patchwork
2020-03-24 5:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DP Phy compliance auto test (rev9) Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-03-18 10:47 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DP Phy compliance auto test (rev8)
URL : https://patchwork.freedesktop.org/series/71121/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8145_full -> Patchwork_17003_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17003_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@q-independent-bsd2:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +8 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb4/igt@gem_ctx_shared@q-independent-bsd2.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb7/igt@gem_ctx_shared@q-independent-bsd2.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112146]) +7 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb6/igt@gem_exec_async@concurrent-writes-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_balancer@hang:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#1277])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-tglb1/igt@gem_exec_balancer@hang.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-tglb7/igt@gem_exec_balancer@hang.html
* igt@gem_exec_schedule@implicit-both-bsd1:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb2/igt@gem_exec_schedule@implicit-both-bsd1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb8/igt@gem_exec_schedule@implicit-both-bsd1.html
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-apl1/igt@i915_suspend@fence-restore-untiled.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-apl4/igt@i915_suspend@fence-restore-untiled.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-kbl3/igt@i915_suspend@forcewake.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-kbl1/igt@i915_suspend@forcewake.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#79])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([i915#61])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-hsw4/igt@kms_flip@flip-vs-suspend-interruptible.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#34])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane@plane-panning-top-left-pipe-b-planes:
- shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-snb2/igt@kms_plane@plane-panning-top-left-pipe-b-planes.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-snb4/igt@kms_plane@plane-panning-top-left-pipe-b-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][23] -> [FAIL][24] ([i915#899])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-x.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109642] / [fdo#111068])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb2/igt@kms_psr@psr2_basic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb8/igt@kms_psr@psr2_basic.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][29] -> [FAIL][30] ([i915#31])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-apl8/igt@kms_setmode@basic.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-apl6/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#112080]) +9 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb1/igt@perf_pmu@busy-no-semaphores-vcs1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb6/igt@perf_pmu@busy-no-semaphores-vcs1.html
#### Possible fixes ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-kbl: [INCOMPLETE][33] ([i915#1402]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-kbl2/igt@gem_ctx_persistence@close-replace-race.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-kbl3/igt@gem_ctx_persistence@close-replace-race.html
- shard-skl: [INCOMPLETE][35] ([i915#1402]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-skl2/igt@gem_ctx_persistence@close-replace-race.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-skl7/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][37] ([fdo#110841]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@implicit-read-write-bsd1:
- shard-iclb: [SKIP][39] ([fdo#109276] / [i915#677]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb6/igt@gem_exec_schedule@implicit-read-write-bsd1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb1/igt@gem_exec_schedule@implicit-read-write-bsd1.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [SKIP][41] ([i915#677]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb4/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb7/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][43] ([fdo#112146]) -> [PASS][44] +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_whisper@basic-queues-priority:
- shard-skl: [FAIL][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-skl10/igt@gem_exec_whisper@basic-queues-priority.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-skl8/igt@gem_exec_whisper@basic-queues-priority.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][47] ([i915#644]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +5 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-apl8/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-iclb: [INCOMPLETE][53] ([i915#1185] / [i915#250]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][57] ([i915#31]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-skl2/igt@kms_setmode@basic.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-skl2/igt@kms_setmode@basic.html
* igt@perf_pmu@init-busy-vcs1:
- shard-iclb: [SKIP][59] ([fdo#112080]) -> [PASS][60] +7 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb7/igt@perf_pmu@init-busy-vcs1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb2/igt@perf_pmu@init-busy-vcs1.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][61] ([fdo#109276]) -> [PASS][62] +10 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-iclb3/igt@prime_busy@hang-bsd2.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-iclb2/igt@prime_busy@hang-bsd2.html
* {igt@sysfs_timeslice_duration@timeout@rcs0}:
- shard-skl: [FAIL][63] ([i915#1459]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-skl3/igt@sysfs_timeslice_duration@timeout@rcs0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-skl3/igt@sysfs_timeslice_duration@timeout@rcs0.html
#### Warnings ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-apl: [INCOMPLETE][65] ([fdo#103927] / [i915#1402]) -> [TIMEOUT][66] ([i915#1340])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-apl4/igt@gem_ctx_persistence@close-replace-race.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-apl1/igt@gem_ctx_persistence@close-replace-race.html
* igt@i915_pm_dc@dc5-psr:
- shard-snb: [INCOMPLETE][67] ([i915#82]) -> [SKIP][68] ([fdo#109271])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-snb4/igt@i915_pm_dc@dc5-psr.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-snb6/igt@i915_pm_dc@dc5-psr.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][69], [FAIL][70]) ([i915#1389] / [i915#1402] / [i915#92]) -> [FAIL][71] ([i915#92])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-kbl2/igt@runner@aborted.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-kbl6/igt@runner@aborted.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-kbl6/igt@runner@aborted.html
- shard-apl: ([FAIL][72], [FAIL][73]) ([fdo#103927] / [i915#1402]) -> [FAIL][74] ([fdo#103927])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-apl4/igt@runner@aborted.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8145/shard-apl3/igt@runner@aborted.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/shard-apl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1277]: https://gitlab.freedesktop.org/drm/intel/issues/1277
[i915#1340]: https://gitlab.freedesktop.org/drm/intel/issues/1340
[i915#1389]: https://gitlab.freedesktop.org/drm/intel/issues/1389
[i915#1402]: https://gitlab.freedesktop.org/drm/intel/issues/1402
[i915#1459]: https://gitlab.freedesktop.org/drm/intel/issues/1459
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8145 -> Patchwork_17003
CI-20190529: 20190529
CI_DRM_8145: 5e893da0b8c2bfec015c5eaa7981e1ffab1d7c9c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5518: ee05a571255783837b18d626c4dff6cd9613cee2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17003: af8eebf967773625d3357a6a78ab300562b524c9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17003/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DP Phy compliance auto test (rev9)
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (10 preceding siblings ...)
2020-03-18 10:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-03-24 5:47 ` Patchwork
2020-03-24 6:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-24 7:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-03-24 5:47 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DP Phy compliance auto test (rev9)
URL : https://patchwork.freedesktop.org/series/71121/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4e5780212f95 drm/amd/display: Align macro name as per DP spec
971a7ccb9e37 drm/dp: get/set phy compliance pattern
1b2997dcbda5 drm/i915/dp: Made intel_dp_adjust_train() non-static
340216da24fa drm/i915/dp: Preparation for DP phy compliance auto test
db7de8a9c187 drm/i915/dp: Add debugfs entry for DP phy compliance
608ba015c19c drm/i915/dp: Register definition for DP compliance register
-:29: WARNING:LONG_LINE: line over 100 characters
#29: FILE: drivers/gpu/drm/i915/i915_reg.h:9800:
+#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
-:42: WARNING:LONG_LINE: line over 100 characters
#42: FILE: drivers/gpu/drm/i915/i915_reg.h:9813:
+#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
total: 0 errors, 2 warnings, 0 checks, 24 lines checked
eeecea37ecbc drm/i915/dp: Program vswing, pre-emphasis, test-pattern
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev9)
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (11 preceding siblings ...)
2020-03-24 5:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DP Phy compliance auto test (rev9) Patchwork
@ 2020-03-24 6:30 ` Patchwork
2020-03-24 7:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-03-24 6:30 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DP Phy compliance auto test (rev9)
URL : https://patchwork.freedesktop.org/series/71121/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8182 -> Patchwork_17062
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/index.html
Known issues
------------
Here are the changes found in Patchwork_17062 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_selftest@live@gem_contexts:
- fi-cml-s: [DMESG-FAIL][1] ([i915#877]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
#### Warnings ####
* igt@i915_selftest@live@gem_contexts:
- fi-cfl-8700k: [DMESG-FAIL][3] ([i915#481]) -> [DMESG-FAIL][4] ([i915#730] / [i915#933])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
[i915#481]: https://gitlab.freedesktop.org/drm/intel/issues/481
[i915#730]: https://gitlab.freedesktop.org/drm/intel/issues/730
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
[i915#933]: https://gitlab.freedesktop.org/drm/intel/issues/933
Participating hosts (51 -> 34)
------------------------------
Missing (17): fi-cml-u2 fi-ilk-m540 fi-bdw-5557u fi-bsw-n3050 fi-byt-j1900 fi-skl-6770hq fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-kbl-7500u fi-ctg-p8600 fi-ivb-3770 fi-byt-clapper fi-bsw-nick fi-skl-6600u fi-snb-2600
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8182 -> Patchwork_17062
CI-20190529: 20190529
CI_DRM_8182: e5245084567cd7f6f93b07baaebf8a2b4d914620 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5531: 79e7382202c104b247a672c61a6186d1f51e4958 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17062: eeecea37ecbc074d3cfb7f80b514e9add7f87dcf @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
eeecea37ecbc drm/i915/dp: Program vswing, pre-emphasis, test-pattern
608ba015c19c drm/i915/dp: Register definition for DP compliance register
db7de8a9c187 drm/i915/dp: Add debugfs entry for DP phy compliance
340216da24fa drm/i915/dp: Preparation for DP phy compliance auto test
1b2997dcbda5 drm/i915/dp: Made intel_dp_adjust_train() non-static
971a7ccb9e37 drm/dp: get/set phy compliance pattern
4e5780212f95 drm/amd/display: Align macro name as per DP spec
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for DP Phy compliance auto test (rev9)
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
` (12 preceding siblings ...)
2020-03-24 6:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-03-24 7:47 ` Patchwork
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-03-24 7:47 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DP Phy compliance auto test (rev9)
URL : https://patchwork.freedesktop.org/series/71121/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8182_full -> Patchwork_17062_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17062_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +8 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb2/igt@gem_busy@busy-vcs1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb8/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-kbl2/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#679])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-apl4/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-apl8/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html
* igt@gem_exec_schedule@implicit-write-read-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#677])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb5/igt@gem_exec_schedule@implicit-write-read-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb1/igt@gem_exec_schedule@implicit-write-read-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +14 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb2/igt@gem_exec_schedule@promotion-bsd1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb5/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb6/igt@gem_exec_schedule@reorder-wide-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#34])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@invalid-oa-format-id:
- shard-hsw: [PASS][19] -> [INCOMPLETE][20] ([i915#61])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-hsw8/igt@perf@invalid-oa-format-id.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-hsw6/igt@perf@invalid-oa-format-id.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [SKIP][21] ([fdo#112080]) -> [PASS][22] +5 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process@render:
- shard-iclb: [FAIL][23] ([i915#679]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb2/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb8/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html
* igt@gem_exec_balancer@hang:
- shard-tglb: [FAIL][25] ([i915#1277]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-tglb1/igt@gem_exec_balancer@hang.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-tglb3/igt@gem_exec_balancer@hang.html
* igt@gem_exec_schedule@implicit-both-bsd1:
- shard-iclb: [SKIP][27] ([fdo#109276] / [i915#677]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb6/igt@gem_exec_schedule@implicit-both-bsd1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb2/igt@gem_exec_schedule@implicit-both-bsd1.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [SKIP][29] ([i915#677]) -> [PASS][30] +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb1/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb6/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][31] ([fdo#112146]) -> [PASS][32] +6 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw: [FAIL][33] -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-hsw6/igt@i915_pm_rc6_residency@rc6-idle.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-hsw2/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_selftest@live@hangcheck:
- shard-skl: [INCOMPLETE][35] ([fdo#108744]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-skl7/igt@i915_selftest@live@hangcheck.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-skl1/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][37] ([i915#180]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-apl8/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-glk: [FAIL][41] ([i915#34]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-glk2/igt@kms_flip@plain-flip-ts-check-interruptible.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-glk1/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][43] ([fdo#108145]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46] +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][47] ([i915#31]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-skl3/igt@kms_setmode@basic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-skl9/igt@kms_setmode@basic.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][49] ([fdo#109276]) -> [PASS][50] +14 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [SKIP][51] ([i915#468]) -> [FAIL][52] ([i915#454])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-tglb5/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-snb: [INCOMPLETE][53] ([i915#82]) -> [SKIP][54] ([fdo#109271])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-snb4/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-snb5/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_pm_rpm@sysfs-read:
- shard-snb: [SKIP][55] ([fdo#109271]) -> [INCOMPLETE][56] ([i915#82])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8182/shard-snb1/igt@i915_pm_rpm@sysfs-read.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/shard-snb2/igt@i915_pm_rpm@sysfs-read.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1277]: https://gitlab.freedesktop.org/drm/intel/issues/1277
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8182 -> Patchwork_17062
CI-20190529: 20190529
CI_DRM_8182: e5245084567cd7f6f93b07baaebf8a2b4d914620 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5531: 79e7382202c104b247a672c61a6186d1f51e4958 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17062: eeecea37ecbc074d3cfb7f80b514e9add7f87dcf @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17062/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread