[Intel-gfx] [PATCH 0/7] drm/i915: DP vswing/preemph fixes

[Intel-gfx] [PATCH 0/7] drm/i915: DP vswing/preemph fixes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

These vswing/preemph fixes were previously posted as part of
the link training crtc_state plumbing series, but since
that potentially had some odd behaviour in ci I'm sending
these separately. Hopefully nothing odd pops up with just these...

Ville Syrjälä (7):
  drm/i915: Fix cpt/ppt max pre-emphasis
  drm/i915: Fix ibx max vswing/preemph
  drm/i915: Fix ivb cpu edp vswing
  drm/i915: Add {preemph,voltage}_max() vfuncs
  drm/i915: Reverse preemph vs. voltage swing preference
  drm/i915: Fix DP_TRAIN_MAX_{PRE_EMPHASIS,SWING}_REACHED handling
  drm/i915: Replace some hand rolled max()s

 drivers/gpu/drm/i915/display/intel_ddi.c      | 21 ++---
 drivers/gpu/drm/i915/display/intel_ddi.h      |  3 -
 .../drm/i915/display/intel_display_types.h    |  3 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 80 +++++--------------
 drivers/gpu/drm/i915/display/intel_dp.h       |  4 -
 .../drm/i915/display/intel_dp_link_training.c | 36 ++++++---
 6 files changed, 56 insertions(+), 91 deletions(-)

-- 
2.26.2

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[Intel-gfx] [PATCH 1/7] drm/i915: Fix cpt/ppt max pre-emphasis

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

cpt/ppt support pre-emphasis level 3. Let's actually declare
support for it, instead of clamping things to level 2.

Also tweak the if-ladder in intel_dp_voltage_max() to match
intel_dp_pre_emphasis_max() to make it easier to compare them.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 67723dede1d1..7541264ff4e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3957,12 +3957,11 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 
 	if (HAS_DDI(dev_priv))
 		return intel_ddi_dp_voltage_max(encoder);
-	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
+		 (HAS_PCH_CPT(dev_priv) && port != PORT_A))
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
-	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
-		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 }
@@ -3976,7 +3975,8 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
 
 	if (HAS_DDI(dev_priv)) {
 		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
-	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
+		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			return DP_TRAIN_PRE_EMPH_LEVEL_3;
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 1/7] drm/i915: Fix cpt/ppt max pre-emphasis

[Souza, Jose]

On Tue, 2020-05-12 at 20:41 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> cpt/ppt support pre-emphasis level 3. Let's actually declare
> support for it, instead of clamping things to level 2.
> 
> Also tweak the if-ladder in intel_dp_voltage_max() to match
> intel_dp_pre_emphasis_max() to make it easier to compare them.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 67723dede1d1..7541264ff4e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3957,12 +3957,11 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  
>  	if (HAS_DDI(dev_priv))
>  		return intel_ddi_dp_voltage_max(encoder);
> -	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> +		 (HAS_PCH_CPT(dev_priv) && port != PORT_A))
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> -	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
> -		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>  }
> @@ -3976,7 +3975,8 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
>  
>  	if (HAS_DDI(dev_priv)) {
>  		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
> -	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> +	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> +		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {

Matches intel_dp_voltage_max().

>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			return DP_TRAIN_PRE_EMPH_LEVEL_3;
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[Intel-gfx] [PATCH 2/7] drm/i915: Fix ibx max vswing/preemph

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

IBX supports vswing level 3 and pre-emphasis level 3. Don't
limit it to level 2 for those.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7541264ff4e9..0924e041e1bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3958,7 +3958,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 	if (HAS_DDI(dev_priv))
 		return intel_ddi_dp_voltage_max(encoder);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
-		 (HAS_PCH_CPT(dev_priv) && port != PORT_A))
+		 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A))
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
@@ -3976,7 +3976,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
 	if (HAS_DDI(dev_priv)) {
 		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
-		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
+		   (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			return DP_TRAIN_PRE_EMPH_LEVEL_3;
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 2/7] drm/i915: Fix ibx max vswing/preemph

[Souza, Jose]

On Tue, 2020-05-12 at 20:41 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> IBX supports vswing level 3 and pre-emphasis level 3. Don't
> limit it to level 2 for those.

Matches https://01.org/linuxgraphics/documentation/driver-documentation-prms/2010-intel-core-processor-family

Reviewed-by: José Roberto de Souza <
jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7541264ff4e9..0924e041e1bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3958,7 +3958,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  	if (HAS_DDI(dev_priv))
>  		return intel_ddi_dp_voltage_max(encoder);
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> -		 (HAS_PCH_CPT(dev_priv) && port != PORT_A))
> +		 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A))
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> @@ -3976,7 +3976,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
>  	if (HAS_DDI(dev_priv)) {
>  		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> -		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> +		   (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			return DP_TRAIN_PRE_EMPH_LEVEL_3;
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[Intel-gfx] [PATCH 3/7] drm/i915: Fix ivb cpu edp vswing

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

According to the DP spec supporting vswing 1 + preemph 2 is
mandatory. We don't have the hw settings for that though. In
order to pretend to follow the DP spec let's just select
vswing 0 + preemph 2 in this case (the DP spec says to use
the requested preemph in preference to the vswing when the
requested values aren't supported).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 13 +------------
 1 file changed, 1 insertion(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0924e041e1bf..4952918d0904 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3960,8 +3960,6 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
 		 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A))
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
-	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
-		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 	else
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 }
@@ -3988,16 +3986,6 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
 		default:
 			return DP_TRAIN_PRE_EMPH_LEVEL_0;
 		}
-	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
-		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-			return DP_TRAIN_PRE_EMPH_LEVEL_2;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-			return DP_TRAIN_PRE_EMPH_LEVEL_1;
-		default:
-			return DP_TRAIN_PRE_EMPH_LEVEL_0;
-		}
 	} else {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
@@ -4293,6 +4281,7 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set)
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
 		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
 		return EDP_LINK_TRAIN_400MV_6DB_IVB;
 
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 3/7] drm/i915: Fix ivb cpu edp vswing

[Souza, Jose]

On Tue, 2020-05-12 at 20:41 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> According to the DP spec supporting vswing 1 + preemph 2 is
> mandatory. We don't have the hw settings for that though. In
> order to pretend to follow the DP spec let's just select
> vswing 0 + preemph 2 in this case (the DP spec says to use
> the requested preemph in preference to the vswing when the
> requested values aren't supported).
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 13 +------------
>  1 file changed, 1 insertion(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0924e041e1bf..4952918d0904 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3960,8 +3960,6 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
>  		 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A))
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> -	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
> -		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>  	else
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>  }
> @@ -3988,16 +3986,6 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
>  		default:
>  			return DP_TRAIN_PRE_EMPH_LEVEL_0;
>  		}
> -	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> -		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_1;
> -		default:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_0;
> -		}
>  	} else {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> @@ -4293,6 +4281,7 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set)
>  	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
>  	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
>  		return EDP_LINK_TRAIN_400MV_6DB_IVB;
>  
>  	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
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[Intel-gfx] [PATCH 4/7] drm/i915: Add {preemph, voltage}_max() vfuncs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Different platforms have different max vswing/preemph settings.
Turn that into a pair vfuncs so we can decouple intel_dp.c and
intel_ddi.c further.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 21 ++----
 drivers/gpu/drm/i915/display/intel_ddi.h      |  3 -
 .../drm/i915/display/intel_display_types.h    |  3 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 67 ++++++-------------
 drivers/gpu/drm/i915/display/intel_dp.h       |  4 --
 .../drm/i915/display/intel_dp_link_training.c | 20 +++++-
 6 files changed, 49 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 798889f72495..f873fd03ac14 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2095,10 +2095,10 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
 				     ddi_translations[level].deemphasis);
 }
 
-u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
+static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
 {
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	enum port port = encoder->port;
 	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int n_entries;
@@ -2151,19 +2151,9 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
  * used on all DDI platforms. Should that change we need to
  * rethink this code.
  */
-u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
+static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
 {
-	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-		return DP_TRAIN_PRE_EMPH_LEVEL_3;
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-		return DP_TRAIN_PRE_EMPH_LEVEL_2;
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-		return DP_TRAIN_PRE_EMPH_LEVEL_1;
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
-	default:
-		return DP_TRAIN_PRE_EMPH_LEVEL_0;
-	}
+	return DP_TRAIN_PRE_EMPH_LEVEL_3;
 }
 
 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
@@ -4510,6 +4500,9 @@ intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
 	else
 		intel_dig_port->dp.set_signal_levels = hsw_set_signal_levels;
 
+	intel_dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
+	intel_dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
+
 	if (INTEL_GEN(dev_priv) < 12) {
 		intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
 		intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index fbdf8ddde486..077e9dbbe367 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -42,9 +42,6 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 					 struct intel_crtc_state *crtc_state);
 u32 bxt_signal_levels(struct intel_dp *intel_dp);
 u32 ddi_signal_levels(struct intel_dp *intel_dp);
-u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
-u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
-				 u8 voltage_swing);
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
 				     bool enable);
 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 87876fce91a5..46e91574f178 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1371,6 +1371,9 @@ struct intel_dp {
 	void (*set_idle_link_train)(struct intel_dp *intel_dp);
 	void (*set_signal_levels)(struct intel_dp *intel_dp);
 
+	u8 (*preemph_max)(struct intel_dp *intel_dp);
+	u8 (*voltage_max)(struct intel_dp *intel_dp);
+
 	/* Displayport compliance testing */
 	struct intel_dp_compliance compliance;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4952918d0904..6d790633e667 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3947,58 +3947,24 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATU
 				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
 }
 
-/* These are source-specific values. */
-u8
-intel_dp_voltage_max(struct intel_dp *intel_dp)
+static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp)
 {
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-	enum port port = encoder->port;
+	return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
+}
 
-	if (HAS_DDI(dev_priv))
-		return intel_ddi_dp_voltage_max(encoder);
-	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
-		 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A))
-		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
-	else
-		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
+static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
+{
+	return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 }
 
-u8
-intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
+static u8 intel_dp_pre_empemph_max_2(struct intel_dp *intel_dp)
 {
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-	enum port port = encoder->port;
+	return DP_TRAIN_PRE_EMPH_LEVEL_2;
+}
 
-	if (HAS_DDI(dev_priv)) {
-		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
-	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
-		   (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
-		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-			return DP_TRAIN_PRE_EMPH_LEVEL_3;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-			return DP_TRAIN_PRE_EMPH_LEVEL_2;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-			return DP_TRAIN_PRE_EMPH_LEVEL_1;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
-		default:
-			return DP_TRAIN_PRE_EMPH_LEVEL_0;
-		}
-	} else {
-		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-			return DP_TRAIN_PRE_EMPH_LEVEL_2;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-			return DP_TRAIN_PRE_EMPH_LEVEL_2;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-			return DP_TRAIN_PRE_EMPH_LEVEL_1;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
-		default:
-			return DP_TRAIN_PRE_EMPH_LEVEL_0;
-		}
-	}
+static u8 intel_dp_pre_empemph_max_3(struct intel_dp *intel_dp)
+{
+	return DP_TRAIN_PRE_EMPH_LEVEL_3;
 }
 
 static void vlv_set_signal_levels(struct intel_dp *intel_dp)
@@ -8325,6 +8291,15 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
 	else
 		intel_dig_port->dp.set_signal_levels = g4x_set_signal_levels;
 
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
+	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
+		intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3;
+		intel_dig_port->dp.voltage_max = intel_dp_voltage_max_3;
+	} else {
+		intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2;
+		intel_dig_port->dp.voltage_max = intel_dp_voltage_max_2;
+	}
+
 	intel_dig_port->dp.output_reg = output_reg;
 	intel_dig_port->max_lanes = 4;
 	intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6659ce15a693..e8375a75c3ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -91,10 +91,6 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
-u8
-intel_dp_voltage_max(struct intel_dp *intel_dp);
-u8
-intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 			   u8 *link_bw, u8 *rate_select);
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index e4f1843170b7..171d9e842fc0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,6 +34,21 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 		      link_status[3], link_status[4], link_status[5]);
 }
 
+static u8 dp_pre_emphasis_max(u8 voltage_swing)
+{
+	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
+		return DP_TRAIN_PRE_EMPH_LEVEL_3;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+		return DP_TRAIN_PRE_EMPH_LEVEL_2;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+		return DP_TRAIN_PRE_EMPH_LEVEL_1;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
+	default:
+		return DP_TRAIN_PRE_EMPH_LEVEL_0;
+	}
+}
+
 void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			       const u8 link_status[DP_LINK_STATUS_SIZE])
 {
@@ -53,11 +68,12 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			p = this_p;
 	}
 
-	voltage_max = intel_dp_voltage_max(intel_dp);
+	voltage_max = intel_dp->voltage_max(intel_dp);
 	if (v >= voltage_max)
 		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
 
-	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+	preemph_max = min(intel_dp->preemph_max(intel_dp),
+			  dp_pre_emphasis_max(v));
 	if (p >= preemph_max)
 		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 4/7] drm/i915: Add {preemph, voltage}_max() vfuncs

[Manasi Navare]

On Tue, May 12, 2020 at 08:41:42PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Different platforms have different max vswing/preemph settings.
> Turn that into a pair vfuncs so we can decouple intel_dp.c and
> intel_ddi.c further.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

This is so much cleaner, thanks for the patch,

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 21 ++----
>  drivers/gpu/drm/i915/display/intel_ddi.h      |  3 -
>  .../drm/i915/display/intel_display_types.h    |  3 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 67 ++++++-------------
>  drivers/gpu/drm/i915/display/intel_dp.h       |  4 --
>  .../drm/i915/display/intel_dp_link_training.c | 20 +++++-
>  6 files changed, 49 insertions(+), 69 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 798889f72495..f873fd03ac14 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2095,10 +2095,10 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
>  				     ddi_translations[level].deemphasis);
>  }
>  
> -u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
> +static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
>  {
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	enum port port = encoder->port;
>  	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	int n_entries;
> @@ -2151,19 +2151,9 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>   * used on all DDI platforms. Should that change we need to
>   * rethink this code.
>   */
> -u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
> +static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
>  {
> -	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> -		return DP_TRAIN_PRE_EMPH_LEVEL_3;
> -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> -		return DP_TRAIN_PRE_EMPH_LEVEL_2;
> -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> -		return DP_TRAIN_PRE_EMPH_LEVEL_1;
> -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> -	default:
> -		return DP_TRAIN_PRE_EMPH_LEVEL_0;
> -	}
> +	return DP_TRAIN_PRE_EMPH_LEVEL_3;
>  }
>  
>  static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
> @@ -4510,6 +4500,9 @@ intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
>  	else
>  		intel_dig_port->dp.set_signal_levels = hsw_set_signal_levels;
>  
> +	intel_dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
> +	intel_dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
> +
>  	if (INTEL_GEN(dev_priv) < 12) {
>  		intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
>  		intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> index fbdf8ddde486..077e9dbbe367 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -42,9 +42,6 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
>  					 struct intel_crtc_state *crtc_state);
>  u32 bxt_signal_levels(struct intel_dp *intel_dp);
>  u32 ddi_signal_levels(struct intel_dp *intel_dp);
> -u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
> -u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
> -				 u8 voltage_swing);
>  int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
>  				     bool enable);
>  void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 87876fce91a5..46e91574f178 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1371,6 +1371,9 @@ struct intel_dp {
>  	void (*set_idle_link_train)(struct intel_dp *intel_dp);
>  	void (*set_signal_levels)(struct intel_dp *intel_dp);
>  
> +	u8 (*preemph_max)(struct intel_dp *intel_dp);
> +	u8 (*voltage_max)(struct intel_dp *intel_dp);
> +
>  	/* Displayport compliance testing */
>  	struct intel_dp_compliance compliance;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4952918d0904..6d790633e667 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3947,58 +3947,24 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATU
>  				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
>  }
>  
> -/* These are source-specific values. */
> -u8
> -intel_dp_voltage_max(struct intel_dp *intel_dp)
> +static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp)
>  {
> -	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> -	enum port port = encoder->port;
> +	return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> +}
>  
> -	if (HAS_DDI(dev_priv))
> -		return intel_ddi_dp_voltage_max(encoder);
> -	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> -		 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A))
> -		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> -	else
> -		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> +static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
> +{
> +	return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  }
>  
> -u8
> -intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
> +static u8 intel_dp_pre_empemph_max_2(struct intel_dp *intel_dp)
>  {
> -	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> -	enum port port = encoder->port;
> +	return DP_TRAIN_PRE_EMPH_LEVEL_2;
> +}
>  
> -	if (HAS_DDI(dev_priv)) {
> -		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
> -	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> -		   (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
> -		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_3;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_1;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> -		default:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_0;
> -		}
> -	} else {
> -		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_1;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> -		default:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_0;
> -		}
> -	}
> +static u8 intel_dp_pre_empemph_max_3(struct intel_dp *intel_dp)
> +{
> +	return DP_TRAIN_PRE_EMPH_LEVEL_3;
>  }
>  
>  static void vlv_set_signal_levels(struct intel_dp *intel_dp)
> @@ -8325,6 +8291,15 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
>  	else
>  		intel_dig_port->dp.set_signal_levels = g4x_set_signal_levels;
>  
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> +	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
> +		intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3;
> +		intel_dig_port->dp.voltage_max = intel_dp_voltage_max_3;
> +	} else {
> +		intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2;
> +		intel_dig_port->dp.voltage_max = intel_dp_voltage_max_2;
> +	}
> +
>  	intel_dig_port->dp.output_reg = output_reg;
>  	intel_dig_port->max_lanes = 4;
>  	intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 6659ce15a693..e8375a75c3ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -91,10 +91,6 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>  void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>  void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
> -u8
> -intel_dp_voltage_max(struct intel_dp *intel_dp);
> -u8
> -intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
>  void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
>  			   u8 *link_bw, u8 *rate_select);
>  bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index e4f1843170b7..171d9e842fc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,6 +34,21 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>  		      link_status[3], link_status[4], link_status[5]);
>  }
>  
> +static u8 dp_pre_emphasis_max(u8 voltage_swing)
> +{
> +	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> +		return DP_TRAIN_PRE_EMPH_LEVEL_3;
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> +		return DP_TRAIN_PRE_EMPH_LEVEL_2;
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> +		return DP_TRAIN_PRE_EMPH_LEVEL_1;
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> +	default:
> +		return DP_TRAIN_PRE_EMPH_LEVEL_0;
> +	}
> +}
> +
>  void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  			       const u8 link_status[DP_LINK_STATUS_SIZE])
>  {
> @@ -53,11 +68,12 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  			p = this_p;
>  	}
>  
> -	voltage_max = intel_dp_voltage_max(intel_dp);
> +	voltage_max = intel_dp->voltage_max(intel_dp);
>  	if (v >= voltage_max)
>  		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>  
> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> +	preemph_max = min(intel_dp->preemph_max(intel_dp),
> +			  dp_pre_emphasis_max(v));
>  	if (p >= preemph_max)
>  		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>  
> -- 
> 2.26.2
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH 5/7] drm/i915: Reverse preemph vs. voltage swing preference

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DP spec says:
"When the combination of the requested pre-emphasis level and
 voltage swing exceeds the capability of a DPTX, the DPTX shall
 set the pre-emphasis level according to the request and use the
 highest voltage swing it can output with the given pre-emphasis level."
and
"When a DPTX reads a request beyond the limits of this Standard,
 the DPTX shall set the pre-emphasis level according to the request
 and set the highest voltage swing level it can output with the
 given pre-emphasis level. If a DPTX is requested for 9.5dB of
 pre-emphasis level (may be supported for a DPTX) and cannot support
 that level, it shall set the pre-emphasis level to the next
 highest level, 6dB."

Ie. we should first validate the pre-emphasis, and then select
the appropriate vswing for it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_dp_link_training.c | 32 +++++++++----------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 171d9e842fc0..573f93779449 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,18 +34,18 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 		      link_status[3], link_status[4], link_status[5]);
 }
 
-static u8 dp_pre_emphasis_max(u8 voltage_swing)
+static u8 dp_voltage_max(u8 preemph)
 {
-	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-		return DP_TRAIN_PRE_EMPH_LEVEL_3;
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-		return DP_TRAIN_PRE_EMPH_LEVEL_2;
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-		return DP_TRAIN_PRE_EMPH_LEVEL_1;
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
+	switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
+	case DP_TRAIN_PRE_EMPH_LEVEL_0:
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
+	case DP_TRAIN_PRE_EMPH_LEVEL_1:
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
+	case DP_TRAIN_PRE_EMPH_LEVEL_2:
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
+	case DP_TRAIN_PRE_EMPH_LEVEL_3:
 	default:
-		return DP_TRAIN_PRE_EMPH_LEVEL_0;
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 	}
 }
 
@@ -68,15 +68,15 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			p = this_p;
 	}
 
-	voltage_max = intel_dp->voltage_max(intel_dp);
-	if (v >= voltage_max)
-		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
-	preemph_max = min(intel_dp->preemph_max(intel_dp),
-			  dp_pre_emphasis_max(v));
+	preemph_max = intel_dp->preemph_max(intel_dp);
 	if (p >= preemph_max)
 		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 
+	voltage_max = min(intel_dp->voltage_max(intel_dp),
+			  dp_voltage_max(p));
+	if (v >= voltage_max)
+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
 	for (lane = 0; lane < 4; lane++)
 		intel_dp->train_set[lane] = v | p;
 }
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 5/7] drm/i915: Reverse preemph vs. voltage swing preference

[Manasi Navare]

On Tue, May 12, 2020 at 08:41:43PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The DP spec says:
> "When the combination of the requested pre-emphasis level and
>  voltage swing exceeds the capability of a DPTX, the DPTX shall
>  set the pre-emphasis level according to the request and use the
>  highest voltage swing it can output with the given pre-emphasis level."
> and
> "When a DPTX reads a request beyond the limits of this Standard,
>  the DPTX shall set the pre-emphasis level according to the request
>  and set the highest voltage swing level it can output with the
>  given pre-emphasis level. If a DPTX is requested for 9.5dB of
>  pre-emphasis level (may be supported for a DPTX) and cannot support
>  that level, it shall set the pre-emphasis level to the next
>  highest level, 6dB."
> 
> Ie. we should first validate the pre-emphasis, and then select
> the appropriate vswing for it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

So basically reverse the logic for selecting the vswing and pre emphasis

> ---
>  .../drm/i915/display/intel_dp_link_training.c | 32 +++++++++----------
>  1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 171d9e842fc0..573f93779449 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,18 +34,18 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>  		      link_status[3], link_status[4], link_status[5]);
>  }
>  
> -static u8 dp_pre_emphasis_max(u8 voltage_swing)
> +static u8 dp_voltage_max(u8 preemph)
>  {
> -	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> -		return DP_TRAIN_PRE_EMPH_LEVEL_3;
> -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> -		return DP_TRAIN_PRE_EMPH_LEVEL_2;
> -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> -		return DP_TRAIN_PRE_EMPH_LEVEL_1;
> -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> +	switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
> +	case DP_TRAIN_PRE_EMPH_LEVEL_0:
> +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> +	case DP_TRAIN_PRE_EMPH_LEVEL_1:
> +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> +	case DP_TRAIN_PRE_EMPH_LEVEL_2:
> +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
> +	case DP_TRAIN_PRE_EMPH_LEVEL_3:
>  	default:
> -		return DP_TRAIN_PRE_EMPH_LEVEL_0;
> +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;

These vswing levels for that specific pre emph level comes from the Bspec
or from the DP spec? It wasnt clear to me how level3 of vswing was the max for pre emphasis level 0 and all others?

Manasi

>  	}
>  }
>  
> @@ -68,15 +68,15 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  			p = this_p;
>  	}
>  
> -	voltage_max = intel_dp->voltage_max(intel_dp);
> -	if (v >= voltage_max)
> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> -
> -	preemph_max = min(intel_dp->preemph_max(intel_dp),
> -			  dp_pre_emphasis_max(v));
> +	preemph_max = intel_dp->preemph_max(intel_dp);
>  	if (p >= preemph_max)
>  		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>  
> +	voltage_max = min(intel_dp->voltage_max(intel_dp),
> +			  dp_voltage_max(p));
> +	if (v >= voltage_max)
> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> +
>  	for (lane = 0; lane < 4; lane++)
>  		intel_dp->train_set[lane] = v | p;
>  }
> -- 
> 2.26.2
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 5/7] drm/i915: Reverse preemph vs. voltage swing preference

[Ville Syrjälä]

On Fri, May 15, 2020 at 12:18:22PM -0700, Manasi Navare wrote:
> On Tue, May 12, 2020 at 08:41:43PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The DP spec says:
> > "When the combination of the requested pre-emphasis level and
> >  voltage swing exceeds the capability of a DPTX, the DPTX shall
> >  set the pre-emphasis level according to the request and use the
> >  highest voltage swing it can output with the given pre-emphasis level."
> > and
> > "When a DPTX reads a request beyond the limits of this Standard,
> >  the DPTX shall set the pre-emphasis level according to the request
> >  and set the highest voltage swing level it can output with the
> >  given pre-emphasis level. If a DPTX is requested for 9.5dB of
> >  pre-emphasis level (may be supported for a DPTX) and cannot support
> >  that level, it shall set the pre-emphasis level to the next
> >  highest level, 6dB."
> > 
> > Ie. we should first validate the pre-emphasis, and then select
> > the appropriate vswing for it.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> So basically reverse the logic for selecting the vswing and pre emphasis
> 
> > ---
> >  .../drm/i915/display/intel_dp_link_training.c | 32 +++++++++----------
> >  1 file changed, 16 insertions(+), 16 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 171d9e842fc0..573f93779449 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -34,18 +34,18 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
> >  		      link_status[3], link_status[4], link_status[5]);
> >  }
> >  
> > -static u8 dp_pre_emphasis_max(u8 voltage_swing)
> > +static u8 dp_voltage_max(u8 preemph)
> >  {
> > -	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> > -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> > -		return DP_TRAIN_PRE_EMPH_LEVEL_3;
> > -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> > -		return DP_TRAIN_PRE_EMPH_LEVEL_2;
> > -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> > -		return DP_TRAIN_PRE_EMPH_LEVEL_1;
> > -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> > +	switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
> > +	case DP_TRAIN_PRE_EMPH_LEVEL_0:
> > +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> > +	case DP_TRAIN_PRE_EMPH_LEVEL_1:
> > +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> > +	case DP_TRAIN_PRE_EMPH_LEVEL_2:
> > +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
> > +	case DP_TRAIN_PRE_EMPH_LEVEL_3:
> >  	default:
> > -		return DP_TRAIN_PRE_EMPH_LEVEL_0;
> > +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
> 
> These vswing levels for that specific pre emph level comes from the Bspec
> or from the DP spec? It wasnt clear to me how level3 of vswing was the max for pre emphasis level 0 and all others?

From DP 1.4 spec "Table 3-1: Allowed Vdiff_pre_pp and Pre-emphasis
Combinations"

Previosuly this was present in some semi-mangled way in each
platform's max preeph calculation. Now we just have one canonical
copy of it. Later on we could probably lift this into drm_dp_helper.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 5/7] drm/i915: Reverse preemph vs. voltage swing preference

[Manasi Navare]

On Fri, May 15, 2020 at 10:59:57PM +0300, Ville Syrjälä wrote:
> On Fri, May 15, 2020 at 12:18:22PM -0700, Manasi Navare wrote:
> > On Tue, May 12, 2020 at 08:41:43PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > The DP spec says:
> > > "When the combination of the requested pre-emphasis level and
> > >  voltage swing exceeds the capability of a DPTX, the DPTX shall
> > >  set the pre-emphasis level according to the request and use the
> > >  highest voltage swing it can output with the given pre-emphasis level."
> > > and
> > > "When a DPTX reads a request beyond the limits of this Standard,
> > >  the DPTX shall set the pre-emphasis level according to the request
> > >  and set the highest voltage swing level it can output with the
> > >  given pre-emphasis level. If a DPTX is requested for 9.5dB of
> > >  pre-emphasis level (may be supported for a DPTX) and cannot support
> > >  that level, it shall set the pre-emphasis level to the next
> > >  highest level, 6dB."
> > > 
> > > Ie. we should first validate the pre-emphasis, and then select
> > > the appropriate vswing for it.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > So basically reverse the logic for selecting the vswing and pre emphasis
> > 
> > > ---
> > >  .../drm/i915/display/intel_dp_link_training.c | 32 +++++++++----------
> > >  1 file changed, 16 insertions(+), 16 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index 171d9e842fc0..573f93779449 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -34,18 +34,18 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
> > >  		      link_status[3], link_status[4], link_status[5]);
> > >  }
> > >  
> > > -static u8 dp_pre_emphasis_max(u8 voltage_swing)
> > > +static u8 dp_voltage_max(u8 preemph)
> > >  {
> > > -	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> > > -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> > > -		return DP_TRAIN_PRE_EMPH_LEVEL_3;
> > > -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> > > -		return DP_TRAIN_PRE_EMPH_LEVEL_2;
> > > -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> > > -		return DP_TRAIN_PRE_EMPH_LEVEL_1;
> > > -	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> > > +	switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
> > > +	case DP_TRAIN_PRE_EMPH_LEVEL_0:
> > > +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> > > +	case DP_TRAIN_PRE_EMPH_LEVEL_1:
> > > +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> > > +	case DP_TRAIN_PRE_EMPH_LEVEL_2:
> > > +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
> > > +	case DP_TRAIN_PRE_EMPH_LEVEL_3:
> > >  	default:
> > > -		return DP_TRAIN_PRE_EMPH_LEVEL_0;
> > > +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
> > 
> > These vswing levels for that specific pre emph level comes from the Bspec
> > or from the DP spec? It wasnt clear to me how level3 of vswing was the max for pre emphasis level 0 and all others?
> 
> From DP 1.4 spec "Table 3-1: Allowed Vdiff_pre_pp and Pre-emphasis
> Combinations"
> 
> Previosuly this was present in some semi-mangled way in each
> platform's max preeph calculation. Now we just have one canonical
> copy of it. Later on we could probably lift this into drm_dp_helper.

Okay great yes confirmed from that table and looks good to me

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> 
> -- 
> Ville Syrjälä
> Intel
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[Intel-gfx] [PATCH 6/7] drm/i915: Fix DP_TRAIN_MAX_{PRE_EMPHASIS, SWING}_REACHED handling

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DP spec says:
"The transmitter shall support at least three levels of voltage
 swing (Levels 0, 1, and 2).

 If only three levels of voltage swing are supported (VOLTAGE
 SWING SET field (bits 1:0) are programmed to 10 (Level 2)),
 this bit shall be set to 1, and cleared in all other cases.

 If all four levels of voltage swing are supported (VOLTAGE
 SWING SET field (bits 1:0) are programmed to 11 (Level 3)),
 this bit shall be set to 1,and cleared in all other cases."

Let's follow that exactly instead of the current apporach
where we can set those also for vswing/preemph levels 0 or 1
(or 2 when the platform max is 3).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 573f93779449..aa7af531bcb8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -72,8 +72,9 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 	if (p >= preemph_max)
 		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 
-	voltage_max = min(intel_dp->voltage_max(intel_dp),
-			  dp_voltage_max(p));
+	v = min(v, dp_voltage_max(p));
+
+	voltage_max = intel_dp->voltage_max(intel_dp);
 	if (v >= voltage_max)
 		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
 
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 6/7] drm/i915: Fix DP_TRAIN_MAX_{PRE_EMPHASIS, SWING}_REACHED handling

[Imre Deak]

On Tue, May 12, 2020 at 08:41:44PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The DP spec says:
> "The transmitter shall support at least three levels of voltage
>  swing (Levels 0, 1, and 2).
> 
>  If only three levels of voltage swing are supported (VOLTAGE
>  SWING SET field (bits 1:0) are programmed to 10 (Level 2)),
>  this bit shall be set to 1, and cleared in all other cases.
> 
>  If all four levels of voltage swing are supported (VOLTAGE
>  SWING SET field (bits 1:0) are programmed to 11 (Level 3)),
>  this bit shall be set to 1,and cleared in all other cases."
> 
> Let's follow that exactly instead of the current apporach
> where we can set those also for vswing/preemph levels 0 or 1
> (or 2 when the platform max is 3).
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Yep, so the sink could've incorrectly stopped asking for higher vswing
levels after it asked for 0 vs+2 pe, when the max vs is 2 for instance.
Matches the spec:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 573f93779449..aa7af531bcb8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -72,8 +72,9 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  	if (p >= preemph_max)
>  		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>  
> -	voltage_max = min(intel_dp->voltage_max(intel_dp),
> -			  dp_voltage_max(p));
> +	v = min(v, dp_voltage_max(p));
> +
> +	voltage_max = intel_dp->voltage_max(intel_dp);
>  	if (v >= voltage_max)
>  		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>  
> -- 
> 2.26.2
> 
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[Intel-gfx] [PATCH 7/7] drm/i915: Replace some hand rolled max()s

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use max() instead of hand rolling it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index aa7af531bcb8..2493142a70e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -59,13 +59,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 	u8 preemph_max;
 
 	for (lane = 0; lane < intel_dp->lane_count; lane++) {
-		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
-		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-
-		if (this_v > v)
-			v = this_v;
-		if (this_p > p)
-			p = this_p;
+		v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
+		p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
 	}
 
 	preemph_max = intel_dp->preemph_max(intel_dp);
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 7/7] drm/i915: Replace some hand rolled max()s

[Manasi Navare]

On Tue, May 12, 2020 at 08:41:45PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use max() instead of hand rolling it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 9 ++-------
>  1 file changed, 2 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index aa7af531bcb8..2493142a70e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -59,13 +59,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  	u8 preemph_max;
>  
>  	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> -
> -		if (this_v > v)
> -			v = this_v;
> -		if (this_p > p)
> -			p = this_p;
> +		v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
> +		p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
>  	}
>  
>  	preemph_max = intel_dp->preemph_max(intel_dp);
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: DP vswing/preemph fixes

[Patchwork]

== Series Details ==

Series: drm/i915: DP vswing/preemph fixes
URL   : https://patchwork.freedesktop.org/series/77198/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8470 -> Patchwork_17635
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17635:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u2:          [PASS][1] -> [{ABORT}][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/fi-icl-u2/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/fi-icl-u2/igt@debugfs_test@read_all_entries.html

  
Known issues
------------

  Here are the changes found in Patchwork_17635 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-hsw-4770:        [PASS][3] -> [SKIP][4] ([fdo#109271]) +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@execlists:
    - fi-skl-6600u:       [PASS][5] -> [INCOMPLETE][6] ([i915#1874])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/fi-skl-6600u/igt@i915_selftest@live@execlists.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/fi-skl-6600u/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_pm:
    - fi-bwr-2160:        [PASS][7] -> [INCOMPLETE][8] ([i915#489])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/fi-bwr-2160/igt@i915_selftest@live@gt_pm.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/fi-bwr-2160/igt@i915_selftest@live@gt_pm.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@active:
    - fi-apl-guc:         [DMESG-FAIL][9] ([i915#666]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/fi-apl-guc/igt@i915_selftest@live@active.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/fi-apl-guc/igt@i915_selftest@live@active.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1874]: https://gitlab.freedesktop.org/drm/intel/issues/1874
  [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
  [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666


Participating hosts (49 -> 43)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8470 -> Patchwork_17635

  CI-20190529: 20190529
  CI_DRM_8470: d2c5ae86eac811c49f2fe22c4fa02b6e6d31cd67 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5651: e54e2642f1967ca3c488db32264607df670d1dfb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17635: 0c0676f7ff331d0f52650631d49993ff07b34aab @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0c0676f7ff33 drm/i915: Replace some hand rolled max()s
eecd407755db drm/i915: Fix DP_TRAIN_MAX_{PRE_EMPHASIS, SWING}_REACHED handling
bf43df649859 drm/i915: Reverse preemph vs. voltage swing preference
bbd0ca405d25 drm/i915: Add {preemph, voltage}_max() vfuncs
73b52b02124f drm/i915: Fix ivb cpu edp vswing
6eda9cf25b2c drm/i915: Fix ibx max vswing/preemph
8a4fb48decbe drm/i915: Fix cpt/ppt max pre-emphasis

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DP vswing/preemph fixes

[Patchwork]

== Series Details ==

Series: drm/i915: DP vswing/preemph fixes
URL   : https://patchwork.freedesktop.org/series/77198/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8470_full -> Patchwork_17635_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_17635_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_suspend@debugfs-reader:
    - shard-kbl:          [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-kbl1/igt@i915_suspend@debugfs-reader.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-kbl7/igt@i915_suspend@debugfs-reader.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([i915#180])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-apl4/igt@i915_suspend@fence-restore-untiled.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-apl1/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen:
    - shard-kbl:          [PASS][5] -> [DMESG-WARN][6] ([i915#78])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([i915#180] / [i915#95])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
    - shard-tglb:         [PASS][9] -> [SKIP][10] ([i915#668]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([i915#1188])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#109642] / [fdo#111068])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-iclb8/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109441])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-iclb6/igt@kms_psr@psr2_cursor_render.html

  * igt@prime_vgem@shrink:
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#165])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-kbl1/igt@prime_vgem@shrink.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-kbl2/igt@prime_vgem@shrink.html

  
#### Possible fixes ####

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [DMESG-WARN][21] ([i915#1436] / [i915#716]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-apl3/igt@gen9_exec_parse@allowed-all.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-apl2/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_selftest@live@gt_pm:
    - shard-apl:          [INCOMPLETE][23] ([i915#1812]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-apl2/igt@i915_selftest@live@gt_pm.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-apl7/igt@i915_selftest@live@gt_pm.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen:
    - shard-skl:          [FAIL][25] ([i915#54]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html

  * {igt@kms_flip@flip-vs-suspend-interruptible@a-dp1}:
    - shard-apl:          [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +5 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * {igt@kms_flip@flip-vs-suspend@c-dp1}:
    - shard-kbl:          [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * {igt@kms_flip@plain-flip-ts-check@a-hdmi-a1}:
    - shard-glk:          [FAIL][31] ([i915#34]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-glk8/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-glk1/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [FAIL][33] ([i915#1188]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][35] ([fdo#108145] / [i915#265]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [SKIP][37] ([fdo#109441]) -> [PASS][38] +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [FAIL][39] ([i915#31]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-kbl3/igt@kms_setmode@basic.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-kbl6/igt@kms_setmode@basic.html

  * {igt@perf@blocking-parameterized}:
    - shard-hsw:          [FAIL][41] ([i915#1542]) -> [PASS][42] +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-hsw8/igt@perf@blocking-parameterized.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-hsw2/igt@perf@blocking-parameterized.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          [TIMEOUT][43] ([i915#1319]) -> [FAIL][44] ([fdo#110321] / [fdo#110336] / [i915#95])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-apl7/igt@kms_content_protection@atomic-dpms.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-apl6/igt@kms_content_protection@atomic-dpms.html
    - shard-kbl:          [TIMEOUT][45] ([i915#1319]) -> [FAIL][46] ([fdo#110321] / [fdo#110336] / [i915#93] / [i915#95])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8470/shard-kbl3/igt@kms_content_protection@atomic-dpms.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/shard-kbl2/igt@kms_content_protection@atomic-dpms.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1812]: https://gitlab.freedesktop.org/drm/intel/issues/1812
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8470 -> Patchwork_17635

  CI-20190529: 20190529
  CI_DRM_8470: d2c5ae86eac811c49f2fe22c4fa02b6e6d31cd67 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5651: e54e2642f1967ca3c488db32264607df670d1dfb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17635: 0c0676f7ff331d0f52650631d49993ff07b34aab @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17635/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx