[Intel-gfx] [PATCH 1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice

[Intel-gfx] [PATCH 1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice

[José Roberto de Souza]

It will be programed right before the link training, so no need to do
it twice.
It will not strictly follow BSpec sequences but most of this sequences
are not matching anyways.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index aa22465bb56e..c100efc6a2c4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3115,7 +3115,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
-	int level = intel_ddi_dp_level(intel_dp);
 	enum transcoder transcoder = crtc_state->cpu_transcoder;
 
 	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
@@ -3190,9 +3189,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 * down this function.
 	 */
 
-	/* 7.e Configure voltage swing and related IO settings */
-	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
-				encoder->type);
+	/*
+	 * 7.e Configure voltage swing and related IO settings
+	 * It will be done in intel_dp_start_link_train(), no need to do twice
+	 */
 
 	/*
 	 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
@@ -3257,7 +3257,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	enum phy phy = intel_port_to_phy(dev_priv, port);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
-	int level = intel_ddi_dp_level(intel_dp);
 
 	if (INTEL_GEN(dev_priv) < 11)
 		drm_WARN_ON(&dev_priv->drm,
@@ -3279,16 +3278,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 
 	icl_program_mg_dp_mode(dig_port, crtc_state);
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
-					level, encoder->type);
-	else if (IS_CANNONLAKE(dev_priv))
-		cnl_ddi_vswing_sequence(encoder, level, encoder->type);
-	else if (IS_GEN9_LP(dev_priv))
-		bxt_ddi_vswing_sequence(encoder, level, encoder->type);
-	else
-		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
-
 	if (intel_phy_is_combo(dev_priv, phy)) {
 		bool lane_reversal =
 			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
-- 
2.26.2

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[Intel-gfx] [PATCH 2/4] drm/i915/bios: Parse HOBL parameter

[José Roberto de Souza]

HOBL means hours of battery life, it is a power-saving feature
were supported motherboards can use a special voltage swing table
that uses less power.

So here parsing the VBT to check if this feature is supported.
While at it already added the VRR parameter too.

BSpec: 20150
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 3 +++
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 ++
 drivers/gpu/drm/i915/i915_drv.h               | 1 +
 3 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 839124647202..b3c453aa7623 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -722,6 +722,9 @@ parse_power_conservation_features(struct drm_i915_private *dev_priv,
 	 */
 	if (!(power->drrs & BIT(panel_type)))
 		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
+
+	if (bdb->version >= 232)
+		dev_priv->vbt.edp.hobl = power->hobl & BIT(panel_type);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index aef7fe932d1a..65f552f57e06 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -820,6 +820,8 @@ struct bdb_lfp_power {
 	u16 adb;
 	u16 lace_enabled_status;
 	struct agressiveness_profile_entry aggressivenes[16];
+	u16 hobl; /* 232+ */
+	u16 vrr; /* 233+ */
 } __packed;
 
 /*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 98f2c448cd92..1e060de3edc4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -690,6 +690,7 @@ struct intel_vbt_data {
 		bool initialized;
 		int bpp;
 		struct edp_power_seq pps;
+		bool hobl;
 	} edp;
 
 	struct {
-- 
2.26.2

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[Intel-gfx] [PATCH 3/4] drm/i915/display: Implement HOBL

[José Roberto de Souza]

Hours Of Battery Life is a new GEN12+ power-saving feature that allows
supported motherboards to use a special voltage swing table for eDP
panels that uses less power.

So here if supported by HW, OEM will set it in VBT and i915 will try
to train link with HOBL vswing table if link training fails it fall
back to the original table.

Just not sure if DP compliance should also use this new voltage swing
table too, cced some folks that worked in DP compliance.

BSpec: 49291
BSpec: 49399
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 48 +++++++++++++++++--
 .../drm/i915/display/intel_display_types.h    |  2 +
 .../drm/i915/display/intel_dp_link_training.c | 20 +++++++-
 drivers/gpu/drm/i915/i915_drv.h               |  2 +
 drivers/gpu/drm/i915/i915_reg.h               |  2 +
 5 files changed, 69 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c100efc6a2c4..a44e190de79f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -692,6 +692,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] =
 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
 };
 
+static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
+	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }
+};
+
 static const struct ddi_buf_trans *
 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 {
@@ -2297,14 +2301,51 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
 }
 
+/*
+ * If supported return HOBL vswing table and set registers to enable HOBL
+ * otherwise returns NULL and unset registers to enable HOBL.
+ */
+static const struct cnl_ddi_buf_trans *
+hobl_get_combo_buf_trans(struct drm_i915_private *dev_priv,
+			 struct intel_encoder *encoder, int type, int rate,
+			 u32 level, int *n_entries)
+{
+	const u32 hobl_en = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	struct intel_dp *intel_dp;
+
+	if (!HAS_HOBL(dev_priv) || type != INTEL_OUTPUT_EDP)
+		return NULL;
+
+	intel_dp = enc_to_intel_dp(encoder);
+	if (!intel_dp->try_hobl || rate > 540000) {
+		intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, 0);
+		return NULL;
+	}
+
+	drm_dbg_kms(&dev_priv->drm, "Enabling HOBL in PHY %c\n", phy_name(phy));
+	drm_WARN_ON_ONCE(&dev_priv->drm, level > 0);
+
+	intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, hobl_en);
+	/* Same table applies to TGL, RKL and DG1 */
+	*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
+	return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
+}
+
 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
-					u32 level, enum phy phy, int type,
-					int rate)
+					 struct intel_encoder *encoder,
+					 u32 level, enum phy phy, int type,
+					 int rate)
 {
 	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
 	u32 n_entries, val;
 	int ln;
 
+	ddi_translations = hobl_get_combo_buf_trans(dev_priv, encoder, type,
+						    rate, level, &n_entries);
+	if (ddi_translations)
+		goto hobl_found;
+
 	if (INTEL_GEN(dev_priv) >= 12)
 		ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
 							   &n_entries);
@@ -2317,6 +2358,7 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
 	if (!ddi_translations)
 		return;
 
+hobl_found:
 	if (level >= n_entries) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "DDI translation not found for level %d. Using %d instead.",
@@ -2424,7 +2466,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
 
 	/* 5. Program swing and de-emphasis */
-	icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
+	icl_ddi_combo_vswing_program(dev_priv, encoder, level, phy, type, rate);
 
 	/* 6. Set training enable to trigger update */
 	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 30b2767578dc..9e7dbff7dd43 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1365,6 +1365,8 @@ struct intel_dp {
 
 	/* Display stream compression testing */
 	bool force_dsc_en;
+
+	bool try_hobl;
 };
 
 enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index e4f1843170b7..db078780542f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -37,12 +37,24 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			       const u8 link_status[DP_LINK_STATUS_SIZE])
 {
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 v = 0;
 	u8 p = 0;
 	int lane;
 	u8 voltage_max;
 	u8 preemph_max;
 
+	if (intel_dp->try_hobl) {
+		/*
+		 * Do not adjust, try now with the regular table using VSwing 0
+		 * and pre-emp 0
+		 */
+		intel_dp->try_hobl = false;
+		drm_dbg_kms(&dev_priv->drm, "HOBL vswing table failed link "
+			    "training, switching back to regular table\n");
+		return;
+	}
+
 	for (lane = 0; lane < intel_dp->lane_count; lane++) {
 		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
@@ -92,9 +104,13 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 }
 
 static bool
-intel_dp_reset_link_train(struct intel_dp *intel_dp,
-			u8 dp_train_pat)
+intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat)
 {
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl)
+		intel_dp->try_hobl = true;
+
 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 	intel_dp_set_signal_levels(intel_dp);
 	return intel_dp_set_link_train(intel_dp, dp_train_pat);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e060de3edc4..8c2fb4da70fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1678,6 +1678,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 		(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
 
+#define HAS_HOBL(dev_priv) (INTEL_GEN(dev_priv) >= 12)
+
 static inline bool intel_vtd_active(void)
 {
 #ifdef CONFIG_INTEL_IOMMU
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9d50fe0f375..a7a8d12fa49d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1896,6 +1896,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
 #define  PWR_DOWN_LN_MASK		(0xf << 4)
 #define  PWR_DOWN_LN_SHIFT		4
+#define  EDP4K2K_MODE_OVRD_EN		(1 << 3)
+#define  EDP4K2K_MODE_OVRD_OPTIMIZED	(1 << 2)
 
 #define ICL_PORT_CL_DW12(phy)		_MMIO(_ICL_PORT_CL_DW(12, phy))
 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Implement HOBL

[Ville Syrjälä]

On Thu, May 28, 2020 at 01:03:55PM -0700, José Roberto de Souza wrote:
> Hours Of Battery Life is a new GEN12+ power-saving feature that allows
> supported motherboards to use a special voltage swing table for eDP
> panels that uses less power.
> 
> So here if supported by HW, OEM will set it in VBT and i915 will try
> to train link with HOBL vswing table if link training fails it fall
> back to the original table.
> 
> Just not sure if DP compliance should also use this new voltage swing
> table too, cced some folks that worked in DP compliance.
> 
> BSpec: 49291
> BSpec: 49399
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 48 +++++++++++++++++--
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  .../drm/i915/display/intel_dp_link_training.c | 20 +++++++-
>  drivers/gpu/drm/i915/i915_drv.h               |  2 +
>  drivers/gpu/drm/i915/i915_reg.h               |  2 +
>  5 files changed, 69 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c100efc6a2c4..a44e190de79f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -692,6 +692,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] =
>  	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
>  };
>  
> +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }
> +};

This doesn't seem to mesh well with the notion of "at least
everything up to vswing 2/preemph 2 is mandatory", as laid 
out in https://patchwork.freedesktop.org/series/77198/

Hmm. I was going to add some WARNs there to make sure
.{voltage,preemph}_max() always return level 2 or level 3.
But looks like I failed to actually do it.

> +
>  static const struct ddi_buf_trans *
>  bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
>  {
> @@ -2297,14 +2301,51 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
>  }
>  
> +/*
> + * If supported return HOBL vswing table and set registers to enable HOBL
> + * otherwise returns NULL and unset registers to enable HOBL.
> + */
> +static const struct cnl_ddi_buf_trans *
> +hobl_get_combo_buf_trans(struct drm_i915_private *dev_priv,
> +			 struct intel_encoder *encoder, int type, int rate,
> +			 u32 level, int *n_entries)
> +{
> +	const u32 hobl_en = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
> +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> +	struct intel_dp *intel_dp;
> +
> +	if (!HAS_HOBL(dev_priv) || type != INTEL_OUTPUT_EDP)
> +		return NULL;
> +
> +	intel_dp = enc_to_intel_dp(encoder);
> +	if (!intel_dp->try_hobl || rate > 540000) {
> +		intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, 0);
> +		return NULL;
> +	}
> +
> +	drm_dbg_kms(&dev_priv->drm, "Enabling HOBL in PHY %c\n", phy_name(phy));
> +	drm_WARN_ON_ONCE(&dev_priv->drm, level > 0);
> +
> +	intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, hobl_en);
> +	/* Same table applies to TGL, RKL and DG1 */
> +	*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
> +	return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> +}
> +
>  static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> -					u32 level, enum phy phy, int type,
> -					int rate)
> +					 struct intel_encoder *encoder,
> +					 u32 level, enum phy phy, int type,
> +					 int rate)
>  {
>  	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
>  	u32 n_entries, val;
>  	int ln;
>  
> +	ddi_translations = hobl_get_combo_buf_trans(dev_priv, encoder, type,
> +						    rate, level, &n_entries);
> +	if (ddi_translations)
> +		goto hobl_found;
> +
>  	if (INTEL_GEN(dev_priv) >= 12)
>  		ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
>  							   &n_entries);
> @@ -2317,6 +2358,7 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
>  	if (!ddi_translations)
>  		return;
>  
> +hobl_found:
>  	if (level >= n_entries) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "DDI translation not found for level %d. Using %d instead.",
> @@ -2424,7 +2466,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>  	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
>  
>  	/* 5. Program swing and de-emphasis */
> -	icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
> +	icl_ddi_combo_vswing_program(dev_priv, encoder, level, phy, type, rate);
>  
>  	/* 6. Set training enable to trigger update */
>  	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 30b2767578dc..9e7dbff7dd43 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1365,6 +1365,8 @@ struct intel_dp {
>  
>  	/* Display stream compression testing */
>  	bool force_dsc_en;
> +
> +	bool try_hobl;
>  };
>  
>  enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index e4f1843170b7..db078780542f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -37,12 +37,24 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>  void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  			       const u8 link_status[DP_LINK_STATUS_SIZE])
>  {
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 v = 0;
>  	u8 p = 0;
>  	int lane;
>  	u8 voltage_max;
>  	u8 preemph_max;
>  
> +	if (intel_dp->try_hobl) {
> +		/*
> +		 * Do not adjust, try now with the regular table using VSwing 0
> +		 * and pre-emp 0
> +		 */
> +		intel_dp->try_hobl = false;
> +		drm_dbg_kms(&dev_priv->drm, "HOBL vswing table failed link "
> +			    "training, switching back to regular table\n");
> +		return;
> +	}
> +
>  	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>  		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>  		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> @@ -92,9 +104,13 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  }
>  
>  static bool
> -intel_dp_reset_link_train(struct intel_dp *intel_dp,
> -			u8 dp_train_pat)
> +intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat)
>  {
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl)
> +		intel_dp->try_hobl = true;
> +
>  	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
>  	intel_dp_set_signal_levels(intel_dp);
>  	return intel_dp_set_link_train(intel_dp, dp_train_pat);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1e060de3edc4..8c2fb4da70fd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1678,6 +1678,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define INTEL_DISPLAY_ENABLED(dev_priv) \
>  		(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
>  
> +#define HAS_HOBL(dev_priv) (INTEL_GEN(dev_priv) >= 12)
> +
>  static inline bool intel_vtd_active(void)
>  {
>  #ifdef CONFIG_INTEL_IOMMU
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e9d50fe0f375..a7a8d12fa49d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1896,6 +1896,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
>  #define  PWR_DOWN_LN_MASK		(0xf << 4)
>  #define  PWR_DOWN_LN_SHIFT		4
> +#define  EDP4K2K_MODE_OVRD_EN		(1 << 3)
> +#define  EDP4K2K_MODE_OVRD_OPTIMIZED	(1 << 2)
>  
>  #define ICL_PORT_CL_DW12(phy)		_MMIO(_ICL_PORT_CL_DW(12, phy))
>  #define   ICL_LANE_ENABLE_AUX		(1 << 0)
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Implement HOBL

[Souza, Jose]

On Fri, 2020-05-29 at 10:00 +0300, Ville Syrjälä wrote:
> On Thu, May 28, 2020 at 01:03:55PM -0700, José Roberto de Souza wrote:
> > Hours Of Battery Life is a new GEN12+ power-saving feature that allows
> > supported motherboards to use a special voltage swing table for eDP
> > panels that uses less power.
> > 
> > So here if supported by HW, OEM will set it in VBT and i915 will try
> > to train link with HOBL vswing table if link training fails it fall
> > back to the original table.
> > 
> > Just not sure if DP compliance should also use this new voltage swing
> > table too, cced some folks that worked in DP compliance.
> > 
> > BSpec: 49291
> > BSpec: 49399
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c      | 48 +++++++++++++++++--
> >  .../drm/i915/display/intel_display_types.h    |  2 +
> >  .../drm/i915/display/intel_dp_link_training.c | 20 +++++++-
> >  drivers/gpu/drm/i915/i915_drv.h               |  2 +
> >  drivers/gpu/drm/i915/i915_reg.h               |  2 +
> >  5 files changed, 69 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index c100efc6a2c4..a44e190de79f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -692,6 +692,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] =
> >  	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> >  };
> >  
> > +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
> > +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }
> > +};
> 
> This doesn't seem to mesh well with the notion of "at least
> everything up to vswing 2/preemph 2 is mandatory", as laid 
> out in https://patchwork.freedesktop.org/series/77198/
> 
> Hmm. I was going to add some WARNs there to make sure
> .{voltage,preemph}_max() always return level 2 or level 3.
> But looks like I failed to actually do it.

Even if you had, intel_dp_voltage_max() is not aware of this new table and if/when it is executed is because the voltage 0 and preemph 0 of the
regular table also failed the link training. 

> 
> > +
> >  static const struct ddi_buf_trans *
> >  bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> >  {
> > @@ -2297,14 +2301,51 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> >  	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
> >  }
> >  
> > +/*
> > + * If supported return HOBL vswing table and set registers to enable HOBL
> > + * otherwise returns NULL and unset registers to enable HOBL.
> > + */
> > +static const struct cnl_ddi_buf_trans *
> > +hobl_get_combo_buf_trans(struct drm_i915_private *dev_priv,
> > +			 struct intel_encoder *encoder, int type, int rate,
> > +			 u32 level, int *n_entries)
> > +{
> > +	const u32 hobl_en = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
> > +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> > +	struct intel_dp *intel_dp;
> > +
> > +	if (!HAS_HOBL(dev_priv) || type != INTEL_OUTPUT_EDP)
> > +		return NULL;
> > +
> > +	intel_dp = enc_to_intel_dp(encoder);
> > +	if (!intel_dp->try_hobl || rate > 540000) {
> > +		intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, 0);
> > +		return NULL;
> > +	}
> > +
> > +	drm_dbg_kms(&dev_priv->drm, "Enabling HOBL in PHY %c\n", phy_name(phy));
> > +	drm_WARN_ON_ONCE(&dev_priv->drm, level > 0);
> > +
> > +	intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, hobl_en);
> > +	/* Same table applies to TGL, RKL and DG1 */
> > +	*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
> > +	return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> > +}
> > +
> >  static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > -					u32 level, enum phy phy, int type,
> > -					int rate)
> > +					 struct intel_encoder *encoder,
> > +					 u32 level, enum phy phy, int type,
> > +					 int rate)
> >  {
> >  	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> >  	u32 n_entries, val;
> >  	int ln;
> >  
> > +	ddi_translations = hobl_get_combo_buf_trans(dev_priv, encoder, type,
> > +						    rate, level, &n_entries);
> > +	if (ddi_translations)
> > +		goto hobl_found;
> > +
> >  	if (INTEL_GEN(dev_priv) >= 12)
> >  		ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
> >  							   &n_entries);
> > @@ -2317,6 +2358,7 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> >  	if (!ddi_translations)
> >  		return;
> >  
> > +hobl_found:
> >  	if (level >= n_entries) {
> >  		drm_dbg_kms(&dev_priv->drm,
> >  			    "DDI translation not found for level %d. Using %d instead.",
> > @@ -2424,7 +2466,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> >  	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
> >  
> >  	/* 5. Program swing and de-emphasis */
> > -	icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
> > +	icl_ddi_combo_vswing_program(dev_priv, encoder, level, phy, type, rate);
> >  
> >  	/* 6. Set training enable to trigger update */
> >  	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 30b2767578dc..9e7dbff7dd43 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1365,6 +1365,8 @@ struct intel_dp {
> >  
> >  	/* Display stream compression testing */
> >  	bool force_dsc_en;
> > +
> > +	bool try_hobl;
> >  };
> >  
> >  enum lspcon_vendor {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index e4f1843170b7..db078780542f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -37,12 +37,24 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
> >  void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> >  			       const u8 link_status[DP_LINK_STATUS_SIZE])
> >  {
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >  	u8 v = 0;
> >  	u8 p = 0;
> >  	int lane;
> >  	u8 voltage_max;
> >  	u8 preemph_max;
> >  
> > +	if (intel_dp->try_hobl) {
> > +		/*
> > +		 * Do not adjust, try now with the regular table using VSwing 0
> > +		 * and pre-emp 0
> > +		 */
> > +		intel_dp->try_hobl = false;
> > +		drm_dbg_kms(&dev_priv->drm, "HOBL vswing table failed link "
> > +			    "training, switching back to regular table\n");
> > +		return;
> > +	}
> > +
> >  	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> >  		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> >  		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> > @@ -92,9 +104,13 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> >  }
> >  
> >  static bool
> > -intel_dp_reset_link_train(struct intel_dp *intel_dp,
> > -			u8 dp_train_pat)
> > +intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat)
> >  {
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > +	if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl)
> > +		intel_dp->try_hobl = true;
> > +
> >  	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> >  	intel_dp_set_signal_levels(intel_dp);
> >  	return intel_dp_set_link_train(intel_dp, dp_train_pat);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 1e060de3edc4..8c2fb4da70fd 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1678,6 +1678,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >  #define INTEL_DISPLAY_ENABLED(dev_priv) \
> >  		(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
> >  
> > +#define HAS_HOBL(dev_priv) (INTEL_GEN(dev_priv) >= 12)
> > +
> >  static inline bool intel_vtd_active(void)
> >  {
> >  #ifdef CONFIG_INTEL_IOMMU
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e9d50fe0f375..a7a8d12fa49d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1896,6 +1896,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
> >  #define  PWR_DOWN_LN_MASK		(0xf << 4)
> >  #define  PWR_DOWN_LN_SHIFT		4
> > +#define  EDP4K2K_MODE_OVRD_EN		(1 << 3)
> > +#define  EDP4K2K_MODE_OVRD_OPTIMIZED	(1 << 2)
> >  
> >  #define ICL_PORT_CL_DW12(phy)		_MMIO(_ICL_PORT_CL_DW(12, phy))
> >  #define   ICL_LANE_ENABLE_AUX		(1 << 0)
> > -- 
> > 2.26.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH 4/4] drm/i915/display: Enable HOBL regardless the VBT value

[José Roberto de Souza]

HOBL worked in my TGL RVP even without the necessary HW support, also
it worked in more than half of the TGL machines in CI so it is worthy
to enable it by default.
Even if link training fails with this new vswing table it will only
cause one additional link training, that is worthy the try to get the
additional power-savings.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index db078780542f..86de1187d363 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -108,7 +108,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl)
+	if (HAS_HOBL(dev_priv) && intel_dp_is_edp(intel_dp))
 		intel_dp->try_hobl = true;
 
 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
-- 
2.26.2

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice
URL   : https://patchwork.freedesktop.org/series/77758/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice
URL   : https://patchwork.freedesktop.org/series/77758/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8549 -> Patchwork_17806
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/index.html

Known issues
------------

  Here are the changes found in Patchwork_17806 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-u2:          [PASS][1] -> [FAIL][2] ([i915#262])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-icl-u2:          [PASS][3] -> [FAIL][4] ([i915#976])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html

  
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#976]: https://gitlab.freedesktop.org/drm/intel/issues/976


Participating hosts (50 -> 41)
------------------------------

  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-n2820 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_8549 -> Patchwork_17806

  CI-20190529: 20190529
  CI_DRM_8549: e50e9c6bf4efd00b02d91ff470993bbd0db94f67 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5682: e5371a99a877be134c6ad5361a5f03843a66f775 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17806: 243da8b64910288d152b148272e64fa8301d62f4 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

243da8b64910 drm/i915/display: Enable HOBL regardless the VBT value
957a89b1b93d drm/i915/display: Implement HOBL
ee42cab5f9b5 drm/i915/bios: Parse HOBL parameter
245f5bdf6d69 drm/i915/display/hsw+: Do not program the same vswing entry twice

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice
URL   : https://patchwork.freedesktop.org/series/77758/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8549_full -> Patchwork_17806_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_17806_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17806_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17806_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gen9_exec_parse@bb-chained:
    - shard-glk:          NOTRUN -> [TIMEOUT][1] +6 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-glk9/igt@gen9_exec_parse@bb-chained.html

  
Known issues
------------

  Here are the changes found in Patchwork_17806_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [PASS][2] -> [INCOMPLETE][3] ([i915#1602] / [i915#456])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-tglb8/igt@gem_exec_suspend@basic-s0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-tglb5/igt@gem_exec_suspend@basic-s0.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
    - shard-kbl:          [PASS][4] -> [FAIL][5] ([i915#54] / [i915#93] / [i915#95])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][8] -> [FAIL][9] ([i915#1188])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][10] -> [FAIL][11] ([fdo#108145] / [i915#265]) +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][12] -> [SKIP][13] ([fdo#109441]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [PASS][14] -> [FAIL][15] ([i915#31])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-hsw4/igt@kms_setmode@basic.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-hsw4/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-suspend:
    - shard-skl:          [INCOMPLETE][16] ([i915#69]) -> [PASS][17] +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-skl4/igt@gem_eio@in-flight-suspend.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-skl9/igt@gem_eio@in-flight-suspend.html

  * {igt@gem_exec_reloc@basic-concurrent0}:
    - shard-apl:          [FAIL][18] ([i915#1930]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-apl7/igt@gem_exec_reloc@basic-concurrent0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-apl3/igt@gem_exec_reloc@basic-concurrent0.html

  * {igt@gem_exec_reloc@basic-concurrent16}:
    - shard-skl:          [FAIL][20] ([i915#1930]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-skl2/igt@gem_exec_reloc@basic-concurrent16.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-skl7/igt@gem_exec_reloc@basic-concurrent16.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-kbl:          [FAIL][22] ([fdo#103375]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-kbl2/igt@i915_pm_rpm@system-suspend.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-kbl7/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_suspend@forcewake:
    - shard-skl:          [INCOMPLETE][24] ([i915#636] / [i915#69]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-skl1/igt@i915_suspend@forcewake.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-skl1/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-glk:          [DMESG-WARN][26] ([i915#1926]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-glk8/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-glk1/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * {igt@kms_flip@flip-vs-suspend-interruptible@a-edp1}:
    - shard-skl:          [INCOMPLETE][28] ([i915#198]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html

  * {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
    - shard-apl:          [DMESG-WARN][30] ([i915#180]) -> [PASS][31] +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [DMESG-WARN][32] ([i915#180]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][34] ([fdo#108145] / [i915#265]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [SKIP][36] ([fdo#109441]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][38] ([i915#468]) -> [FAIL][39] ([i915#454])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-tglb1/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_content_protection@legacy:
    - shard-apl:          [FAIL][40] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][41] ([i915#1319] / [i915#1635])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-apl7/igt@kms_content_protection@legacy.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-apl3/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-glk:          [DMESG-WARN][42] ([i915#1926]) -> [DMESG-WARN][43] ([i915#1927])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-glk1/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-glk7/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-apl:          [FAIL][44] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][45] ([fdo#108145] / [i915#265])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8549/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926
  [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927
  [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
  [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_8549 -> Patchwork_17806

  CI-20190529: 20190529
  CI_DRM_8549: e50e9c6bf4efd00b02d91ff470993bbd0db94f67 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5682: e5371a99a877be134c6ad5361a5f03843a66f775 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17806: 243da8b64910288d152b148272e64fa8301d62f4 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17806/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice

[Ville Syrjälä]

On Thu, May 28, 2020 at 01:03:53PM -0700, José Roberto de Souza wrote:
> It will be programed right before the link training, so no need to do
> it twice.
> It will not strictly follow BSpec sequences but most of this sequences
> are not matching anyways.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++---------------
>  1 file changed, 4 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index aa22465bb56e..c100efc6a2c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3115,7 +3115,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> -	int level = intel_ddi_dp_level(intel_dp);
>  	enum transcoder transcoder = crtc_state->cpu_transcoder;
>  
>  	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> @@ -3190,9 +3189,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	 * down this function.
>  	 */
>  
> -	/* 7.e Configure voltage swing and related IO settings */
> -	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> -				encoder->type);
> +	/*
> +	 * 7.e Configure voltage swing and related IO settings
> +	 * It will be done in intel_dp_start_link_train(), no need to do twice
> +	 */

Hmm. Do we still set it up before turning on the port?

>  
>  	/*
>  	 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
> @@ -3257,7 +3257,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> -	int level = intel_ddi_dp_level(intel_dp);
>  
>  	if (INTEL_GEN(dev_priv) < 11)
>  		drm_WARN_ON(&dev_priv->drm,
> @@ -3279,16 +3278,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  
>  	icl_program_mg_dp_mode(dig_port, crtc_state);
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> -		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> -					level, encoder->type);
> -	else if (IS_CANNONLAKE(dev_priv))
> -		cnl_ddi_vswing_sequence(encoder, level, encoder->type);
> -	else if (IS_GEN9_LP(dev_priv))
> -		bxt_ddi_vswing_sequence(encoder, level, encoder->type);
> -	else
> -		intel_prepare_dp_ddi_buffers(encoder, crtc_state);

This last one definitely has to stay IIRC. HSW/BDW/SKL buf trans
stuff works quite bit differently than the BXT+ style more manual
programming.

> -
>  	if (intel_phy_is_combo(dev_priv, phy)) {
>  		bool lane_reversal =
>  			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice

[Souza, Jose]

On Fri, 2020-05-29 at 09:51 +0300, Ville Syrjälä wrote:
> On Thu, May 28, 2020 at 01:03:53PM -0700, José Roberto de Souza wrote:
> > It will be programed right before the link training, so no need to do
> > it twice.
> > It will not strictly follow BSpec sequences but most of this sequences
> > are not matching anyways.
> > 
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++---------------
> >  1 file changed, 4 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index aa22465bb56e..c100efc6a2c4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3115,7 +3115,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> >  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >  	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> > -	int level = intel_ddi_dp_level(intel_dp);
> >  	enum transcoder transcoder = crtc_state->cpu_transcoder;
> >  
> >  	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> > @@ -3190,9 +3189,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> >  	 * down this function.
> >  	 */
> >  
> > -	/* 7.e Configure voltage swing and related IO settings */
> > -	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> > -				encoder->type);
> > +	/*
> > +	 * 7.e Configure voltage swing and related IO settings
> > +	 * It will be done in intel_dp_start_link_train(), no need to do twice
> > +	 */
> 
> Hmm. Do we still set it up before turning on the port?

No.

intel_dp_start_link_train()
	intel_dp_link_training_clock_recovery()
		intel_dp->prepare_link_retrain(intel_dp)/intel_ddi_prepare_link_retrain();/* Port is enabled here in training mode */

		....

		intel_dp_reset_link_train()
			intel_dp_set_signal_levels() /* Vswing table is set here */
Guess is safer keep programming it twice then?


> 
> >  
> >  	/*
> >  	 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
> > @@ -3257,7 +3257,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> >  	enum phy phy = intel_port_to_phy(dev_priv, port);
> >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >  	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> > -	int level = intel_ddi_dp_level(intel_dp);
> >  
> >  	if (INTEL_GEN(dev_priv) < 11)
> >  		drm_WARN_ON(&dev_priv->drm,
> > @@ -3279,16 +3278,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> >  
> >  	icl_program_mg_dp_mode(dig_port, crtc_state);
> >  
> > -	if (INTEL_GEN(dev_priv) >= 11)
> > -		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> > -					level, encoder->type);
> > -	else if (IS_CANNONLAKE(dev_priv))
> > -		cnl_ddi_vswing_sequence(encoder, level, encoder->type);
> > -	else if (IS_GEN9_LP(dev_priv))
> > -		bxt_ddi_vswing_sequence(encoder, level, encoder->type);
> > -	else
> > -		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
> 
> This last one definitely has to stay IIRC. HSW/BDW/SKL buf trans
> stuff works quite bit differently than the BXT+ style more manual
> programming.
> 
> > -
> >  	if (intel_phy_is_combo(dev_priv, phy)) {
> >  		bool lane_reversal =
> >  			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> > -- 
> > 2.26.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice

[Ville Syrjälä]

On Fri, May 29, 2020 at 08:52:38PM +0000, Souza, Jose wrote:
> On Fri, 2020-05-29 at 09:51 +0300, Ville Syrjälä wrote:
> > On Thu, May 28, 2020 at 01:03:53PM -0700, José Roberto de Souza wrote:
> > > It will be programed right before the link training, so no need to do
> > > it twice.
> > > It will not strictly follow BSpec sequences but most of this sequences
> > > are not matching anyways.
> > > 
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++---------------
> > >  1 file changed, 4 insertions(+), 15 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index aa22465bb56e..c100efc6a2c4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -3115,7 +3115,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > >  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> > >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > >  	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> > > -	int level = intel_ddi_dp_level(intel_dp);
> > >  	enum transcoder transcoder = crtc_state->cpu_transcoder;
> > >  
> > >  	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> > > @@ -3190,9 +3189,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > >  	 * down this function.
> > >  	 */
> > >  
> > > -	/* 7.e Configure voltage swing and related IO settings */
> > > -	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> > > -				encoder->type);
> > > +	/*
> > > +	 * 7.e Configure voltage swing and related IO settings
> > > +	 * It will be done in intel_dp_start_link_train(), no need to do twice
> > > +	 */
> > 
> > Hmm. Do we still set it up before turning on the port?
> 
> No.
> 
> intel_dp_start_link_train()
> 	intel_dp_link_training_clock_recovery()
> 		intel_dp->prepare_link_retrain(intel_dp)/intel_ddi_prepare_link_retrain();/* Port is enabled here in training mode */
> 
> 		....
> 
> 		intel_dp_reset_link_train()
> 			intel_dp_set_signal_levels() /* Vswing table is set here */
> Guess is safer keep programming it twice then?

Probably.

> 
> 
> > 
> > >  
> > >  	/*
> > >  	 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
> > > @@ -3257,7 +3257,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > >  	enum phy phy = intel_port_to_phy(dev_priv, port);
> > >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > >  	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> > > -	int level = intel_ddi_dp_level(intel_dp);
> > >  
> > >  	if (INTEL_GEN(dev_priv) < 11)
> > >  		drm_WARN_ON(&dev_priv->drm,
> > > @@ -3279,16 +3278,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > >  
> > >  	icl_program_mg_dp_mode(dig_port, crtc_state);
> > >  
> > > -	if (INTEL_GEN(dev_priv) >= 11)
> > > -		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> > > -					level, encoder->type);
> > > -	else if (IS_CANNONLAKE(dev_priv))
> > > -		cnl_ddi_vswing_sequence(encoder, level, encoder->type);
> > > -	else if (IS_GEN9_LP(dev_priv))
> > > -		bxt_ddi_vswing_sequence(encoder, level, encoder->type);
> > > -	else
> > > -		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
> > 
> > This last one definitely has to stay IIRC. HSW/BDW/SKL buf trans
> > stuff works quite bit differently than the BXT+ style more manual
> > programming.
> > 
> > > -
> > >  	if (intel_phy_is_combo(dev_priv, phy)) {
> > >  		bool lane_reversal =
> > >  			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> > > -- 
> > > 2.26.2
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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