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From: Hans de Goede <hdegoede@redhat.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Jani Nikula" <jani.nikula@linux.intel.com>,
	"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Rafael J . Wysocki" <rjw@rjwysocki.net>,
	"Len Brown" <lenb@kernel.org>
Cc: linux-pwm@vger.kernel.org, linux-acpi@vger.kernel.org,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel@lists.freedesktop.org,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: [Intel-gfx] [PATCH v5 08/16] pwm: crc: Fix off-by-one error in the clock-divider calculations
Date: Fri, 17 Jul 2020 15:37:45 +0200
Message-ID: <20200717133753.127282-9-hdegoede@redhat.com> (raw)
In-Reply-To: <20200717133753.127282-1-hdegoede@redhat.com>

The CRC PWM controller has a clock-divider which divides the clock with
a value between 1-128. But as can seen from the PWM_DIV_CLK_xxx
defines, this range maps to a register value of 0-127.

So after calculating the clock-divider we must subtract 1 to get the
register value, unless the requested frequency was so high that the
calculation has already resulted in a (rounded) divider value of 0.

Note that before this fix, setting a period of PWM_MAX_PERIOD_NS which
corresponds to the max. divider value of 128 could have resulted in a
bug where the code would use 128 as divider-register value which would
have resulted in an actual divider value of 0 (and the enable bit being
set). A rounding error stopped this bug from actually happen. This
same rounding error means that after the subtraction of 1 it is impossible
to set the divider to 128. Also bump PWM_MAX_PERIOD_NS by 1 ns to allow
setting a divider of 128 (register-value 127).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v3:
- Introduce crc_pwm_calc_clk_div() here instead of later in the patch-set
  to reduce the amount of churn in the patch-set a bit
---
 drivers/pwm/pwm-crc.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
index c056eb9b858c..44ec7d5b63e1 100644
--- a/drivers/pwm/pwm-crc.c
+++ b/drivers/pwm/pwm-crc.c
@@ -22,7 +22,7 @@
 #define PWM_MAX_LEVEL		0xFF
 
 #define PWM_BASE_CLK_MHZ	6	/* 6 MHz */
-#define PWM_MAX_PERIOD_NS	5461333	/* 183 Hz */
+#define PWM_MAX_PERIOD_NS	5461334	/* 183 Hz */
 
 /**
  * struct crystalcove_pwm - Crystal Cove PWM controller
@@ -39,6 +39,18 @@ static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc)
 	return container_of(pc, struct crystalcove_pwm, chip);
 }
 
+static int crc_pwm_calc_clk_div(int period_ns)
+{
+	int clk_div;
+
+	clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
+	/* clk_div 1 - 128, maps to register values 0-127 */
+	if (clk_div > 0)
+		clk_div--;
+
+	return clk_div;
+}
+
 static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
 {
 	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
@@ -68,11 +80,10 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm,
 	}
 
 	if (pwm_get_period(pwm) != period_ns) {
-		int clk_div;
+		int clk_div = crc_pwm_calc_clk_div(period_ns);
 
 		/* changing the clk divisor, need to disable fisrt */
 		crc_pwm_disable(c, pwm);
-		clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
 
 		regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
 					clk_div | PWM_OUTPUT_ENABLE);
-- 
2.26.2

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  parent reply index

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-17 13:37 [Intel-gfx] [PATCH v5 00/16] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 02/16] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 03/16] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 04/16] pwm: lpss: Add range limit check for the base_unit register value Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 05/16] pwm: lpss: Add pwm_lpss_prepare_enable() helper Hans de Goede
2020-07-28 18:45   ` Andy Shevchenko
2020-07-28 19:49     ` Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 06/16] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume Hans de Goede
2020-07-28 18:57   ` Andy Shevchenko
2020-07-28 19:55     ` Hans de Goede
2020-07-29  8:12       ` Andy Shevchenko
2020-08-02 20:51         ` Hans de Goede
2020-08-03  8:41           ` Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 07/16] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 Hans de Goede
2020-07-28 19:36   ` Andy Shevchenko
2020-07-28 20:00     ` Hans de Goede
2020-07-29  8:13   ` Andy Shevchenko
2020-07-17 13:37 ` Hans de Goede [this message]
2020-07-29 10:28   ` [Intel-gfx] [PATCH v5 08/16] pwm: crc: Fix off-by-one error in the clock-divider calculations Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 09/16] pwm: crc: Fix period changes not having any effect Hans de Goede
2020-07-29 10:30   ` Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 10/16] pwm: crc: Enable/disable PWM output on enable/disable Hans de Goede
2020-07-29 10:32   ` Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 11/16] pwm: crc: Implement apply() method to support the new atomic PWM API Hans de Goede
2020-07-29 10:51   ` Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 12/16] pwm: crc: Implement get_state() method Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 13/16] drm/i915: panel: Add get_vbt_pwm_freq() helper Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 14/16] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller Hans de Goede
2020-07-17 13:44 ` [Intel-gfx] [PATCH v5 15/16] drm/i915: panel: Honor the VBT PWM min setting " Hans de Goede
2020-07-17 13:44   ` [Intel-gfx] [PATCH v5 16/16] drm/i915: panel: Use atomic PWM API " Hans de Goede
2020-07-27  7:41 ` [Intel-gfx] [PATCH v5 00/16] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Thierry Reding
2020-07-29  8:23   ` Andy Shevchenko
2020-07-29  9:32     ` Hans de Goede
2020-07-30  9:26       ` Thierry Reding
2020-08-01 14:33         ` Hans de Goede
2020-07-29 10:54 ` Andy Shevchenko
2020-08-01 14:38   ` Hans de Goede
2020-08-02 11:25     ` Andy Shevchenko
2020-08-02 19:43       ` Hans de Goede

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