[Intel-gfx] [PATCH 1/7] drm/i915: setup the LMEM region

[Intel-gfx] [PATCH 1/7] drm/i915: setup the LMEM region

[Matthew Auld]

Hook up the LMEM region. Addresses will start from zero, and for CPU
access we get LMEM_BAR which is just a 1:1 mapping of said region.

Based on a patch from Michel Thierry.

v2 by Jani:
- use intel_uncore_read/intel_uncore_write
- remove trailing blank line

v3: s/drm_info/drm_dbg for info which in non-pertinent for the user

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 37 +++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_region_lmem.h |  2 ++
 drivers/gpu/drm/i915/i915_reg.h             |  3 ++
 drivers/gpu/drm/i915/intel_memory_region.c  | 11 +++++-
 4 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 28a1d5e1fb92..bdd38efe0811 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -136,3 +136,40 @@ intel_setup_fake_lmem(struct drm_i915_private *i915)
 
 	return mem;
 }
+
+static struct intel_memory_region *
+setup_lmem(struct drm_i915_private *i915)
+{
+	struct pci_dev *pdev = i915->drm.pdev;
+	struct intel_memory_region *mem;
+	resource_size_t io_start;
+	resource_size_t size;
+
+	/* Enables Local Memory functionality in GAM */
+	intel_uncore_write(&i915->uncore, GEN12_LMEM_CFG_ADDR,
+			   intel_uncore_read(&i915->uncore, GEN12_LMEM_CFG_ADDR) | LMEM_ENABLE);
+
+	io_start = pci_resource_start(pdev, 2);
+	size = pci_resource_len(pdev, 2);
+
+	mem = intel_memory_region_create(i915,
+					 0,
+					 size,
+					 I915_GTT_PAGE_SIZE_4K,
+					 io_start,
+					 &intel_region_lmem_ops);
+	if (!IS_ERR(mem)) {
+		drm_dbg(&i915->drm, "Intel graphics LMEM: %pR\n", &mem->region);
+		drm_dbg(&i915->drm, "Intel graphics LMEM IO start: %pa\n",
+			 &mem->io_start);
+		drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n", &size);
+	}
+
+	return mem;
+}
+
+struct intel_memory_region *
+i915_gem_setup_lmem(struct drm_i915_private *i915)
+{
+	return setup_lmem(i915);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.h b/drivers/gpu/drm/i915/gt/intel_region_lmem.h
index 8ea43e538dab..b32222bd493c 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.h
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.h
@@ -8,6 +8,8 @@
 
 struct drm_i915_private;
 
+struct intel_memory_region *i915_gem_setup_lmem(struct drm_i915_private *i915);
+
 struct intel_memory_region *
 intel_setup_fake_lmem(struct drm_i915_private *i915);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e7e41a3c467e..28001b5a3cb5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12111,6 +12111,9 @@ enum skl_power_gate {
 
 #define GEN12_GLOBAL_MOCS(i)	_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
 
+#define GEN12_LMEM_CFG_ADDR		_MMIO(0xcf58)
+#define   LMEM_ENABLE			(1 << 31)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 1bfcdd89b241..9ce4a81c48b1 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -259,7 +259,16 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
 			mem = i915_gem_stolen_setup(i915);
 			break;
 		case INTEL_MEMORY_LOCAL:
-			mem = intel_setup_fake_lmem(i915);
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+			if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
+				if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
+				    i915->params.fake_lmem_start)
+					mem = intel_setup_fake_lmem(i915);
+			}
+#endif
+
+			if (IS_ERR(mem))
+				mem = i915_gem_setup_lmem(i915);
 			break;
 		}
 
-- 
2.26.2

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[Intel-gfx] [PATCH 2/7] drm/i915: reserve stolen for LMEM region

[Matthew Auld]

From: CQ Tang <cq.tang@intel.com>

The lmem region needs to remove the stolen part, which should just be a
case of snipping it off the end.

Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 12 ++++++++----
 drivers/gpu/drm/i915/i915_reg.h             |  2 ++
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index bdd38efe0811..30959c1e535f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -140,21 +140,24 @@ intel_setup_fake_lmem(struct drm_i915_private *i915)
 static struct intel_memory_region *
 setup_lmem(struct drm_i915_private *i915)
 {
+	struct intel_uncore *uncore = &i915->uncore;
 	struct pci_dev *pdev = i915->drm.pdev;
 	struct intel_memory_region *mem;
 	resource_size_t io_start;
-	resource_size_t size;
+	resource_size_t lmem_size;
 
 	/* Enables Local Memory functionality in GAM */
 	intel_uncore_write(&i915->uncore, GEN12_LMEM_CFG_ADDR,
 			   intel_uncore_read(&i915->uncore, GEN12_LMEM_CFG_ADDR) | LMEM_ENABLE);
 
+	/* Stolen starts from GSMBASE on DG1 */
+	lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE);
+
 	io_start = pci_resource_start(pdev, 2);
-	size = pci_resource_len(pdev, 2);
 
 	mem = intel_memory_region_create(i915,
 					 0,
-					 size,
+					 lmem_size,
 					 I915_GTT_PAGE_SIZE_4K,
 					 io_start,
 					 &intel_region_lmem_ops);
@@ -162,7 +165,8 @@ setup_lmem(struct drm_i915_private *i915)
 		drm_dbg(&i915->drm, "Intel graphics LMEM: %pR\n", &mem->region);
 		drm_dbg(&i915->drm, "Intel graphics LMEM IO start: %pa\n",
 			 &mem->io_start);
-		drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n", &size);
+		drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n",
+			 &lmem_size);
 	}
 
 	return mem;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 28001b5a3cb5..626ebbe64bfd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12114,6 +12114,8 @@ enum skl_power_gate {
 #define GEN12_LMEM_CFG_ADDR		_MMIO(0xcf58)
 #define   LMEM_ENABLE			(1 << 31)
 
+#define GEN12_GSMBASE			_MMIO(0x108100)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
-- 
2.26.2

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[Intel-gfx] [PATCH 3/7] drm/i915: introduce mem->reserved

[Matthew Auld]

From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

In the following patch we need to reserve regions unaccessible to the
driver during initialization, so add mem->reserved for collecting such
regions.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/intel_memory_region.c    |  2 +
 drivers/gpu/drm/i915/intel_memory_region.h    |  2 +
 .../drm/i915/selftests/intel_memory_region.c  | 89 +++++++++++++++++++
 3 files changed, 93 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 9ce4a81c48b1..79b07fa2436d 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -156,6 +156,7 @@ int intel_memory_region_init_buddy(struct intel_memory_region *mem)
 
 void intel_memory_region_release_buddy(struct intel_memory_region *mem)
 {
+	i915_buddy_free_list(&mem->mm, &mem->reserved);
 	i915_buddy_fini(&mem->mm);
 }
 
@@ -185,6 +186,7 @@ intel_memory_region_create(struct drm_i915_private *i915,
 	mutex_init(&mem->objects.lock);
 	INIT_LIST_HEAD(&mem->objects.list);
 	INIT_LIST_HEAD(&mem->objects.purgeable);
+	INIT_LIST_HEAD(&mem->reserved);
 
 	mutex_init(&mem->mm_lock);
 
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index 6ffc0673f005..8c9947bba3e8 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -89,6 +89,8 @@ struct intel_memory_region {
 	unsigned int id;
 	char name[8];
 
+	struct list_head reserved;
+
 	dma_addr_t remap_addr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index ce7adfa3bca0..79e5c5a6b563 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -144,6 +144,94 @@ static bool is_contiguous(struct drm_i915_gem_object *obj)
 	return true;
 }
 
+static int igt_reserve_range(struct intel_memory_region *mem,
+			     struct list_head *reserved,
+			     u64 offset,
+			     u64 size)
+{
+	int ret;
+	LIST_HEAD(blocks);
+
+	ret = i915_buddy_alloc_range(&mem->mm, &blocks, offset, size);
+	if (!ret)
+		list_splice_tail(&blocks, reserved);
+
+	return ret;
+}
+
+static int igt_mock_reserve(void *arg)
+{
+	struct drm_i915_gem_object *obj;
+	struct intel_memory_region *mem = arg;
+	resource_size_t avail = resource_size(&mem->region);
+	I915_RND_STATE(prng);
+	LIST_HEAD(objects);
+	LIST_HEAD(reserved);
+	u32 i, offset, count, *order;
+	u64 allocated, cur_avail;
+	const u32 chunk_size = SZ_32M;
+	int err = 0;
+
+	count = avail / chunk_size;
+	order = i915_random_order(count, &prng);
+	if (!order)
+		return 0;
+
+	/* Reserve a bunch of ranges within the region */
+	for (i = 0; i < count; ++i) {
+		u64 start = order[i] * chunk_size;
+		u64 size = i915_prandom_u32_max_state(chunk_size, &prng);
+
+		/* Allow for some really big holes */
+		if (!size)
+			continue;
+
+		size = round_up(size, PAGE_SIZE);
+		offset = igt_random_offset(&prng, 0, chunk_size, size,
+					   PAGE_SIZE);
+
+		err = igt_reserve_range(mem, &reserved, start + offset, size);
+		if (err) {
+			pr_err("%s failed to reserve range", __func__);
+			goto out_close;
+		}
+
+		/* XXX: maybe sanity check the block range here? */
+		avail -= size;
+	}
+
+	/* Try to see if we can allocate from the remaining space */
+	allocated = 0;
+	cur_avail = avail;
+	do {
+		u64 size = i915_prandom_u32_max_state(cur_avail, &prng);
+
+		size = max_t(u64, round_up(size, PAGE_SIZE), (u64)PAGE_SIZE);
+		obj = igt_object_create(mem, &objects, size, 0);
+
+		if (IS_ERR(obj)) {
+			if (PTR_ERR(obj) == -ENXIO)
+				break;
+
+			err = PTR_ERR(obj);
+			goto out_close;
+		}
+		cur_avail -= size;
+		allocated += size;
+	} while (1);
+
+	if (allocated != avail) {
+		pr_err("%s mismatch between allocation and free space", __func__);
+		err = -EINVAL;
+	}
+
+out_close:
+	kfree(order);
+	close_objects(mem, &objects);
+	i915_buddy_free_list(&mem->mm, &reserved);
+	return err;
+}
+
 static int igt_mock_contiguous(void *arg)
 {
 	struct intel_memory_region *mem = arg;
@@ -930,6 +1018,7 @@ static int perf_memcpy(void *arg)
 int intel_memory_region_mock_selftests(void)
 {
 	static const struct i915_subtest tests[] = {
+		SUBTEST(igt_mock_reserve),
 		SUBTEST(igt_mock_fill),
 		SUBTEST(igt_mock_contiguous),
 		SUBTEST(igt_mock_splintered_region),
-- 
2.26.2

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[Intel-gfx] [PATCH 4/7] drm/i915/dg1: Reserve first 1MB of local memory

[Matthew Auld]

From: Imre Deak <imre.deak@intel.com>

On DG1 A0/B0 steppings the first 1MB of local memory must be reserved.
One reason for this is that the 0xA0000-0xB0000 range is not accessible
by the display, probably since this region is redirected to another
memory location for legacy VGA compatibility.

BSpec: 50586
Testcase: igt/kms_big_fb/linear-64bpp-rotate-0

v2:
- Reserve the memory on B0 as well.

v3: replace DRM_DEBUG/DRM_ERROR with drm_dbg/drm_err

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 53 +++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 30959c1e535f..13ec2ecce2e7 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -137,6 +137,49 @@ intel_setup_fake_lmem(struct drm_i915_private *i915)
 	return mem;
 }
 
+static void get_legacy_lowmem_region(struct intel_uncore *uncore,
+				     u64 *start, u32 *size)
+{
+	*start = 0;
+	*size = 0;
+
+	if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))
+		return;
+
+	*size = SZ_1M;
+
+	drm_dbg(&uncore->i915->drm, "LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n",
+		*start, *start + *size);
+}
+
+static int reserve_lowmem_region(struct intel_uncore *uncore,
+				 struct intel_memory_region *mem)
+{
+
+	u64 reserve_start;
+	u64 reserve_end;
+	u64 region_start;
+	u32 region_size;
+	int ret;
+
+	get_legacy_lowmem_region(uncore, &region_start, &region_size);
+	reserve_start = region_start;
+	reserve_end = region_start + region_size;
+
+	if (!reserve_end)
+		return 0;
+
+	drm_dbg(&uncore->i915->drm, "LMEM: reserving low-memory region [0x%llx-0x%llx]\n",
+		reserve_start, reserve_end);
+	ret = i915_buddy_alloc_range(&mem->mm, &mem->reserved,
+				     reserve_start,
+				     reserve_end - reserve_start);
+	if (ret)
+		drm_err(&uncore->i915->drm, "LMEM: reserving low memory region failed\n");
+
+	return ret;
+}
+
 static struct intel_memory_region *
 setup_lmem(struct drm_i915_private *i915)
 {
@@ -161,6 +204,16 @@ setup_lmem(struct drm_i915_private *i915)
 					 I915_GTT_PAGE_SIZE_4K,
 					 io_start,
 					 &intel_region_lmem_ops);
+	if (!IS_ERR(mem)) {
+		int err;
+
+		err = reserve_lowmem_region(uncore, mem);
+		if (err) {
+			intel_memory_region_put(mem);
+			return ERR_PTR(err);
+		}
+	}
+
 	if (!IS_ERR(mem)) {
 		drm_dbg(&i915->drm, "Intel graphics LMEM: %pR\n", &mem->region);
 		drm_dbg(&i915->drm, "Intel graphics LMEM IO start: %pa\n",
-- 
2.26.2

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[Intel-gfx] [PATCH 5/7] drm/i915: allocate context from LMEM

[Matthew Auld]

Prefer allocating the context from LMEM on dgfx.

Based on a patch from Michel Thierry.

v2: flatten the chain

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 33b529dcb05f..8508b8d701c1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3,6 +3,8 @@
  * Copyright © 2014 Intel Corporation
  */
 
+#include "gem/i915_gem_lmem.h"
+
 #include "gen8_engine_cs.h"
 #include "i915_drv.h"
 #include "i915_perf.h"
@@ -808,7 +810,9 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
 		context_size += PAGE_SIZE;
 	}
 
-	obj = i915_gem_object_create_shmem(engine->i915, context_size);
+	obj = i915_gem_object_create_lmem(engine->i915, context_size, 0);
+	if (IS_ERR(obj))
+		obj = i915_gem_object_create_shmem(engine->i915, context_size);
 	if (IS_ERR(obj))
 		return ERR_CAST(obj);
 
-- 
2.26.2

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[Intel-gfx] [PATCH 6/7] drm/i915: move engine scratch to LMEM

[Matthew Auld]

Prefer allocating the engine scratch from LMEM on dgfx.

v2: flatten the chain

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d8e1ab412634..2e46709e04c7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -4,6 +4,8 @@
  */
 
 #include "debugfs_gt.h"
+
+#include "gem/i915_gem_lmem.h"
 #include "i915_drv.h"
 #include "intel_context.h"
 #include "intel_gt.h"
@@ -344,11 +346,13 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
 	struct i915_vma *vma;
 	int ret;
 
-	obj = i915_gem_object_create_stolen(i915, size);
+	obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
+	if (IS_ERR(obj))
+		obj = i915_gem_object_create_stolen(i915, size);
 	if (IS_ERR(obj))
 		obj = i915_gem_object_create_internal(i915, size);
 	if (IS_ERR(obj)) {
-		DRM_ERROR("Failed to allocate scratch page\n");
+		drm_err(&i915->drm, "Failed to allocate scratch page\n");
 		return PTR_ERR(obj);
 	}
 
-- 
2.26.2

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[Intel-gfx] [PATCH 7/7] drm/i915: allocate cmd ring in lmem

[Matthew Auld]

From: Michel Thierry <michel.thierry@intel.com>

Prefer allocating the cmd ring from LMEM on dgfx.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ring.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index 29c87b3c23bc..aee0a77c77e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -3,6 +3,7 @@
  * Copyright © 2019 Intel Corporation
  */
 
+#include "gem/i915_gem_lmem.h"
 #include "gem/i915_gem_object.h"
 
 #include "i915_drv.h"
@@ -108,8 +109,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 
-	obj = ERR_PTR(-ENODEV);
-	if (i915_ggtt_has_aperture(ggtt))
+	obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
+	if (IS_ERR(obj) && i915_ggtt_has_aperture(ggtt))
 		obj = i915_gem_object_create_stolen(i915, size);
 	if (IS_ERR(obj))
 		obj = i915_gem_object_create_internal(i915, size);
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 1/7] drm/i915: setup the LMEM region

[Tvrtko Ursulin]

On 26/01/2021 09:46, Matthew Auld wrote:
> Hook up the LMEM region. Addresses will start from zero, and for CPU
> access we get LMEM_BAR which is just a 1:1 mapping of said region.
> 
> Based on a patch from Michel Thierry.
> 
> v2 by Jani:
> - use intel_uncore_read/intel_uncore_write
> - remove trailing blank line
> 
> v3: s/drm_info/drm_dbg for info which in non-pertinent for the user
> 
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_region_lmem.c | 37 +++++++++++++++++++++
>   drivers/gpu/drm/i915/gt/intel_region_lmem.h |  2 ++
>   drivers/gpu/drm/i915/i915_reg.h             |  3 ++
>   drivers/gpu/drm/i915/intel_memory_region.c  | 11 +++++-
>   4 files changed, 52 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 28a1d5e1fb92..bdd38efe0811 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -136,3 +136,40 @@ intel_setup_fake_lmem(struct drm_i915_private *i915)
>   
>   	return mem;
>   }
> +
> +static struct intel_memory_region *
> +setup_lmem(struct drm_i915_private *i915)
> +{ > +	struct pci_dev *pdev = i915->drm.pdev;
> +	struct intel_memory_region *mem;
> +	resource_size_t io_start;
> +	resource_size_t size;
> +
> +	/* Enables Local Memory functionality in GAM */
> +	intel_uncore_write(&i915->uncore, GEN12_LMEM_CFG_ADDR,
> +			   intel_uncore_read(&i915->uncore, GEN12_LMEM_CFG_ADDR) | LMEM_ENABLE);

You could use intel_uncore_rmw as well for some minimal improvement in 
readability. Just a passing by observation, no need to respin if it 
doesn't fit the schedules.

> +
> +	io_start = pci_resource_start(pdev, 2);
> +	size = pci_resource_len(pdev, 2);
> +
> +	mem = intel_memory_region_create(i915,
> +					 0,
> +					 size,
> +					 I915_GTT_PAGE_SIZE_4K,
> +					 io_start,
> +					 &intel_region_lmem_ops);
> +	if (!IS_ERR(mem)) {
> +		drm_dbg(&i915->drm, "Intel graphics LMEM: %pR\n", &mem->region);
> +		drm_dbg(&i915->drm, "Intel graphics LMEM IO start: %pa\n",
> +			 &mem->io_start);
> +		drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n", &size);
> +	}
> +
> +	return mem;
> +}
> +
> +struct intel_memory_region *
> +i915_gem_setup_lmem(struct drm_i915_private *i915)
> +{
> +	return setup_lmem(i915);
> +}

Was it ever discussed if there was an easy way (and if it makes sense 
actually) to move this from GEM to GT (in name and input parameter?

Regards,

Tvrtko

> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.h b/drivers/gpu/drm/i915/gt/intel_region_lmem.h
> index 8ea43e538dab..b32222bd493c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.h
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.h
> @@ -8,6 +8,8 @@
>   
>   struct drm_i915_private;
>   
> +struct intel_memory_region *i915_gem_setup_lmem(struct drm_i915_private *i915);
> +
>   struct intel_memory_region *
>   intel_setup_fake_lmem(struct drm_i915_private *i915);
>   
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e7e41a3c467e..28001b5a3cb5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -12111,6 +12111,9 @@ enum skl_power_gate {
>   
>   #define GEN12_GLOBAL_MOCS(i)	_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
>   
> +#define GEN12_LMEM_CFG_ADDR		_MMIO(0xcf58)
> +#define   LMEM_ENABLE			(1 << 31)
> +
>   /* gamt regs */
>   #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
>   #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
> index 1bfcdd89b241..9ce4a81c48b1 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -259,7 +259,16 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
>   			mem = i915_gem_stolen_setup(i915);
>   			break;
>   		case INTEL_MEMORY_LOCAL:
> -			mem = intel_setup_fake_lmem(i915);
> +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> +			if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
> +				if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
> +				    i915->params.fake_lmem_start)
> +					mem = intel_setup_fake_lmem(i915);
> +			}
> +#endif
> +
> +			if (IS_ERR(mem))
> +				mem = i915_gem_setup_lmem(i915);
>   			break;
>   		}
>   
> 
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: setup the LMEM region

[Patchwork]

== Series Details ==

Series: series starting with [1/7] drm/i915: setup the LMEM region
URL   : https://patchwork.freedesktop.org/series/86294/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
684488fc1838 drm/i915: setup the LMEM region
-:57: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#57: FILE: drivers/gpu/drm/i915/gt/intel_region_lmem.c:164:
+		drm_dbg(&i915->drm, "Intel graphics LMEM IO start: %pa\n",
+			 &mem->io_start);

total: 0 errors, 0 warnings, 1 checks, 74 lines checked
bebbd470cc5f drm/i915: reserve stolen for LMEM region
47e9cf146fbe drm/i915: introduce mem->reserved
-:75: WARNING:LINE_SPACING: Missing a blank line after declarations
#75: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:167:
+	resource_size_t avail = resource_size(&mem->region);
+	I915_RND_STATE(prng);

total: 0 errors, 1 warnings, 0 checks, 123 lines checked
f8db1a26bbd9 drm/i915/dg1: Reserve first 1MB of local memory
-:48: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#48: FILE: drivers/gpu/drm/i915/gt/intel_region_lmem.c:158:
+{
+

total: 0 errors, 0 warnings, 1 checks, 65 lines checked
41cf705692f0 drm/i915: allocate context from LMEM
85f01e9f4886 drm/i915: move engine scratch to LMEM
bf5fa03c9cc5 drm/i915: allocate cmd ring in lmem


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: setup the LMEM region

[Patchwork]

== Series Details ==

Series: series starting with [1/7] drm/i915: setup the LMEM region
URL   : https://patchwork.freedesktop.org/series/86294/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1327:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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Re: [Intel-gfx] [PATCH 2/7] drm/i915: reserve stolen for LMEM region

[Chris Wilson]

Quoting Matthew Auld (2021-01-26 09:46:07)
> @@ -162,7 +165,8 @@ setup_lmem(struct drm_i915_private *i915)
>                 drm_dbg(&i915->drm, "Intel graphics LMEM: %pR\n", &mem->region);
>                 drm_dbg(&i915->drm, "Intel graphics LMEM IO start: %pa\n",
>                          &mem->io_start);
> -               drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n", &size);
> +               drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n",
> +                        &lmem_size);

LMEM is Intel jargon. Intel is more or less redundant here as we have
the device and driver already in the message.

drm_info(&i915->drm, "Local memory available: %pa\n", &lmem_size);
-Chris
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Re: [Intel-gfx] [PATCH 1/7] drm/i915: setup the LMEM region

[Matthew Auld]

On 26/01/2021 10:09, Tvrtko Ursulin wrote:
> 
> On 26/01/2021 09:46, Matthew Auld wrote:
>> Hook up the LMEM region. Addresses will start from zero, and for CPU
>> access we get LMEM_BAR which is just a 1:1 mapping of said region.
>>
>> Based on a patch from Michel Thierry.
>>
>> v2 by Jani:
>> - use intel_uncore_read/intel_uncore_write
>> - remove trailing blank line
>>
>> v3: s/drm_info/drm_dbg for info which in non-pertinent for the user
>>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_region_lmem.c | 37 +++++++++++++++++++++
>>   drivers/gpu/drm/i915/gt/intel_region_lmem.h |  2 ++
>>   drivers/gpu/drm/i915/i915_reg.h             |  3 ++
>>   drivers/gpu/drm/i915/intel_memory_region.c  | 11 +++++-
>>   4 files changed, 52 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
>> b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> index 28a1d5e1fb92..bdd38efe0811 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> @@ -136,3 +136,40 @@ intel_setup_fake_lmem(struct drm_i915_private *i915)
>>       return mem;
>>   }
>> +
>> +static struct intel_memory_region *
>> +setup_lmem(struct drm_i915_private *i915)
>> +{ > +    struct pci_dev *pdev = i915->drm.pdev;
>> +    struct intel_memory_region *mem;
>> +    resource_size_t io_start;
>> +    resource_size_t size;
>> +
>> +    /* Enables Local Memory functionality in GAM */
>> +    intel_uncore_write(&i915->uncore, GEN12_LMEM_CFG_ADDR,
>> +               intel_uncore_read(&i915->uncore, GEN12_LMEM_CFG_ADDR) 
>> | LMEM_ENABLE);
> 
> You could use intel_uncore_rmw as well for some minimal improvement in 
> readability. Just a passing by observation, no need to respin if it 
> doesn't fit the schedules.

On second thought, I think we can just drop this since it should be 
default enabled nowadays anyway.

> 
>> +
>> +    io_start = pci_resource_start(pdev, 2);
>> +    size = pci_resource_len(pdev, 2);
>> +
>> +    mem = intel_memory_region_create(i915,
>> +                     0,
>> +                     size,
>> +                     I915_GTT_PAGE_SIZE_4K,
>> +                     io_start,
>> +                     &intel_region_lmem_ops);
>> +    if (!IS_ERR(mem)) {
>> +        drm_dbg(&i915->drm, "Intel graphics LMEM: %pR\n", &mem->region);
>> +        drm_dbg(&i915->drm, "Intel graphics LMEM IO start: %pa\n",
>> +             &mem->io_start);
>> +        drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n", &size);
>> +    }
>> +
>> +    return mem;
>> +}
>> +
>> +struct intel_memory_region *
>> +i915_gem_setup_lmem(struct drm_i915_private *i915)
>> +{
>> +    return setup_lmem(i915);
>> +}
> 
> Was it ever discussed if there was an easy way (and if it makes sense 
> actually) to move this from GEM to GT (in name and input parameter?

Yeah, makes sense, especially since this is now in gt/

So just:
intel_gt_setup_lmem(gt)

?

> 
> Regards,
> 
> Tvrtko
> 
>> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.h 
>> b/drivers/gpu/drm/i915/gt/intel_region_lmem.h
>> index 8ea43e538dab..b32222bd493c 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.h
>> @@ -8,6 +8,8 @@
>>   struct drm_i915_private;
>> +struct intel_memory_region *i915_gem_setup_lmem(struct 
>> drm_i915_private *i915);
>> +
>>   struct intel_memory_region *
>>   intel_setup_fake_lmem(struct drm_i915_private *i915);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index e7e41a3c467e..28001b5a3cb5 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -12111,6 +12111,9 @@ enum skl_power_gate {
>>   #define GEN12_GLOBAL_MOCS(i)    _MMIO(0x4000 + (i) * 4) /* Global 
>> MOCS regs */
>> +#define GEN12_LMEM_CFG_ADDR        _MMIO(0xcf58)
>> +#define   LMEM_ENABLE            (1 << 31)
>> +
>>   /* gamt regs */
>>   #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
>>   #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* 
>> max/min for LRA1/2 */
>> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c 
>> b/drivers/gpu/drm/i915/intel_memory_region.c
>> index 1bfcdd89b241..9ce4a81c48b1 100644
>> --- a/drivers/gpu/drm/i915/intel_memory_region.c
>> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
>> @@ -259,7 +259,16 @@ int intel_memory_regions_hw_probe(struct 
>> drm_i915_private *i915)
>>               mem = i915_gem_stolen_setup(i915);
>>               break;
>>           case INTEL_MEMORY_LOCAL:
>> -            mem = intel_setup_fake_lmem(i915);
>> +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>> +            if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
>> +                if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
>> +                    i915->params.fake_lmem_start)
>> +                    mem = intel_setup_fake_lmem(i915);
>> +            }
>> +#endif
>> +
>> +            if (IS_ERR(mem))
>> +                mem = i915_gem_setup_lmem(i915);
>>               break;
>>           }
>>
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Re: [Intel-gfx] [PATCH 2/7] drm/i915: reserve stolen for LMEM region

[Matthew Auld]

On 26/01/2021 10:27, Chris Wilson wrote:
> Quoting Matthew Auld (2021-01-26 09:46:07)
>> @@ -162,7 +165,8 @@ setup_lmem(struct drm_i915_private *i915)
>>                  drm_dbg(&i915->drm, "Intel graphics LMEM: %pR\n", &mem->region);
>>                  drm_dbg(&i915->drm, "Intel graphics LMEM IO start: %pa\n",
>>                           &mem->io_start);
>> -               drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n", &size);
>> +               drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n",
>> +                        &lmem_size);
> 
> LMEM is Intel jargon. Intel is more or less redundant here as we have
> the device and driver already in the message.
> 
> drm_info(&i915->drm, "Local memory available: %pa\n", &lmem_size);

Ok, makes sense.

> -Chris
> 
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Re: [Intel-gfx] [PATCH 1/7] drm/i915: setup the LMEM region

[Chris Wilson]

Quoting Matthew Auld (2021-01-26 10:38:09)
> On 26/01/2021 10:09, Tvrtko Ursulin wrote:
> > 
> > On 26/01/2021 09:46, Matthew Auld wrote:
> >> +struct intel_memory_region *
> >> +i915_gem_setup_lmem(struct drm_i915_private *i915)
> >> +{
> >> +    return setup_lmem(i915);
> >> +}
> > 
> > Was it ever discussed if there was an easy way (and if it makes sense 
> > actually) to move this from GEM to GT (in name and input parameter?
> 
> Yeah, makes sense, especially since this is now in gt/
> 
> So just:
> intel_gt_setup_lmem(gt)

The implication is that the memory region should be added during the GT
probe, so some jiggling around required. (So as each GT comes online,
we add it's available memory to the pool.)

Shouldn't be too bad as conceptually it's just moving the memprobe down
a couple of lines in i915_driver_hw_probe :)
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: setup the LMEM region

[Patchwork]

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== Series Details ==

Series: series starting with [1/7] drm/i915: setup the LMEM region
URL   : https://patchwork.freedesktop.org/series/86294/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9682 -> Patchwork_19502
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_19502 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19502, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19502/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19502:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7500u:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19502/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html

  
Known issues
------------

  Here are the changes found in Patchwork_19502 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_flink_basic@bad-flink:
    - fi-tgl-y:           [PASS][3] -> [DMESG-WARN][4] ([i915#402])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/fi-tgl-y/igt@gem_flink_basic@bad-flink.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19502/fi-tgl-y/igt@gem_flink_basic@bad-flink.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-n3050:       [PASS][5] -> [INCOMPLETE][6] ([i915#2940])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19502/fi-bsw-n3050/igt@i915_selftest@live@execlists.html

  * igt@runner@aborted:
    - fi-bsw-n3050:       NOTRUN -> [FAIL][7] ([i915#1436] / [i915#1602])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19502/fi-bsw-n3050/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic:
    - fi-tgl-y:           [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/fi-tgl-y/igt@gem_ctx_create@basic.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19502/fi-tgl-y/igt@gem_ctx_create@basic.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-kbl-guc:         [SKIP][10] ([fdo#109271]) -> [FAIL][11] ([i915#704])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9682/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19502/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704


Participating hosts (40 -> 36)
------------------------------

  Missing    (4): fi-ctg-p8600 fi-jsl-1 fi-ilk-m540 fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_9682 -> Patchwork_19502

  CI-20190529: 20190529
  CI_DRM_9682: 35ee6d505b478462c04952da1a4fbc03991af114 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5971: abef2b7d6ff30f3b948b3e5d39653debb73083f3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19502: bf5fa03c9cc58969a5b0d7f9b8f2d1a4a332bd04 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

bf5fa03c9cc5 drm/i915: allocate cmd ring in lmem
85f01e9f4886 drm/i915: move engine scratch to LMEM
41cf705692f0 drm/i915: allocate context from LMEM
f8db1a26bbd9 drm/i915/dg1: Reserve first 1MB of local memory
47e9cf146fbe drm/i915: introduce mem->reserved
bebbd470cc5f drm/i915: reserve stolen for LMEM region
684488fc1838 drm/i915: setup the LMEM region

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19502/index.html

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