* [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object
@ 2021-02-03 9:01 Chris Wilson
2021-02-03 9:01 ` [Intel-gfx] [CI 2/8] drm/i915/selftests: Use a coherent map to setup scratch batch buffers Chris Wilson
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Chris Wilson @ 2021-02-03 9:01 UTC (permalink / raw)
To: intel-gfx
Set the cache coherency and status using the set-coherency helper.
Otherwise, we forget to mark the new pages as cache dirty.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index aacf4856ccb4..f6329e462cfc 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -171,10 +171,8 @@ huge_pages_object(struct drm_i915_private *i915,
i915_gem_object_init(obj, &huge_page_ops, &lock_class);
i915_gem_object_set_volatile(obj);
-
- obj->write_domain = I915_GEM_DOMAIN_CPU;
- obj->read_domains = I915_GEM_DOMAIN_CPU;
- obj->cache_level = I915_CACHE_NONE;
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
+ __start_cpu_write(obj);
obj->mm.page_mask = page_mask;
@@ -324,10 +322,8 @@ fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single)
i915_gem_object_init(obj, &fake_ops, &lock_class);
i915_gem_object_set_volatile(obj);
-
- obj->write_domain = I915_GEM_DOMAIN_CPU;
- obj->read_domains = I915_GEM_DOMAIN_CPU;
- obj->cache_level = I915_CACHE_NONE;
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
+ __start_cpu_write(obj);
return obj;
}
@@ -994,7 +990,7 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val)
u32 *ptr = kmap_atomic(i915_gem_object_get_page(obj, n));
if (needs_flush & CLFLUSH_BEFORE)
- drm_clflush_virt_range(ptr, PAGE_SIZE);
+ drm_clflush_virt_range(&ptr[dword], sizeof(val));
if (ptr[dword] != val) {
pr_err("n=%lu ptr[%u]=%u, val=%u\n",
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [CI 2/8] drm/i915/selftests: Use a coherent map to setup scratch batch buffers
2021-02-03 9:01 [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object Chris Wilson
@ 2021-02-03 9:01 ` Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 3/8] drm/i915/selftests: Replace the unbounded set-domain with an explicit wait Chris Wilson
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2021-02-03 9:01 UTC (permalink / raw)
To: intel-gfx
Instead of manipulating the object's cache domain, just use the device
coherent map to write the batch buffer.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index d3f87dc4eda3..e02299fffe60 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1622,7 +1622,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
if (err)
goto out_vm;
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
goto out;
@@ -1658,7 +1658,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
if (err)
goto out_vm;
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
goto out;
@@ -1707,15 +1707,17 @@ static int read_from_scratch(struct i915_gem_context *ctx,
i915_vma_unpin(vma);
+ i915_request_get(rq);
i915_request_add(rq);
- i915_gem_object_lock(obj, NULL);
- err = i915_gem_object_set_to_cpu_domain(obj, false);
- i915_gem_object_unlock(obj);
- if (err)
+ if (i915_request_wait(rq, 0, HZ / 5) < 0) {
+ i915_request_put(rq);
+ err = -ETIME;
goto out_vm;
+ }
+ i915_request_put(rq);
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
goto out_vm;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [CI 3/8] drm/i915/selftests: Replace the unbounded set-domain with an explicit wait
2021-02-03 9:01 [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object Chris Wilson
2021-02-03 9:01 ` [Intel-gfx] [CI 2/8] drm/i915/selftests: Use a coherent map to setup scratch batch buffers Chris Wilson
@ 2021-02-03 9:02 ` Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 4/8] drm/i915/selftests: Remove redundant set-to-gtt-domain Chris Wilson
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2021-02-03 9:02 UTC (permalink / raw)
To: intel-gfx
After running client_blt, we flush the object by changing its domain.
This causes us to wait forever instead of an bounded wait suitable for
the selftest timeout. So do an explicit wait with a suitable timeout --
which in turn means we have to limit the size of the object/blit to run
within reason.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
.../i915/gem/selftests/i915_gem_client_blt.c | 26 ++++++++++++++-----
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 6a674a7994df..175581724d44 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -23,12 +23,19 @@ static int __igt_client_fill(struct intel_engine_cs *engine)
I915_RND_STATE(prng);
IGT_TIMEOUT(end);
u32 *vaddr;
+ u64 limit;
int err = 0;
+ /* Try to keep the blits within the timeout */
+ limit = min_t(u64, ce->vm->total >> 4,
+ jiffies_to_msecs(i915_selftest.timeout_jiffies) * SZ_2M);
+ if (!limit)
+ limit = SZ_4K;
+
intel_engine_pm_get(engine);
do {
const u32 max_block_size = S16_MAX * PAGE_SIZE;
- u32 sz = min_t(u64, ce->vm->total >> 4, prandom_u32_state(&prng));
+ u32 sz = min_t(u64, limit, prandom_u32_state(&prng));
u32 phys_sz = sz % (max_block_size + 1);
u32 val = prandom_u32_state(&prng);
u32 i;
@@ -73,13 +80,20 @@ static int __igt_client_fill(struct intel_engine_cs *engine)
if (err)
goto err_unpin;
- i915_gem_object_lock(obj, NULL);
- err = i915_gem_object_set_to_cpu_domain(obj, false);
- i915_gem_object_unlock(obj);
- if (err)
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ 2 * i915_selftest.timeout_jiffies);
+ if (err) {
+ pr_err("%s fill %zxB timed out\n",
+ engine->name, obj->base.size);
goto err_unpin;
+ }
- for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); ++i) {
+ for (i = 0;
+ i < huge_gem_object_phys_size(obj) / sizeof(u32);
+ i += 17) {
+ if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
+ clflush(&vaddr[i]);
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [CI 4/8] drm/i915/selftests: Remove redundant set-to-gtt-domain
2021-02-03 9:01 [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object Chris Wilson
2021-02-03 9:01 ` [Intel-gfx] [CI 2/8] drm/i915/selftests: Use a coherent map to setup scratch batch buffers Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 3/8] drm/i915/selftests: Replace the unbounded set-domain with an explicit wait Chris Wilson
@ 2021-02-03 9:02 ` Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 5/8] drm/i915/selftests: Replace unbound set-domain waits with explicit timeouts Chris Wilson
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2021-02-03 9:02 UTC (permalink / raw)
To: intel-gfx
Since the vma's backing store is flushed upon first creation, remove the
manual calls to set-to-gtt-domain.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
.../gpu/drm/i915/gem/selftests/i915_gem_mman.c | 16 ----------------
drivers/gpu/drm/i915/selftests/i915_vma.c | 6 ------
2 files changed, 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index d429c7643ff2..39293d98f34d 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -104,14 +104,6 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj,
GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);
- i915_gem_object_lock(obj, NULL);
- err = i915_gem_object_set_to_gtt_domain(obj, true);
- i915_gem_object_unlock(obj);
- if (err) {
- pr_err("Failed to flush to GTT write domain; err=%d\n", err);
- return err;
- }
-
page = i915_prandom_u32_max_state(npages, prng);
view = compute_partial_view(obj, page, MIN_CHUNK_PAGES);
@@ -189,14 +181,6 @@ static int check_partial_mappings(struct drm_i915_gem_object *obj,
GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);
- i915_gem_object_lock(obj, NULL);
- err = i915_gem_object_set_to_gtt_domain(obj, true);
- i915_gem_object_unlock(obj);
- if (err) {
- pr_err("Failed to flush to GTT write domain; err=%d\n", err);
- return err;
- }
-
for_each_prime_number_from(page, 1, npages) {
struct i915_ggtt_view view =
compute_partial_view(obj, page, MIN_CHUNK_PAGES);
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 1b6125e4c1ac..065a9d82ad5c 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -892,12 +892,6 @@ static int igt_vma_remapped_gtt(void *arg)
unsigned int x, y;
int err;
- i915_gem_object_lock(obj, NULL);
- err = i915_gem_object_set_to_gtt_domain(obj, true);
- i915_gem_object_unlock(obj);
- if (err)
- goto out;
-
vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [CI 5/8] drm/i915/selftests: Replace unbound set-domain waits with explicit timeouts
2021-02-03 9:01 [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object Chris Wilson
` (2 preceding siblings ...)
2021-02-03 9:02 ` [Intel-gfx] [CI 4/8] drm/i915/selftests: Remove redundant set-to-gtt-domain Chris Wilson
@ 2021-02-03 9:02 ` Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 6/8] drm/i915/selftests: Replace an unbounded set-domain wait with a timeout Chris Wilson
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2021-02-03 9:02 UTC (permalink / raw)
To: intel-gfx
Let's prefer to use explicit request tracking and bounded timeouts in
our selftests.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
.../gpu/drm/i915/gt/selftest_workarounds.c | 106 +++++++-----------
1 file changed, 40 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index af33a720dbf8..e5ee6136c81f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -93,56 +93,27 @@ reference_lists_fini(struct intel_gt *gt, struct wa_lists *lists)
intel_wa_list_free(&lists->gt_wa_list);
}
-static struct drm_i915_gem_object *
-read_nonprivs(struct intel_context *ce)
+static struct i915_request *
+read_nonprivs(struct intel_context *ce, struct i915_vma *result)
{
struct intel_engine_cs *engine = ce->engine;
const u32 base = engine->mmio_base;
- struct drm_i915_gem_object *result;
struct i915_request *rq;
- struct i915_vma *vma;
u32 srm, *cs;
int err;
int i;
- result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
- if (IS_ERR(result))
- return result;
-
- i915_gem_object_set_cache_coherency(result, I915_CACHE_LLC);
-
- cs = i915_gem_object_pin_map(result, I915_MAP_WB);
- if (IS_ERR(cs)) {
- err = PTR_ERR(cs);
- goto err_obj;
- }
- memset(cs, 0xc5, PAGE_SIZE);
- i915_gem_object_flush_map(result);
- i915_gem_object_unpin_map(result);
-
- vma = i915_vma_instance(result, &engine->gt->ggtt->vm, NULL);
- if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- goto err_obj;
- }
-
- err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
- if (err)
- goto err_obj;
-
rq = intel_context_create_request(ce);
- if (IS_ERR(rq)) {
- err = PTR_ERR(rq);
- goto err_pin;
- }
+ if (IS_ERR(rq))
+ return rq;
- i915_vma_lock(vma);
- err = i915_request_await_object(rq, vma->obj, true);
+ i915_vma_lock(result);
+ err = i915_request_await_object(rq, result->obj, true);
if (err == 0)
- err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
+ err = i915_vma_move_to_active(result, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(result);
if (err)
- goto err_req;
+ goto err_rq;
srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
if (INTEL_GEN(engine->i915) >= 8)
@@ -151,28 +122,24 @@ read_nonprivs(struct intel_context *ce)
cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
- goto err_req;
+ goto err_rq;
}
for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
*cs++ = srm;
*cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));
- *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
+ *cs++ = i915_ggtt_offset(result) + sizeof(u32) * i;
*cs++ = 0;
}
intel_ring_advance(rq, cs);
+ i915_request_get(rq);
i915_request_add(rq);
- i915_vma_unpin(vma);
- return result;
+ return rq;
-err_req:
+err_rq:
i915_request_add(rq);
-err_pin:
- i915_vma_unpin(vma);
-err_obj:
- i915_gem_object_put(result);
return ERR_PTR(err);
}
@@ -203,32 +170,36 @@ print_results(const struct intel_engine_cs *engine, const u32 *results)
static int check_whitelist(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
- struct drm_i915_gem_object *results;
- struct intel_wedge_me wedge;
+ struct i915_vma *result;
+ struct i915_request *rq;
+ int err = 0;
u32 *vaddr;
- int err;
int i;
- results = read_nonprivs(ce);
- if (IS_ERR(results))
- return PTR_ERR(results);
+ result = __vm_create_scratch_for_read(&engine->gt->ggtt->vm, PAGE_SIZE);
+ if (IS_ERR(result))
+ return PTR_ERR(result);
- err = 0;
- i915_gem_object_lock(results, NULL);
- intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! */
- err = i915_gem_object_set_to_cpu_domain(results, false);
- i915_gem_object_unlock(results);
- if (intel_gt_is_wedged(engine->gt))
- err = -EIO;
- if (err)
- goto out_put;
-
- vaddr = i915_gem_object_pin_map(results, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map(result->obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
goto out_put;
}
+ memset(vaddr, 0xc5, PAGE_SIZE);
+ i915_gem_object_flush_map(result->obj);
+
+ rq = read_nonprivs(ce, result);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_map;
+ }
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0) {
+ err = -EIO;
+ goto out_rq;
+ }
+
for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
u32 expected = get_whitelist_reg(engine, i);
u32 actual = vaddr[i];
@@ -243,9 +214,12 @@ static int check_whitelist(struct intel_context *ce)
}
}
- i915_gem_object_unpin_map(results);
+out_rq:
+ i915_request_put(rq);
+out_map:
+ i915_gem_object_unpin_map(result->obj);
out_put:
- i915_gem_object_put(results);
+ i915_vma_put(result);
return err;
}
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [CI 6/8] drm/i915/selftests: Replace an unbounded set-domain wait with a timeout
2021-02-03 9:01 [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object Chris Wilson
` (3 preceding siblings ...)
2021-02-03 9:02 ` [Intel-gfx] [CI 5/8] drm/i915/selftests: Replace unbound set-domain waits with explicit timeouts Chris Wilson
@ 2021-02-03 9:02 ` Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 7/8] drm/i915/selftests: Remove redundant set-to-gtt-domain before batch submission Chris Wilson
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2021-02-03 9:02 UTC (permalink / raw)
To: intel-gfx
After the memory-region test completes, it flushes the test by calling
set-to-cpu-domain. Use the igt_flush_test as it includes a timeout,
recovery and reports and error for miscreant tests.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 64348528e1d5..3e583139f767 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -738,11 +738,10 @@ static int igt_lmem_write_cpu(void *arg)
if (err)
goto out_unpin;
- i915_gem_object_lock(obj, NULL);
- err = i915_gem_object_set_to_wc_domain(obj, true);
- i915_gem_object_unlock(obj);
- if (err)
+ if (igt_flush_test(engine->i915)) {
+ err = -EIO;
goto out_unpin;
+ }
count = ARRAY_SIZE(bytes);
order = i915_random_order(count * count, &prng);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [CI 7/8] drm/i915/selftests: Remove redundant set-to-gtt-domain before batch submission
2021-02-03 9:01 [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object Chris Wilson
` (4 preceding siblings ...)
2021-02-03 9:02 ` [Intel-gfx] [CI 6/8] drm/i915/selftests: Replace an unbounded set-domain wait with a timeout Chris Wilson
@ 2021-02-03 9:02 ` Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 8/8] drm/i915/gem: Manage all set-domain waits explicitly Chris Wilson
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2021-02-03 9:02 UTC (permalink / raw)
To: intel-gfx
In construction the rpcs_query batch we know that it is device coherent
and ready for execution, the set-to-gtt-domain here is redudant.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index e02299fffe60..df949320f2b5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -954,8 +954,6 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
err = i915_gem_object_lock(obj, &ww);
if (!err)
err = i915_gem_object_lock(rpcs, &ww);
- if (!err)
- err = i915_gem_object_set_to_gtt_domain(obj, false);
if (!err)
err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER);
if (err)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [CI 8/8] drm/i915/gem: Manage all set-domain waits explicitly
2021-02-03 9:01 [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object Chris Wilson
` (5 preceding siblings ...)
2021-02-03 9:02 ` [Intel-gfx] [CI 7/8] drm/i915/selftests: Remove redundant set-to-gtt-domain before batch submission Chris Wilson
@ 2021-02-03 9:02 ` Chris Wilson
2021-02-03 10:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/8] drm/i915/selftests: Set cache status for huge_gem_object Patchwork
2021-02-03 13:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2021-02-03 9:02 UTC (permalink / raw)
To: intel-gfx
Only perform the domain transition under the object lock, and push the
required waits to outside the lock.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 9 +-
drivers/gpu/drm/i915/gem/i915_gem_clflush.h | 2 -
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 157 +++++-------------
drivers/gpu/drm/i915/gem/i915_gem_object.h | 12 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 6 +
.../gpu/drm/i915/gem/selftests/huge_pages.c | 8 -
.../i915/gem/selftests/i915_gem_coherency.c | 30 +++-
.../drm/i915/gem/selftests/i915_gem_phys.c | 8 +-
.../drm/i915/gem/selftests/igt_gem_utils.c | 3 +
drivers/gpu/drm/i915/i915_gem.c | 12 +-
11 files changed, 89 insertions(+), 162 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
index bc0223716906..a28f8c912a3e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
@@ -57,8 +57,6 @@ static struct clflush *clflush_work_create(struct drm_i915_gem_object *obj)
{
struct clflush *clflush;
- GEM_BUG_ON(!obj->cache_dirty);
-
clflush = kmalloc(sizeof(*clflush), GFP_KERNEL);
if (!clflush)
return NULL;
@@ -102,13 +100,10 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
trace_i915_gem_object_clflush(obj);
- clflush = NULL;
- if (!(flags & I915_CLFLUSH_SYNC))
- clflush = clflush_work_create(obj);
+ clflush = clflush_work_create(obj);
if (clflush) {
i915_sw_fence_await_reservation(&clflush->base.chain,
- obj->base.resv, NULL, true,
- i915_fence_timeout(to_i915(obj->base.dev)),
+ obj->base.resv, NULL, true, 0,
I915_FENCE_GFP);
dma_resv_add_excl_fence(obj->base.resv, &clflush->base.dma);
dma_fence_work_commit(&clflush->base);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.h b/drivers/gpu/drm/i915/gem/i915_gem_clflush.h
index e6c382973129..4cd5787d1507 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.h
@@ -9,12 +9,10 @@
#include <linux/types.h>
-struct drm_i915_private;
struct drm_i915_gem_object;
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
unsigned int flags);
#define I915_CLFLUSH_FORCE BIT(0)
-#define I915_CLFLUSH_SYNC BIT(1)
#endif /* __I915_GEM_CLFLUSH_H__ */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 5cc8a0b2387f..d804b0003e0d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -133,7 +133,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_dire
if (err)
goto out;
- err = i915_gem_object_set_to_cpu_domain(obj, write);
+ i915_gem_object_set_to_cpu_domain(obj, write);
i915_gem_object_unlock(obj);
out:
@@ -154,7 +154,7 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direct
if (err)
goto out;
- err = i915_gem_object_set_to_gtt_domain(obj, false);
+ i915_gem_object_set_to_gtt_domain(obj, false);
i915_gem_object_unlock(obj);
out:
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 36f54cedaaeb..0478b069c202 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -49,7 +49,7 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
break;
case I915_GEM_DOMAIN_CPU:
- i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
+ i915_gem_clflush_object(obj, 0);
break;
case I915_GEM_DOMAIN_RENDER:
@@ -97,34 +97,13 @@ void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj)
* This function returns when the move is complete, including waiting on
* flushes to occur.
*/
-int
+void
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
{
- int ret;
-
assert_object_held(obj);
- ret = i915_gem_object_wait(obj,
- I915_WAIT_INTERRUPTIBLE |
- (write ? I915_WAIT_ALL : 0),
- MAX_SCHEDULE_TIMEOUT);
- if (ret)
- return ret;
-
if (obj->write_domain == I915_GEM_DOMAIN_WC)
- return 0;
-
- /* Flush and acquire obj->pages so that we are coherent through
- * direct access in memory with previous cached writes through
- * shmemfs and that our cache domain tracking remains valid.
- * For example, if the obj->filp was moved to swap without us
- * being notified and releasing the pages, we would mistakenly
- * continue to assume that the obj remained out of the CPU cached
- * domain.
- */
- ret = i915_gem_object_pin_pages(obj);
- if (ret)
- return ret;
+ return;
flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
@@ -145,9 +124,6 @@ i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
obj->write_domain = I915_GEM_DOMAIN_WC;
obj->mm.dirty = true;
}
-
- i915_gem_object_unpin_pages(obj);
- return 0;
}
/**
@@ -158,34 +134,13 @@ i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
* This function returns when the move is complete, including waiting on
* flushes to occur.
*/
-int
+void
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
{
- int ret;
-
assert_object_held(obj);
- ret = i915_gem_object_wait(obj,
- I915_WAIT_INTERRUPTIBLE |
- (write ? I915_WAIT_ALL : 0),
- MAX_SCHEDULE_TIMEOUT);
- if (ret)
- return ret;
-
if (obj->write_domain == I915_GEM_DOMAIN_GTT)
- return 0;
-
- /* Flush and acquire obj->pages so that we are coherent through
- * direct access in memory with previous cached writes through
- * shmemfs and that our cache domain tracking remains valid.
- * For example, if the obj->filp was moved to swap without us
- * being notified and releasing the pages, we would mistakenly
- * continue to assume that the obj remained out of the CPU cached
- * domain.
- */
- ret = i915_gem_object_pin_pages(obj);
- if (ret)
- return ret;
+ return;
flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
@@ -214,9 +169,6 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
i915_vma_set_ggtt_write(vma);
spin_unlock(&obj->vma.lock);
}
-
- i915_gem_object_unpin_pages(obj);
- return 0;
}
/**
@@ -442,25 +394,23 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
* This function returns when the move is complete, including waiting on
* flushes to occur.
*/
-int
+void
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
{
- int ret;
-
assert_object_held(obj);
- ret = i915_gem_object_wait(obj,
- I915_WAIT_INTERRUPTIBLE |
- (write ? I915_WAIT_ALL : 0),
- MAX_SCHEDULE_TIMEOUT);
- if (ret)
- return ret;
-
flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
/* Flush the CPU cache if it's still invalid. */
if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
- i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
+ /*
+ * While we track when we write though the CPU cache
+ * (with obj->cache_dirty), this is only a guide as we do
+ * not know when the CPU may have speculatively populated
+ * the cache. We have to invalidate such speculative cachelines
+ * prior to reading writes by the GPU.
+ */
+ i915_gem_clflush_object(obj, 0);
obj->read_domains |= I915_GEM_DOMAIN_CPU;
}
@@ -474,8 +424,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
*/
if (write)
__start_cpu_write(obj);
-
- return 0;
}
/**
@@ -513,19 +461,6 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
if (!obj)
return -ENOENT;
- /*
- * Try to flush the object off the GPU without holding the lock.
- * We will repeat the flush holding the lock in the normal manner
- * to catch cases where we are gazumped.
- */
- err = i915_gem_object_wait(obj,
- I915_WAIT_INTERRUPTIBLE |
- I915_WAIT_PRIORITY |
- (write_domain ? I915_WAIT_ALL : 0),
- MAX_SCHEDULE_TIMEOUT);
- if (err)
- goto out;
-
/*
* Proxy objects do not control access to the backing storage, ergo
* they cannot be used as a means to manipulate the cache domain
@@ -561,21 +496,27 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
* without having to further check the requested write_domain.
*/
if (READ_ONCE(obj->write_domain) == read_domains)
- goto out_unpin;
+ goto out_wait;
err = i915_gem_object_lock_interruptible(obj, NULL);
if (err)
goto out_unpin;
if (read_domains & I915_GEM_DOMAIN_WC)
- err = i915_gem_object_set_to_wc_domain(obj, write_domain);
+ i915_gem_object_set_to_wc_domain(obj, write_domain);
else if (read_domains & I915_GEM_DOMAIN_GTT)
- err = i915_gem_object_set_to_gtt_domain(obj, write_domain);
+ i915_gem_object_set_to_gtt_domain(obj, write_domain);
else
- err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
+ i915_gem_object_set_to_cpu_domain(obj, write_domain);
i915_gem_object_unlock(obj);
+out_wait:
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_PRIORITY |
+ (write_domain ? I915_WAIT_ALL : 0),
+ MAX_SCHEDULE_TIMEOUT);
if (write_domain)
i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
@@ -602,26 +543,21 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj,
assert_object_held(obj);
- ret = i915_gem_object_wait(obj,
- I915_WAIT_INTERRUPTIBLE,
- MAX_SCHEDULE_TIMEOUT);
- if (ret)
- return ret;
-
ret = i915_gem_object_pin_pages(obj);
if (ret)
return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ ||
- !static_cpu_has(X86_FEATURE_CLFLUSH)) {
- ret = i915_gem_object_set_to_cpu_domain(obj, false);
- if (ret)
- goto err_unpin;
- else
- goto out;
- }
+ !static_cpu_has(X86_FEATURE_CLFLUSH))
+ i915_gem_object_set_to_cpu_domain(obj, false);
+ else
+ flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
- flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ goto err_unpin;
/* If we're not in the cpu read domain, set ourself into the gtt
* read domain and manually flush cachelines (if required). This
@@ -632,7 +568,6 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj,
!(obj->read_domains & I915_GEM_DOMAIN_CPU))
*needs_clflush = CLFLUSH_BEFORE;
-out:
/* return with the pages pinned */
return 0;
@@ -652,27 +587,22 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj,
assert_object_held(obj);
- ret = i915_gem_object_wait(obj,
- I915_WAIT_INTERRUPTIBLE |
- I915_WAIT_ALL,
- MAX_SCHEDULE_TIMEOUT);
- if (ret)
- return ret;
-
ret = i915_gem_object_pin_pages(obj);
if (ret)
return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE ||
- !static_cpu_has(X86_FEATURE_CLFLUSH)) {
- ret = i915_gem_object_set_to_cpu_domain(obj, true);
- if (ret)
- goto err_unpin;
- else
- goto out;
- }
+ !static_cpu_has(X86_FEATURE_CLFLUSH))
+ i915_gem_object_set_to_cpu_domain(obj, true);
+ else
+ flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
- flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ goto err_unpin;
/* If we're not in the cpu write domain, set ourself into the
* gtt write domain and manually flush cachelines (as required).
@@ -690,7 +620,6 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj,
*needs_clflush |= CLFLUSH_BEFORE;
}
-out:
i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
obj->mm.dirty = true;
/* return with the pages pinned */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3411ad197fa6..35a8d90f14f1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -513,12 +513,12 @@ void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj,
void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj);
void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj);
-int __must_check
-i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
-int __must_check
-i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
-int __must_check
-i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
+void i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj,
+ bool write);
+void i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
+ bool write);
+void i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
+ bool write);
struct i915_vma * __must_check
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
u32 alignment,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0438e00d4ca7..0a1fdbac882e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -183,6 +183,12 @@ struct drm_i915_gem_object {
unsigned int cache_coherent:2;
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
+ /*
+ * Note cache_dirty is only a guide; we know when we have written
+ * through the CPU cache, but we do not know when the CPU may have
+ * speculatively populated the cache. Before a read via the cache
+ * of GPU written memory, we have to cautiously invalidate the cache.
+ */
unsigned int cache_dirty:1;
/**
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index f6329e462cfc..10ee24b252dd 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -962,14 +962,6 @@ static int gpu_write(struct intel_context *ce,
u32 dw,
u32 val)
{
- int err;
-
- i915_gem_object_lock(vma->obj, NULL);
- err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
- i915_gem_object_unlock(vma->obj);
- if (err)
- return err;
-
return igt_gpu_fill_dw(ce, vma, dw * sizeof(u32),
vma->size >> PAGE_SHIFT, val);
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index 1117d2a44518..b5dbf15570fc 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -90,8 +90,13 @@ static int gtt_set(struct context *ctx, unsigned long offset, u32 v)
int err = 0;
i915_gem_object_lock(ctx->obj, NULL);
- err = i915_gem_object_set_to_gtt_domain(ctx->obj, true);
+ i915_gem_object_set_to_gtt_domain(ctx->obj, true);
i915_gem_object_unlock(ctx->obj);
+
+ err = i915_gem_object_wait(ctx->obj,
+ I915_WAIT_ALL |
+ I915_WAIT_INTERRUPTIBLE,
+ HZ / 2);
if (err)
return err;
@@ -123,8 +128,12 @@ static int gtt_get(struct context *ctx, unsigned long offset, u32 *v)
int err = 0;
i915_gem_object_lock(ctx->obj, NULL);
- err = i915_gem_object_set_to_gtt_domain(ctx->obj, false);
+ i915_gem_object_set_to_gtt_domain(ctx->obj, false);
i915_gem_object_unlock(ctx->obj);
+
+ err = i915_gem_object_wait(ctx->obj,
+ I915_WAIT_INTERRUPTIBLE,
+ HZ / 2);
if (err)
return err;
@@ -155,8 +164,13 @@ static int wc_set(struct context *ctx, unsigned long offset, u32 v)
int err;
i915_gem_object_lock(ctx->obj, NULL);
- err = i915_gem_object_set_to_wc_domain(ctx->obj, true);
+ i915_gem_object_set_to_wc_domain(ctx->obj, true);
i915_gem_object_unlock(ctx->obj);
+
+ err = i915_gem_object_wait(ctx->obj,
+ I915_WAIT_ALL |
+ I915_WAIT_INTERRUPTIBLE,
+ HZ / 2);
if (err)
return err;
@@ -178,8 +192,12 @@ static int wc_get(struct context *ctx, unsigned long offset, u32 *v)
int err;
i915_gem_object_lock(ctx->obj, NULL);
- err = i915_gem_object_set_to_wc_domain(ctx->obj, false);
+ i915_gem_object_set_to_wc_domain(ctx->obj, false);
i915_gem_object_unlock(ctx->obj);
+
+ err = i915_gem_object_wait(ctx->obj,
+ I915_WAIT_INTERRUPTIBLE,
+ HZ / 2);
if (err)
return err;
@@ -201,9 +219,7 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v)
int err;
i915_gem_object_lock(ctx->obj, NULL);
- err = i915_gem_object_set_to_gtt_domain(ctx->obj, true);
- if (err)
- goto out_unlock;
+ i915_gem_object_set_to_gtt_domain(ctx->obj, false);
vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
index 8cee68c6a6dc..b62d02cb9579 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
@@ -45,14 +45,10 @@ static int mock_phys_object(void *arg)
/* Make the object dirty so that put_pages must do copy back the data */
i915_gem_object_lock(obj, NULL);
- err = i915_gem_object_set_to_gtt_domain(obj, true);
+ i915_gem_object_set_to_gtt_domain(obj, true);
i915_gem_object_unlock(obj);
- if (err) {
- pr_err("i915_gem_object_set_to_gtt_domain failed with err=%d\n",
- err);
- goto out_obj;
- }
+ err = 0;
out_obj:
i915_gem_object_put(obj);
out:
diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
index d6783061bc72..b7e064667d39 100644
--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
+++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
@@ -7,6 +7,7 @@
#include "igt_gem_utils.h"
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_clflush.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"
@@ -138,6 +139,8 @@ int igt_gpu_fill_dw(struct intel_context *ce,
goto skip_request;
i915_vma_lock(vma);
+ if (vma->obj->cache_dirty & ~vma->obj->cache_coherent)
+ i915_gem_clflush_object(vma->obj, 0);
err = i915_request_await_object(rq, vma->obj, true);
if (err == 0)
err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f2f344ecf547..b2e3b5cfccb4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -306,11 +306,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
if (ret)
goto out_unpin;
- ret = i915_gem_object_set_to_gtt_domain(obj, false);
- if (ret) {
- i915_gem_object_unlock(obj);
- goto out_unpin;
- }
+ i915_gem_object_set_to_gtt_domain(obj, false);
fence = i915_gem_object_lock_fence(obj);
i915_gem_object_unlock(obj);
@@ -511,11 +507,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
if (ret)
goto out_unpin;
- ret = i915_gem_object_set_to_gtt_domain(obj, true);
- if (ret) {
- i915_gem_object_unlock(obj);
- goto out_unpin;
- }
+ i915_gem_object_set_to_gtt_domain(obj, true);
fence = i915_gem_object_lock_fence(obj);
i915_gem_object_unlock(obj);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/8] drm/i915/selftests: Set cache status for huge_gem_object
2021-02-03 9:01 [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object Chris Wilson
` (6 preceding siblings ...)
2021-02-03 9:02 ` [Intel-gfx] [CI 8/8] drm/i915/gem: Manage all set-domain waits explicitly Chris Wilson
@ 2021-02-03 10:49 ` Patchwork
2021-02-03 13:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2021-02-03 10:49 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4465 bytes --]
== Series Details ==
Series: series starting with [CI,1/8] drm/i915/selftests: Set cache status for huge_gem_object
URL : https://patchwork.freedesktop.org/series/86626/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9721 -> Patchwork_19570
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/index.html
Known issues
------------
Here are the changes found in Patchwork_19570 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#142] / [i915#2405])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@hangcheck:
- fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([i915#2782] / [i915#926])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/fi-icl-y/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/fi-icl-y/igt@i915_selftest@live@hangcheck.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
* igt@runner@aborted:
- fi-byt-j1900: NOTRUN -> [FAIL][7] ([i915#1814] / [i915#2505])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/fi-byt-j1900/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic:
- fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/fi-tgl-y/igt@gem_mmap_gtt@basic.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/fi-tgl-y/igt@gem_mmap_gtt@basic.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [FAIL][10] ([i915#579]) -> [SKIP][11] ([fdo#109271])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#926]: https://gitlab.freedesktop.org/drm/intel/issues/926
Participating hosts (42 -> 38)
------------------------------
Missing (4): fi-jsl-1 fi-bdw-samus fi-bsw-cyan fi-skl-6600u
Build changes
-------------
* Linux: CI_DRM_9721 -> Patchwork_19570
CI-20190529: 20190529
CI_DRM_9721: 2bd88ea627421f4c9179740592f21c2789e1afda @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5988: 4581082c706498cc3afe20e89fc4836a3fc69105 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19570: 6a011dd0f51abea8e0652c4b018b333a6fddf93a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6a011dd0f51a drm/i915/gem: Manage all set-domain waits explicitly
38603c58675f drm/i915/selftests: Remove redundant set-to-gtt-domain before batch submission
6b0fc3bf8497 drm/i915/selftests: Replace an unbounded set-domain wait with a timeout
5616e93b9fca drm/i915/selftests: Replace unbound set-domain waits with explicit timeouts
24b33d831171 drm/i915/selftests: Remove redundant set-to-gtt-domain
dfc407ff0fa7 drm/i915/selftests: Replace the unbounded set-domain with an explicit wait
61c7e3eb85eb drm/i915/selftests: Use a coherent map to setup scratch batch buffers
0f47176702b6 drm/i915/selftests: Set cache status for huge_gem_object
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/index.html
[-- Attachment #1.2: Type: text/html, Size: 5300 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/8] drm/i915/selftests: Set cache status for huge_gem_object
2021-02-03 9:01 [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object Chris Wilson
` (7 preceding siblings ...)
2021-02-03 10:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/8] drm/i915/selftests: Set cache status for huge_gem_object Patchwork
@ 2021-02-03 13:08 ` Patchwork
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2021-02-03 13:08 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30309 bytes --]
== Series Details ==
Series: series starting with [CI,1/8] drm/i915/selftests: Set cache status for huge_gem_object
URL : https://patchwork.freedesktop.org/series/86626/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9721_full -> Patchwork_19570_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19570_full:
### Piglit changes ###
#### Possible regressions ####
* spec@glsl-1.30@linker@interpolation-qualifiers@flat-gl_frontsecondarycolor-smooth-gl_backsecondarycolor (NEW):
- {pig-icl-1065g7}: NOTRUN -> [CRASH][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/pig-icl-1065g7/spec@glsl-1.30@linker@interpolation-qualifiers@flat-gl_frontsecondarycolor-smooth-gl_backsecondarycolor.html
* spec@glsl-1.30@linker@interpolation-qualifiers@unused-noperspective-gl_backcolor-unused-smooth-gl_color (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][2] +6 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/pig-icl-1065g7/spec@glsl-1.30@linker@interpolation-qualifiers@unused-noperspective-gl_backcolor-unused-smooth-gl_color.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* spec@glsl-1.10@execution@fs-dfdx-accuracy:
- {pig-kbl-iris}: NOTRUN -> [WARN][3] +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/pig-kbl-iris/spec@glsl-1.10@execution@fs-dfdx-accuracy.html
* spec@glsl-1.30@execution@tex-miplevel-selection textureoffset 2darrayshadow:
- {pig-kbl-iris}: NOTRUN -> [FAIL][4] +7 similar issues
[4]: None
New tests
---------
New tests have been introduced between CI_DRM_9721_full and Patchwork_19570_full:
### New Piglit tests (8) ###
* spec@glsl-1.30@linker@interpolation-qualifiers@flat-gl_frontcolor-default-gl_color:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@linker@interpolation-qualifiers@flat-gl_frontsecondarycolor-smooth-gl_backsecondarycolor:
- Statuses : 1 crash(s)
- Exec time: [0.27] s
* spec@glsl-1.30@linker@interpolation-qualifiers@noperspective-gl_backcolor-flat-gl_frontcolor:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@linker@interpolation-qualifiers@unused-flat-gl_backsecondarycolor-unused-noperspective-gl_secondarycolor:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@linker@interpolation-qualifiers@unused-noperspective-gl_backcolor-unused-smooth-gl_color:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@linker@interpolation-qualifiers@unused-smooth-gl_backsecondarycolor-unused-default-gl_secondarycolor:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@linker@interpolation-qualifiers@unused-smooth-gl_backsecondarycolor-unused-flat-gl_secondarycolor:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@linker@interpolation-qualifiers@unused-smooth-gl_frontsecondarycolor-unused-default-gl_secondarycolor:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_19570_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_capture@pi@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][5] ([i915#2295])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl6/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@gem_exec_fair@basic-none@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl6/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: NOTRUN -> [FAIL][10] ([i915#2851])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb3/igt@gem_exec_fair@basic-pace@vcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-tglb8/igt@gem_exec_fair@basic-pace@vcs1.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-tglb5/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: NOTRUN -> [FAIL][16] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][17] ([i915#2389])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb4/igt@gem_exec_reloc@basic-wide-active@vcs1.html
* igt@gem_exec_schedule@u-fairslice@bcs0:
- shard-tglb: [PASS][18] -> [DMESG-WARN][19] ([i915#2803])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-tglb1/igt@gem_exec_schedule@u-fairslice@bcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-tglb8/igt@gem_exec_schedule@u-fairslice@bcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-glk: [PASS][20] -> [DMESG-WARN][21] ([i915#1610] / [i915#2803])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-glk9/igt@gem_exec_schedule@u-fairslice@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-glk8/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-skl: NOTRUN -> [DMESG-WARN][22] ([i915#1610] / [i915#2803])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl2/igt@gem_exec_schedule@u-fairslice@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#2190])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl7/igt@gem_huc_copy@huc-copy.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [PASS][24] -> [FAIL][25] ([i915#644])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl8/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@mmap-offset-invalidate-active@wb:
- shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271]) +76 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl4/igt@gem_userptr_blits@mmap-offset-invalidate-active@wb.html
* igt@gem_vm_create@destroy-race:
- shard-tglb: [PASS][27] -> [TIMEOUT][28] ([i915#2795])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-tglb1/igt@gem_vm_create@destroy-race.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-tglb7/igt@gem_vm_create@destroy-race.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#180])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl7/igt@i915_suspend@sysfs-reader.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl1/igt@i915_suspend@sysfs-reader.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][31] -> [FAIL][32] ([i915#2597])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-tglb6/igt@kms_async_flips@test-time-stamp.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-tglb6/igt@kms_async_flips@test-time-stamp.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-c:
- shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#165] / [i915#180]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-c.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-c.html
* igt@kms_big_joiner@basic:
- shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#2705])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl6/igt@kms_big_joiner@basic.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-skl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +5 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl7/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color@pipe-d-ctm-max:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271]) +52 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl1/igt@kms_color@pipe-d-ctm-max.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +5 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl1/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-a-degamma:
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +4 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl6/igt@kms_color_chamelium@pipe-a-degamma.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][40] ([i915#1319])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl4/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#54]) +7 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen:
- shard-skl: NOTRUN -> [FAIL][43] ([i915#54]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [PASS][44] -> [FAIL][45] ([i915#2346])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][46] -> [INCOMPLETE][47] ([i915#155] / [i915#180] / [i915#636])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [PASS][48] -> [FAIL][49] ([i915#2122]) +4 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#2642])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271]) +22 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_hdr@static-toggle-dpms:
- shard-iclb: NOTRUN -> [SKIP][52] ([i915#1187])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb6/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- shard-kbl: [PASS][53] -> [DMESG-WARN][54] ([i915#165]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#533])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl4/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][58] ([fdo#108145] / [i915#265])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-kbl: [PASS][60] -> [DMESG-WARN][61] ([i915#165] / [i915#180] / [i915#2621] / [i915#78])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-y.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_plane_lowres@pipe-b-tiling-none:
- shard-kbl: [PASS][62] -> [DMESG-WARN][63] ([i915#180] / [i915#78]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@kms_plane_lowres@pipe-b-tiling-none.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl2/igt@kms_plane_lowres@pipe-b-tiling-none.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr2_su@page_flip:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl7/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][66] -> [SKIP][67] ([fdo#109441]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: [PASS][68] -> [DMESG-WARN][69] ([i915#180])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2437])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl6/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@polling:
- shard-skl: [PASS][71] -> [FAIL][72] ([i915#1542])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl4/igt@perf@polling.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl1/igt@perf@polling.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [DMESG-WARN][73] ([i915#180]) -> [PASS][74] +3 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl: [FAIL][75] ([i915#2389]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl3/igt@gem_exec_reloc@basic-many-active@rcs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl1/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-iclb: [DMESG-WARN][77] ([i915#2803]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb2/igt@gem_exec_schedule@u-fairslice@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb6/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw: [FAIL][79] ([i915#1860]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw1/igt@i915_pm_rc6_residency@rc6-idle.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-hsw6/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: [DMESG-WARN][81] ([i915#180]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl1/igt@i915_suspend@fence-restore-untiled.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl1/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_color@pipe-a-ctm-max:
- shard-hsw: [DMESG-WARN][83] ([i915#44]) -> [PASS][84] +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw5/igt@kms_color@pipe-a-ctm-max.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-hsw8/igt@kms_color@pipe-a-ctm-max.html
* igt@kms_color@pipe-a-legacy-gamma:
- shard-hsw: [DMESG-FAIL][85] ([i915#44]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw5/igt@kms_color@pipe-a-legacy-gamma.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-hsw8/igt@kms_color@pipe-a-legacy-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-skl: [FAIL][87] ([i915#54]) -> [PASS][88] +4 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [INCOMPLETE][89] ([i915#2295] / [i915#300]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen:
- shard-hsw: [FAIL][91] -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw5/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-hsw8/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][93] ([i915#96]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: [FAIL][95] ([i915#2346]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][97] ([i915#79]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][99] ([i915#1188]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][101] ([fdo#108145] / [i915#265]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][103] ([fdo#109441]) -> [PASS][104] +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][105] ([i915#198]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-skl3/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-skl7/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
* {igt@sysfs_clients@recycle}:
- shard-hsw: [FAIL][107] ([i915#3028]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-hsw6/igt@sysfs_clients@recycle.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-hsw2/igt@sysfs_clients@recycle.html
- shard-apl: [FAIL][109] ([i915#3028]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl1/igt@sysfs_clients@recycle.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-apl2/igt@sysfs_clients@recycle.html
* {igt@sysfs_clients@recycle-many}:
- shard-glk: [FAIL][111] -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-glk8/igt@sysfs_clients@recycle-many.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-glk2/igt@sysfs_clients@recycle-many.html
#### Warnings ####
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][113] ([i915#2842]) -> [FAIL][114] ([i915#2849])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][115] ([i915#1804] / [i915#2684]) -> [WARN][116] ([i915#2681] / [i915#2684])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: [SKIP][117] ([i915#2920]) -> [SKIP][118] ([i915#658])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb6/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][119] ([i915#658]) -> [SKIP][120] ([i915#2920])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132]) ([i915#1436] / [i915#1814] / [i915#2295] / [i915#3002] / [i915#602]) -> ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142]) ([i915#1436] / [i915#1814] / [i915#2295] / [i915#3002] / [i915#602] / [i915#92])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl4/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl7/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl4/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl4/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl1/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-kbl2/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl4/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl2/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl4/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl1/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl1/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl1/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl7/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl7/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl2/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-kbl2/igt@runner@aborted.html
- shard-iclb: ([FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146]) ([i915#2295] / [i915#2426] / [i915#2724] / [i915#3002]) -> ([FAIL][147], [FAIL][148], [FAIL][149]) ([i915#2295] / [i915#2724] / [i915#3002])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb5/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb7/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb2/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-iclb1/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb3/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb2/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/shard-iclb5/igt@runner@aborted.html
- shard-apl: ([FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154]) ([i915#2295] / [i915#3002]) -> ([FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158]) ([i915#1814] / [i915#2295] / [i915#3002])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9721/shard-apl7/igt@runner@aborted.html
[151]: https://intel-
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19570/index.html
[-- Attachment #1.2: Type: text/html, Size: 33772 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-02-03 13:08 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-03 9:01 [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object Chris Wilson
2021-02-03 9:01 ` [Intel-gfx] [CI 2/8] drm/i915/selftests: Use a coherent map to setup scratch batch buffers Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 3/8] drm/i915/selftests: Replace the unbounded set-domain with an explicit wait Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 4/8] drm/i915/selftests: Remove redundant set-to-gtt-domain Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 5/8] drm/i915/selftests: Replace unbound set-domain waits with explicit timeouts Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 6/8] drm/i915/selftests: Replace an unbounded set-domain wait with a timeout Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 7/8] drm/i915/selftests: Remove redundant set-to-gtt-domain before batch submission Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 8/8] drm/i915/gem: Manage all set-domain waits explicitly Chris Wilson
2021-02-03 10:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/8] drm/i915/selftests: Set cache status for huge_gem_object Patchwork
2021-02-03 13:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).