[Intel-gfx] [PATCH 1/4] drm/i915/gen12: Add recommended hardware tuning value

[Intel-gfx] [PATCH 1/4] drm/i915/gen12: Add recommended hardware tuning value

[Lucas De Marchi]

From: Caz Yokoyama <caz.yokoyama@intel.com>

Follow Bspec 31870 to set recommended tuning values for certain GT
register.  These values aren't workarounds per-se, but it's best to
handle them in the same general area of the driver, especially since
there may be real workarounds that update other bits of the same
registers.

At the moment the only value we need to worry about is the
TDS_TIMER setting in FF_MODE2.  This setting was previously
described as "Wa_1604555607" on some platforms, but the spec
tells us that we should continue to program this on all current
gen12 platforms, even those that do not have that WA.

Bspec: 31870

Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++++++++++++++++-----
 1 file changed, 37 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b4a7da60f0b..f6d9b849aa62 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -646,9 +646,38 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
 }
 
+/*
+ * These settings aren't actually workarounds, but general tuning settings that
+ * need to be programmed on several platforms.
+ */
+static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
+				     struct i915_wa_list *wal)
+{
+	/*
+	 * Although some platforms refer to it as Wa_1604555607, we need to
+	 * program it even on those that don't explicitly list that
+	 * workaround.
+	 *
+	 * Note that the implementation of this workaround is further modified
+	 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
+	 *
+	 * FF_MODE2 register will return the wrong value when read. The default
+	 * value for this register is zero for all fields and there are no bit
+	 * masks. So instead of doing a RMW we should just write TDS timer
+	 * value. For the same reason read verification is ignored.
+	 */
+	wa_add(wal,
+	       FF_MODE2,
+	       FF_MODE2_TDS_TIMER_MASK,
+	       FF_MODE2_TDS_TIMER_128,
+	       0);
+}
+
 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
 				       struct i915_wa_list *wal)
 {
+	gen12_ctx_gt_tuning_init(engine, wal);
+
 	/*
 	 * Wa_1409142259:tgl
 	 * Wa_1409347922:tgl
@@ -675,19 +704,15 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	gen12_ctx_workarounds_init(engine, wal);
 
 	/*
-	 * Wa_1604555607:tgl,rkl
+	 * Wa_16011163337
 	 *
-	 * Note that the implementation of this workaround is further modified
-	 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
-	 * FF_MODE2 register will return the wrong value when read. The default
-	 * value for this register is zero for all fields and there are no bit
-	 * masks. So instead of doing a RMW we should just write the GS Timer
-	 * and TDS timer values for Wa_1604555607 and Wa_16011163337.
+	 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due
+	 * to Wa_1608008084.
 	 */
 	wa_add(wal,
 	       FF_MODE2,
-	       FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
-	       FF_MODE2_GS_TIMER_224  | FF_MODE2_TDS_TIMER_128,
+	       FF_MODE2_GS_TIMER_MASK,
+	       FF_MODE2_GS_TIMER_224,
 	       0);
 }
 
@@ -707,12 +732,13 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
 	/*
 	 * Wa_16011163337
 	 *
-	 * Like in tgl_ctx_workarounds_init(), read verification is ignored due
+	 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due
 	 * to Wa_1608008084.
 	 */
 	wa_add(wal,
 	       FF_MODE2,
-	       FF_MODE2_GS_TIMER_MASK, FF_MODE2_GS_TIMER_224, 0);
+	       FF_MODE2_GS_TIMER_MASK,
+	       FF_MODE2_GS_TIMER_224, 0);
 }
 
 static void
-- 
2.30.1

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[Intel-gfx] [PATCH 2/4] drm/i915/icl: add Wa_22010271021 for all gen11

[Lucas De Marchi]

From: Caz Yokoyama <caz.yokoyama@intel.com>

Wa_22010271021 does not apply only to EHL, but to all gen11 platforms.

Bspec: 33450, 52887

Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f6d9b849aa62..9e6e405aabac 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1820,11 +1820,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN7_FF_THREAD_MODE,
 			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
-		/* Wa_22010271021:ehl */
-		if (IS_JSL_EHL(i915))
-			wa_masked_en(wal,
-				     GEN9_CS_DEBUG_MODE1,
-				     FF_DOP_CLOCK_GATE_DISABLE);
+		/* Wa_22010271021:gen11 */
+		wa_masked_en(wal,
+			     GEN9_CS_DEBUG_MODE1,
+			     FF_DOP_CLOCK_GATE_DISABLE);
 	}
 
 	if (IS_GEN_RANGE(i915, 9, 12)) {
-- 
2.30.1

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[Intel-gfx] [PATCH 3/4] drm/i915: Wa_14010826681 does the same as Wa_22010271021

[Lucas De Marchi]

From: Caz Yokoyama <caz.yokoyama@intel.com>

Add a comment marking Wa_14010826681 as the same as Wa_22010271021
for easy verification.

Bspec: 54508, 52890

Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9e6e405aabac..e678fa8d2ab9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1682,7 +1682,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 		/*
 		 * Wa_1606700617:tgl,dg1
-		 * Wa_22010271021:tgl,rkl,dg1, adl-s
+		 * Wa_22010271021:tgl,rkl,dg1,adl-s
+		 * Wa_14010826681:tgl,dg1
 		 */
 		wa_masked_en(wal,
 			     GEN9_CS_DEBUG_MODE1,
-- 
2.30.1

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[Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

[Lucas De Marchi]

From: Zhen Han <zhen.han@intel.com>

GPU hangs at RCC. According to Wa_14012131227 we shouldn't have a hang
due to RHWO, but that is what we are observing, even without media
compressible render target. Feedback from HW engineers is to leave RHWO
disabled.

Cc: Jianjun Liu <Jianjun.liu@intel.com>
Cc: Chuansheng Liu <chuansheng.liu@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Zhen Han <zhen.han@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e678fa8d2ab9..5235fb70a69a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -739,6 +739,17 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
 	       FF_MODE2,
 	       FF_MODE2_GS_TIMER_MASK,
 	       FF_MODE2_GS_TIMER_224, 0);
+
+	/*
+	 * Wa_14012131227
+	 *
+	 * Although the WA is described as causing corruption when using media
+	 * compressible render target, leaving RHWO enabled is also causing
+	 * gpu hang when using multiple concurrent render and media workloads.
+	 * Disable it completely for now.
+	 */
+	wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1,
+		     GEN9_RHWO_OPTIMIZATION_DISABLE);
 }
 
 static void
-- 
2.30.1

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Re: [Intel-gfx] [PATCH 1/4] drm/i915/gen12: Add recommended hardware tuning value

[Matt Roper]

On Tue, Mar 02, 2021 at 05:07:25PM -0800, Lucas De Marchi wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
> 
> Follow Bspec 31870 to set recommended tuning values for certain GT
> register.  These values aren't workarounds per-se, but it's best to
> handle them in the same general area of the driver, especially since
> there may be real workarounds that update other bits of the same
> registers.
> 
> At the moment the only value we need to worry about is the
> TDS_TIMER setting in FF_MODE2.  This setting was previously
> described as "Wa_1604555607" on some platforms, but the spec
> tells us that we should continue to program this on all current
> gen12 platforms, even those that do not have that WA.
> 
> Bspec: 31870
> 
> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

A couple minor nitpicks about the comments, but you can tweak those
while applying.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

There appear to be some other registers recommended on the same bspec
tuning page that we don't seem to be handling yet.  Will those be coming
as additional patches?

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++++++++++++++++-----
>  1 file changed, 37 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3b4a7da60f0b..f6d9b849aa62 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -646,9 +646,38 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
>  }
>  
> +/*
> + * These settings aren't actually workarounds, but general tuning settings that
> + * need to be programmed on several platforms.
> + */
> +static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> +				     struct i915_wa_list *wal)
> +{
> +	/*
> +	 * Although some platforms refer to it as Wa_1604555607, we need to
> +	 * program it even on those that don't explicitly list that
> +	 * workaround.
> +	 *
> +	 * Note that the implementation of this workaround is further modified

Since we just got done saying that this technically isn't a workaround,
even though some of the older platforms still list it that way, I'd
re-word the comment here.  Maybe "Note that the programming of this
register is further modified..." would be more appropriate.

> +	 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
> +	 *

Minor nitpick; the new paragraph start here makes it sound like we've
moved on to describing something else, rather than explaining what
Wa_1608008084:gen12 asks us to do.  I'd remove the blank line here and
start the next sentence with "Wa_1608008084 tells us..." to link the
statements together.


Matt

> +	 * FF_MODE2 register will return the wrong value when read. The default
> +	 * value for this register is zero for all fields and there are no bit
> +	 * masks. So instead of doing a RMW we should just write TDS timer
> +	 * value. For the same reason read verification is ignored.
> +	 */
> +	wa_add(wal,
> +	       FF_MODE2,
> +	       FF_MODE2_TDS_TIMER_MASK,
> +	       FF_MODE2_TDS_TIMER_128,
> +	       0);
> +}
> +
>  static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
>  				       struct i915_wa_list *wal)
>  {
> +	gen12_ctx_gt_tuning_init(engine, wal);
> +
>  	/*
>  	 * Wa_1409142259:tgl
>  	 * Wa_1409347922:tgl
> @@ -675,19 +704,15 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	gen12_ctx_workarounds_init(engine, wal);
>  
>  	/*
> -	 * Wa_1604555607:tgl,rkl
> +	 * Wa_16011163337
>  	 *
> -	 * Note that the implementation of this workaround is further modified
> -	 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
> -	 * FF_MODE2 register will return the wrong value when read. The default
> -	 * value for this register is zero for all fields and there are no bit
> -	 * masks. So instead of doing a RMW we should just write the GS Timer
> -	 * and TDS timer values for Wa_1604555607 and Wa_16011163337.
> +	 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due
> +	 * to Wa_1608008084.
>  	 */
>  	wa_add(wal,
>  	       FF_MODE2,
> -	       FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
> -	       FF_MODE2_GS_TIMER_224  | FF_MODE2_TDS_TIMER_128,
> +	       FF_MODE2_GS_TIMER_MASK,
> +	       FF_MODE2_GS_TIMER_224,
>  	       0);
>  }
>  
> @@ -707,12 +732,13 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	/*
>  	 * Wa_16011163337
>  	 *
> -	 * Like in tgl_ctx_workarounds_init(), read verification is ignored due
> +	 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due
>  	 * to Wa_1608008084.
>  	 */
>  	wa_add(wal,
>  	       FF_MODE2,
> -	       FF_MODE2_GS_TIMER_MASK, FF_MODE2_GS_TIMER_224, 0);
> +	       FF_MODE2_GS_TIMER_MASK,
> +	       FF_MODE2_GS_TIMER_224, 0);
>  }
>  
>  static void
> -- 
> 2.30.1
> 

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 2/4] drm/i915/icl: add Wa_22010271021 for all gen11

[Matt Roper]

On Tue, Mar 02, 2021 at 05:07:26PM -0800, Lucas De Marchi wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
> 
> Wa_22010271021 does not apply only to EHL, but to all gen11 platforms.

It also applies to a bunch of gen12 platforms; we already apply the same
workaround in an earlier block of the same function too to handle all of
them.  It's fine to keep the gen11 and gen12 copies separate and prevent
even more complicated if/else chains in this function that's already
overly-complicated, but you should probably just drop the ":gen11"
suffix on the code comment and you may want to tweak the commit message
here to indicate that we already have this handled properly for all the
gen12 platforms.

Aside from that,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> 
> Bspec: 33450, 52887
> 
> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index f6d9b849aa62..9e6e405aabac 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1820,11 +1820,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  			    GEN7_FF_THREAD_MODE,
>  			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
>  
> -		/* Wa_22010271021:ehl */
> -		if (IS_JSL_EHL(i915))
> -			wa_masked_en(wal,
> -				     GEN9_CS_DEBUG_MODE1,
> -				     FF_DOP_CLOCK_GATE_DISABLE);
> +		/* Wa_22010271021:gen11 */
> +		wa_masked_en(wal,
> +			     GEN9_CS_DEBUG_MODE1,
> +			     FF_DOP_CLOCK_GATE_DISABLE);
>  	}
>  
>  	if (IS_GEN_RANGE(i915, 9, 12)) {
> -- 
> 2.30.1
> 

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 3/4] drm/i915: Wa_14010826681 does the same as Wa_22010271021

[Matt Roper]

On Tue, Mar 02, 2021 at 05:07:27PM -0800, Lucas De Marchi wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
> 
> Add a comment marking Wa_14010826681 as the same as Wa_22010271021
> for easy verification.
> 
> Bspec: 54508, 52890
> 
> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9e6e405aabac..e678fa8d2ab9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1682,7 +1682,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  
>  		/*
>  		 * Wa_1606700617:tgl,dg1
> -		 * Wa_22010271021:tgl,rkl,dg1, adl-s
> +		 * Wa_22010271021:tgl,rkl,dg1,adl-s
> +		 * Wa_14010826681:tgl,dg1
>  		 */
>  		wa_masked_en(wal,
>  			     GEN9_CS_DEBUG_MODE1,
> -- 
> 2.30.1
> 

-- 
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Intel Corporation
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Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

[Han, Zhen]

[-- Attachment #1.1: Type: text/plain, Size: 3610 bytes --]

Yes, that's the case.
It has RCC related silicon issues in gen12-lp.
Followings are two consecutive GPU hangs we found in SG1 and DG1 linux which have no media compressible render target.
1. HSD-1508524297<https://hsdes.intel.com/appstore/article/>  [SG1][DG1] GPU hang in PIPECONTROL in running 120 ways of Android container with running pocket story HD apk.
--> The solution is disable RHWO optimization in default.
2. hsd-1508734716<https://hsdes.intel.com/appstore/article/> [DG1][Linux] GPU hang in PIPECONTROL(IPEHR:0x7a000004) with (PSS, RCPFE, RCC, WMFE) not done in running Monkey test
--> The solution is keeping RHWO optimization in when Render Target Resolve type is PARTIAL or FULL. The change will be in mesa code.

SV and RCC design team have further study and give the root cause explain the bug-eco HSD of 1508744258 - Hang due to deadlock created by RHWO scenario with RHWO optimization enabled<https://hsdes.intel.com/appstore/article/>.

BTW, recently, Windows team found similar GPU hangs in custom's TGL platform and need "disable RHWO" as the WA solution.  So it's a general issues in Gen12 (TGL and DG1).
*       14012336472 - [HP-TDC_IEC/HarryPotter]SIO1880260 Simple Solitaire UI show garbage when playing the game by finger.<https://hsdes.intel.com/appstore/article/>
*       18014955083 - [TGL] Sporadic pixel shader hang when alpha blending is enabled <https://hsdes.intel.com/appstore/article/>  (SV sighting)

Thanks
Han Zhen

-----Original Message-----
From: De Marchi, Lucas <lucas.demarchi@intel.com>
Sent: Wednesday, March 3, 2021 9:07 AM
To: intel-gfx@lists.freedesktop.org
Cc: Han, Zhen <zhen.han@intel.com>; Liu, Jianjun <jianjun.liu@intel.com>; Liu, Chuansheng <chuansheng.liu@intel.com>; Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
Subject: [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

From: Zhen Han <zhen.han@intel.com<mailto:zhen.han@intel.com>>

GPU hangs at RCC. According to Wa_14012131227 we shouldn't have a hang due to RHWO, but that is what we are observing, even without media compressible render target. Feedback from HW engineers is to leave RHWO disabled.

Cc: Jianjun Liu <Jianjun.liu@intel.com<mailto:Jianjun.liu@intel.com>>
Cc: Chuansheng Liu <chuansheng.liu@intel.com<mailto:chuansheng.liu@intel.com>>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com<mailto:radhakrishna.sripada@intel.com>>
Signed-off-by: Zhen Han <zhen.han@intel.com<mailto:zhen.han@intel.com>>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com<mailto:lucas.demarchi@intel.com>>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e678fa8d2ab9..5235fb70a69a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -739,6 +739,17 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
               FF_MODE2,
               FF_MODE2_GS_TIMER_MASK,
               FF_MODE2_GS_TIMER_224, 0);
+
+       /*
+        * Wa_14012131227
+        *
+        * Although the WA is described as causing corruption when using media
+        * compressible render target, leaving RHWO enabled is also causing
+        * gpu hang when using multiple concurrent render and media workloads.
+        * Disable it completely for now.
+        */
+       wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1,
+                    GEN9_RHWO_OPTIMIZATION_DISABLE);
 }

 static void
--
2.30.1



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Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

[Matt Roper]

On Tue, Mar 02, 2021 at 05:07:28PM -0800, Lucas De Marchi wrote:
> From: Zhen Han <zhen.han@intel.com>
> 
> GPU hangs at RCC. According to Wa_14012131227 we shouldn't have a hang
> due to RHWO, but that is what we are observing, even without media
> compressible render target. Feedback from HW engineers is to leave RHWO
> disabled.

"14012131227" isn't the correct workaround number; that's a
platform-specific identifier.  This should be referred to by its lineage
number 22011054531 which is common across all affected platforms.
From a quick scan, it looks like this isn't just a DG1 workaround, but
also applies to at least TGL and ADL-S as well (and is pending for RKL).

I'm not sure we actually need this workaround in the kernel though.
We're already whitelisting this register for userspace to allow UMD's to
apply workarounds to it directly (and UMD's are already doing their own
programming of the register for Wa_1808121037).  So it may be best to
leave the handling of this additional bit to them as well, especially if
the desired handling doesn't quite match the officially documented
workaround text.


Matt

> 
> Cc: Jianjun Liu <Jianjun.liu@intel.com>
> Cc: Chuansheng Liu <chuansheng.liu@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Zhen Han <zhen.han@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e678fa8d2ab9..5235fb70a69a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -739,6 +739,17 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	       FF_MODE2,
>  	       FF_MODE2_GS_TIMER_MASK,
>  	       FF_MODE2_GS_TIMER_224, 0);
> +
> +	/*
> +	 * Wa_14012131227
> +	 *
> +	 * Although the WA is described as causing corruption when using media
> +	 * compressible render target, leaving RHWO enabled is also causing
> +	 * gpu hang when using multiple concurrent render and media workloads.
> +	 * Disable it completely for now.
> +	 */
> +	wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1,
> +		     GEN9_RHWO_OPTIMIZATION_DISABLE);
>  }
>  
>  static void
> -- 
> 2.30.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

[Han, Zhen]

Dear Matt,

Yes, it needs the WA in TGL.  Not sure the ADL-S and RKL.
The issue is different from 1808121037.
Previously, it was not found which exact usage condition needs to disable RHWO in studying the Alibaba issue in SG1, so make this change in kernel. 
Should we move the " disable RHWO " to mesa default setting path? 

Thanks
Han Zhen
-----Original Message-----
From: Roper, Matthew D <matthew.d.roper@intel.com> 
Sent: Wednesday, March 3, 2021 11:37 AM
To: De Marchi, Lucas <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org; Liu, Jianjun <jianjun.liu@intel.com>; Han, Zhen <zhen.han@intel.com>
Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

On Tue, Mar 02, 2021 at 05:07:28PM -0800, Lucas De Marchi wrote:
> From: Zhen Han <zhen.han@intel.com>
> 
> GPU hangs at RCC. According to Wa_14012131227 we shouldn't have a hang 
> due to RHWO, but that is what we are observing, even without media 
> compressible render target. Feedback from HW engineers is to leave 
> RHWO disabled.

"14012131227" isn't the correct workaround number; that's a platform-specific identifier.  This should be referred to by its lineage number 22011054531 which is common across all affected platforms.
From a quick scan, it looks like this isn't just a DG1 workaround, but also applies to at least TGL and ADL-S as well (and is pending for RKL).

I'm not sure we actually need this workaround in the kernel though.
We're already whitelisting this register for userspace to allow UMD's to apply workarounds to it directly (and UMD's are already doing their own programming of the register for Wa_1808121037).  So it may be best to leave the handling of this additional bit to them as well, especially if the desired handling doesn't quite match the officially documented workaround text.


Matt

> 
> Cc: Jianjun Liu <Jianjun.liu@intel.com>
> Cc: Chuansheng Liu <chuansheng.liu@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Zhen Han <zhen.han@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e678fa8d2ab9..5235fb70a69a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -739,6 +739,17 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	       FF_MODE2,
>  	       FF_MODE2_GS_TIMER_MASK,
>  	       FF_MODE2_GS_TIMER_224, 0);
> +
> +	/*
> +	 * Wa_14012131227
> +	 *
> +	 * Although the WA is described as causing corruption when using media
> +	 * compressible render target, leaving RHWO enabled is also causing
> +	 * gpu hang when using multiple concurrent render and media workloads.
> +	 * Disable it completely for now.
> +	 */
> +	wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1,
> +		     GEN9_RHWO_OPTIMIZATION_DISABLE);
>  }
>  
>  static void
> --
> 2.30.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/4] drm/i915/gen12: Add recommended hardware tuning value (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/gen12: Add recommended hardware tuning value (rev2)
URL   : https://patchwork.freedesktop.org/series/87560/
State : failure

== Summary ==

Applying: drm/i915/gen12: Add recommended hardware tuning value
Applying: drm/i915/icl: add Wa_22010271021 for all gen11
Applying: drm/i915: Wa_14010826681 does the same as Wa_22010271021
Applying: drm/i915/dg1: WA GPU hang at RCC
error: patch failed: drivers/gpu/drm/i915/gt/intel_workarounds.c:739
error: drivers/gpu/drm/i915/gt/intel_workarounds.c: patch does not apply
error: Did you hand edit your patch?
It does not apply to blobs recorded in its index.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Using index info to reconstruct a base tree...
Patch failed at 0004 drm/i915/dg1: WA GPU hang at RCC
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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Re: [Intel-gfx] [PATCH 1/4] drm/i915/gen12: Add recommended hardware tuning value

[Lucas De Marchi]

On Tue, Mar 02, 2021 at 07:14:07PM -0800, Matt Roper wrote:
>On Tue, Mar 02, 2021 at 05:07:25PM -0800, Lucas De Marchi wrote:
>> From: Caz Yokoyama <caz.yokoyama@intel.com>
>>
>> Follow Bspec 31870 to set recommended tuning values for certain GT
>> register.  These values aren't workarounds per-se, but it's best to
>> handle them in the same general area of the driver, especially since
>> there may be real workarounds that update other bits of the same
>> registers.
>>
>> At the moment the only value we need to worry about is the
>> TDS_TIMER setting in FF_MODE2.  This setting was previously
>> described as "Wa_1604555607" on some platforms, but the spec
>> tells us that we should continue to program this on all current
>> gen12 platforms, even those that do not have that WA.
>>
>> Bspec: 31870
>>
>> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>A couple minor nitpicks about the comments, but you can tweak those
>while applying.
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>There appear to be some other registers recommended on the same bspec
>tuning page that we don't seem to be handling yet.  Will those be coming
>as additional patches?

I don't have those ready, but that is the intention, yes. Here I
basically wanted to get the basic changes in place to make those
possible, while moving the one we already have in the driver there.

>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++++++++++++++++-----
>>  1 file changed, 37 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 3b4a7da60f0b..f6d9b849aa62 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -646,9 +646,38 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>  	wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
>>  }
>>
>> +/*
>> + * These settings aren't actually workarounds, but general tuning settings that
>> + * need to be programmed on several platforms.
>> + */
>> +static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>> +				     struct i915_wa_list *wal)
>> +{
>> +	/*
>> +	 * Although some platforms refer to it as Wa_1604555607, we need to
>> +	 * program it even on those that don't explicitly list that
>> +	 * workaround.
>> +	 *
>> +	 * Note that the implementation of this workaround is further modified
>
>Since we just got done saying that this technically isn't a workaround,
>even though some of the older platforms still list it that way, I'd
>re-word the comment here.  Maybe "Note that the programming of this
>register is further modified..." would be more appropriate.
>
>> +	 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
>> +	 *
>
>Minor nitpick; the new paragraph start here makes it sound like we've
>moved on to describing something else, rather than explaining what
>Wa_1608008084:gen12 asks us to do.  I'd remove the blank line here and
>start the next sentence with "Wa_1608008084 tells us..." to link the
>statements together.

thanks. I changed those and will resubmit.

Lucas De Marchi

>
>
>Matt
>
>> +	 * FF_MODE2 register will return the wrong value when read. The default
>> +	 * value for this register is zero for all fields and there are no bit
>> +	 * masks. So instead of doing a RMW we should just write TDS timer
>> +	 * value. For the same reason read verification is ignored.
>> +	 */
>> +	wa_add(wal,
>> +	       FF_MODE2,
>> +	       FF_MODE2_TDS_TIMER_MASK,
>> +	       FF_MODE2_TDS_TIMER_128,
>> +	       0);
>> +}
>> +
>>  static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
>>  				       struct i915_wa_list *wal)
>>  {
>> +	gen12_ctx_gt_tuning_init(engine, wal);
>> +
>>  	/*
>>  	 * Wa_1409142259:tgl
>>  	 * Wa_1409347922:tgl
>> @@ -675,19 +704,15 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>  	gen12_ctx_workarounds_init(engine, wal);
>>
>>  	/*
>> -	 * Wa_1604555607:tgl,rkl
>> +	 * Wa_16011163337
>>  	 *
>> -	 * Note that the implementation of this workaround is further modified
>> -	 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
>> -	 * FF_MODE2 register will return the wrong value when read. The default
>> -	 * value for this register is zero for all fields and there are no bit
>> -	 * masks. So instead of doing a RMW we should just write the GS Timer
>> -	 * and TDS timer values for Wa_1604555607 and Wa_16011163337.
>> +	 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due
>> +	 * to Wa_1608008084.
>>  	 */
>>  	wa_add(wal,
>>  	       FF_MODE2,
>> -	       FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
>> -	       FF_MODE2_GS_TIMER_224  | FF_MODE2_TDS_TIMER_128,
>> +	       FF_MODE2_GS_TIMER_MASK,
>> +	       FF_MODE2_GS_TIMER_224,
>>  	       0);
>>  }
>>
>> @@ -707,12 +732,13 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
>>  	/*
>>  	 * Wa_16011163337
>>  	 *
>> -	 * Like in tgl_ctx_workarounds_init(), read verification is ignored due
>> +	 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due
>>  	 * to Wa_1608008084.
>>  	 */
>>  	wa_add(wal,
>>  	       FF_MODE2,
>> -	       FF_MODE2_GS_TIMER_MASK, FF_MODE2_GS_TIMER_224, 0);
>> +	       FF_MODE2_GS_TIMER_MASK,
>> +	       FF_MODE2_GS_TIMER_224, 0);
>>  }
>>
>>  static void
>> --
>> 2.30.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
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[Intel-gfx] [PATCH 2/4] drm/i915/icl: add Wa_22010271021 for all gen11

[Lucas De Marchi]

From: Caz Yokoyama <caz.yokoyama@intel.com>

Wa_22010271021 does not apply only to EHL, but to all gen11 and other
gen12 platforms. Gen12 is already covered in another code path, but we
need to stop checking for EHL when handling gen11.

Bspec: 33450, 52887

v2: Remove "gen11" suffix as it also applies to gen12 platforms

Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2e367f95b989..3c609adca2ee 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1820,11 +1820,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN7_FF_THREAD_MODE,
 			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
-		/* Wa_22010271021:ehl */
-		if (IS_JSL_EHL(i915))
-			wa_masked_en(wal,
-				     GEN9_CS_DEBUG_MODE1,
-				     FF_DOP_CLOCK_GATE_DISABLE);
+		/* Wa_22010271021 */
+		wa_masked_en(wal,
+			     GEN9_CS_DEBUG_MODE1,
+			     FF_DOP_CLOCK_GATE_DISABLE);
 	}
 
 	if (IS_GEN_RANGE(i915, 9, 12)) {
-- 
2.31.0

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