From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: matthew.auld@intel.com, Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH v5 04/12] drm/i915/gt: Add an insert_entry for gen8_ppgtt
Date: Thu, 17 Jun 2021 08:30:10 +0200 [thread overview]
Message-ID: <20210617063018.92802-5-thomas.hellstrom@linux.intel.com> (raw)
In-Reply-To: <20210617063018.92802-1-thomas.hellstrom@linux.intel.com>
From: Chris Wilson <chris@chris-wilson.co.uk>
In the next patch, we will want to write a PTE for an explicit
dma address, outside of the usual vma.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 21c8b7350b7a..1b676d7700bf 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -555,6 +555,24 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
}
}
+static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ u64 idx = offset >> GEN8_PTE_SHIFT;
+ struct i915_page_directory * const pdp =
+ gen8_pdp_for_page_index(vm, idx);
+ struct i915_page_directory *pd =
+ i915_pd_entry(pdp, gen8_pd_index(idx, 2));
+ gen8_pte_t *vaddr;
+
+ vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+ vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
+ clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+}
+
static int gen8_init_scratch(struct i915_address_space *vm)
{
u32 pte_flags;
@@ -734,6 +752,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
+ ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
ppgtt->vm.clear_range = gen8_ppgtt_clear;
--
2.31.1
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next prev parent reply other threads:[~2021-06-17 6:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 6:30 [Intel-gfx] [PATCH v5 00/12] i915 TTM sync accelerated migration and clear Thomas Hellström
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 01/12] drm/i915: Reference objects on the ww object list Thomas Hellström
2021-06-17 19:13 ` Daniel Vetter
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 02/12] drm/i915: Break out dma_resv ww locking utilities to separate files Thomas Hellström
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 03/12] drm/i915: Introduce a ww transaction helper Thomas Hellström
2021-06-17 6:30 ` Thomas Hellström [this message]
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 05/12] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT Thomas Hellström
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 06/12] drm/i915/gt: Export the pinned context constructor and destructor Thomas Hellström
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 07/12] drm/i915/gt: Pipelined page migration Thomas Hellström
2021-08-05 10:05 ` Daniel Vetter
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 08/12] drm/i915/gt: Pipelined clear Thomas Hellström
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 09/12] drm/i915/gt: Setup a default migration context on the GT Thomas Hellström
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 10/12] drm/i915/ttm: accelerated move implementation Thomas Hellström
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 11/12] drm/i915/gem: Zap the client blt code Thomas Hellström
2021-06-17 6:30 ` [Intel-gfx] [PATCH v5 12/12] drm/i915/gem: Zap the i915_gem_object_blt code Thomas Hellström
2021-06-17 6:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915 TTM sync accelerated migration and clear (rev4) Patchwork
2021-06-17 7:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-17 8:30 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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