[Intel-gfx] [PATCH 0/7] More workaround updates

[Intel-gfx] [PATCH 0/7] More workaround updates

[Matt Roper]

The first six patches are just general maintenance of workarounds for
various platforms.  The final patch switches the way we match ranges of
steppings in the driver from an inclusive upper bound to an exclusive
upper bound; this matches how workarounds are defined in our specs and
should help reduce simple mistakes going forward.

Matt Roper (7):
  drm/i915: Fix application of WaInPlaceDecompressionHang
  drm/i915/icl: Drop a couple unnecessary workarounds
  drm/i915: Program DFR enable/disable as a GT workaround
  drm/i915/adl_s: Wa_14011765242 is also needed on A1 display stepping
  drm/i915/rkl: Wa_1409767108 also applies to RKL
  drm/i915/rkl: Wa_1408330847 no longer applies to RKL
  drm/i915: Make workaround upper bounds exclusive

 drivers/gpu/drm/i915/display/intel_cdclk.c    |  2 +-
 .../drm/i915/display/intel_display_power.c    |  5 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 24 +++----
 .../drm/i915/display/skl_universal_plane.c    |  8 +--
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  2 +-
 drivers/gpu/drm/i915/gt/intel_region_lmem.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 69 +++++++------------
 drivers/gpu/drm/i915/i915_drv.h               |  4 +-
 drivers/gpu/drm/i915/intel_device_info.c      |  4 +-
 drivers/gpu/drm/i915/intel_pm.c               | 16 ++---
 drivers/gpu/drm/i915/intel_step.h             |  1 +
 11 files changed, 55 insertions(+), 82 deletions(-)

-- 
2.25.4

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[Intel-gfx] [PATCH 1/7] drm/i915: Fix application of WaInPlaceDecompressionHang

[Matt Roper]

On SKL we've been applying this workaround on H0+ steppings, which is
actually backwards; H0 is supposed to be the first stepping where the
workaround is no longer needed.  Flip the bounds so that the workaround
applies to all steppings _before_ H0.

On BXT we've been applying this workaround to all steppings, but the
bspec tells us it's only needed until C0.  Pre-C0 GT steppings only
appeared in pre-production hardware, which we no longer support in the
driver, so we can drop the workaround completely for this platform.

On ICL we've been applying this workaround to all steppings, but there
doesn't seem to be any indication that this workaround was ever needed
for this platform (even now-deprecated page 20196 of the bspec doesn't
mention it).  We can go ahead and drop it.

I also don't see any mention of this workaround being needed for KBL,
although this may be an oversight since the workaround is needed for all
steppings of CFL.  I'll leave the workaround in place for KBL to be
safe.

Bspec: 14091, 33450
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++------------------
 1 file changed, 2 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 7731db33c46a..76a3b5d5e9dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -838,23 +838,12 @@ skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaInPlaceDecompressionHang:skl */
-	if (IS_SKL_GT_STEP(i915, STEP_H0, STEP_FOREVER))
+	if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0 - 1))
 		wa_write_or(wal,
 			    GEN9_GAMT_ECO_REG_RW_IA,
 			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 }
 
-static void
-bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
-{
-	gen9_gt_workarounds_init(i915, wal);
-
-	/* WaInPlaceDecompressionHang:bxt */
-	wa_write_or(wal,
-		    GEN9_GAMT_ECO_REG_RW_IA,
-		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-}
-
 static void
 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
@@ -942,11 +931,6 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
 	icl_wa_init_mcr(i915, wal);
 
-	/* WaInPlaceDecompressionHang:icl */
-	wa_write_or(wal,
-		    GEN9_GAMT_ECO_REG_RW_IA,
-		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-
 	/* WaModifyGamTlbPartitioning:icl */
 	wa_write_clr_set(wal,
 			 GEN11_GACB_PERF_CTRL,
@@ -1081,7 +1065,7 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	else if (IS_KABYLAKE(i915))
 		kbl_gt_workarounds_init(i915, wal);
 	else if (IS_BROXTON(i915))
-		bxt_gt_workarounds_init(i915, wal);
+		gen9_gt_workarounds_init(i915, wal);
 	else if (IS_SKYLAKE(i915))
 		skl_gt_workarounds_init(i915, wal);
 	else if (IS_HASWELL(i915))
-- 
2.25.4

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Re: [Intel-gfx] [PATCH 1/7] drm/i915: Fix application of WaInPlaceDecompressionHang

[Souza, Jose]

On Fri, 2021-07-16 at 22:14 -0700, Matt Roper wrote:
> On SKL we've been applying this workaround on H0+ steppings, which is
> actually backwards; H0 is supposed to be the first stepping where the
> workaround is no longer needed.  Flip the bounds so that the workaround
> applies to all steppings _before_ H0.
> 
> On BXT we've been applying this workaround to all steppings, but the
> bspec tells us it's only needed until C0.  Pre-C0 GT steppings only
> appeared in pre-production hardware, which we no longer support in the
> driver, so we can drop the workaround completely for this platform.
> 
> On ICL we've been applying this workaround to all steppings, but there
> doesn't seem to be any indication that this workaround was ever needed
> for this platform (even now-deprecated page 20196 of the bspec doesn't
> mention it).  We can go ahead and drop it.
> 
> I also don't see any mention of this workaround being needed for KBL,
> although this may be an oversight since the workaround is needed for all
> steppings of CFL.  I'll leave the workaround in place for KBL to be
> safe.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Bspec: 14091, 33450
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++------------------
>  1 file changed, 2 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 7731db33c46a..76a3b5d5e9dc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -838,23 +838,12 @@ skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
>  
>  	/* WaInPlaceDecompressionHang:skl */
> -	if (IS_SKL_GT_STEP(i915, STEP_H0, STEP_FOREVER))
> +	if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0 - 1))
>  		wa_write_or(wal,
>  			    GEN9_GAMT_ECO_REG_RW_IA,
>  			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
>  }
>  
> -static void
> -bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> -{
> -	gen9_gt_workarounds_init(i915, wal);
> -
> -	/* WaInPlaceDecompressionHang:bxt */
> -	wa_write_or(wal,
> -		    GEN9_GAMT_ECO_REG_RW_IA,
> -		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> -}
> -
>  static void
>  kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  {
> @@ -942,11 +931,6 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  {
>  	icl_wa_init_mcr(i915, wal);
>  
> -	/* WaInPlaceDecompressionHang:icl */
> -	wa_write_or(wal,
> -		    GEN9_GAMT_ECO_REG_RW_IA,
> -		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> -
>  	/* WaModifyGamTlbPartitioning:icl */
>  	wa_write_clr_set(wal,
>  			 GEN11_GACB_PERF_CTRL,
> @@ -1081,7 +1065,7 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  	else if (IS_KABYLAKE(i915))
>  		kbl_gt_workarounds_init(i915, wal);
>  	else if (IS_BROXTON(i915))
> -		bxt_gt_workarounds_init(i915, wal);
> +		gen9_gt_workarounds_init(i915, wal);
>  	else if (IS_SKYLAKE(i915))
>  		skl_gt_workarounds_init(i915, wal);
>  	else if (IS_HASWELL(i915))

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[Intel-gfx] [PATCH 2/7] drm/i915/icl: Drop a couple unnecessary workarounds

[Matt Roper]

While doing a quick sanity check of the ICL workarounds in the driver I
noticed a few things that should be updated:

 * There's no mention in the bspec that WaPipelineFlushCoherentLines
   is needed on gen11 (both the current WA database and the old,
   deprecated page 20196 were checked); it appears this might have just
   been copied from the gen9 list?  Even if this were needed, it doesn't
   seem like this was the correct implementation anyway since the gen9
   workaround is supposed to be implemented in the indirect context bb
   (as we do in gen8_emit_flush_coherentl3_wa() on gen8/gen9).

 * WaForwardProgressSoftReset does not appear in the current workaround
   database.  The old deprecated workaround list has a note indicating
   the workaround was dropped in 2017, so we should be safe to drop it
   from the code too.

While we're at it, add the formal workaround ID number to
WaDisableBankHangMode (our hardware team made a transition from
text-based workaround names to ID numbers partway through the
development of ICL, which is why some workarounds only have names, some
only have numbers, and some have both).

Bspec: 33450
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 76a3b5d5e9dc..36d972492883 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -517,7 +517,7 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
-	/* WaDisableBankHangMode:icl */
+	/* Wa_1406697149 (WaDisableBankHangMode:icl) */
 	wa_write(wal,
 		 GEN8_L3CNTLREG,
 		 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
@@ -1587,11 +1587,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			     _3D_CHICKEN3,
 			     _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
 
-		/* WaPipelineFlushCoherentLines:icl */
-		wa_write_or(wal,
-			    GEN8_L3SQCREG4,
-			    GEN8_LQSC_FLUSH_COHERENT_LINES);
-
 		/*
 		 * Wa_1405543622:icl
 		 * Formerly known as WaGAPZPriorityScheme
@@ -1621,13 +1616,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN8_L3SQCREG4,
 			    GEN11_LQSC_CLEAN_EVICT_DISABLE);
 
-		/* WaForwardProgressSoftReset:icl */
-		wa_write_or(wal,
-			    GEN10_SCRATCH_LNCF2,
-			    PMFLUSHDONE_LNICRSDROP |
-			    PMFLUSH_GAPL3UNBLOCK |
-			    PMFLUSHDONE_LNEBLK);
-
 		/* Wa_1606682166:icl */
 		wa_write_or(wal,
 			    GEN7_SARCHKMD,
-- 
2.25.4

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Re: [Intel-gfx] [PATCH 2/7] drm/i915/icl: Drop a couple unnecessary workarounds

[Souza, Jose]

On Fri, 2021-07-16 at 22:14 -0700, Matt Roper wrote:
> While doing a quick sanity check of the ICL workarounds in the driver I
> noticed a few things that should be updated:
> 
>  * There's no mention in the bspec that WaPipelineFlushCoherentLines
>    is needed on gen11 (both the current WA database and the old,
>    deprecated page 20196 were checked); it appears this might have just
>    been copied from the gen9 list?  Even if this were needed, it doesn't
>    seem like this was the correct implementation anyway since the gen9
>    workaround is supposed to be implemented in the indirect context bb
>    (as we do in gen8_emit_flush_coherentl3_wa() on gen8/gen9).
> 
>  * WaForwardProgressSoftReset does not appear in the current workaround
>    database.  The old deprecated workaround list has a note indicating
>    the workaround was dropped in 2017, so we should be safe to drop it
>    from the code too.
> 
> While we're at it, add the formal workaround ID number to
> WaDisableBankHangMode (our hardware team made a transition from
> text-based workaround names to ID numbers partway through the
> development of ICL, which is why some workarounds only have names, some
> only have numbers, and some have both).

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Bspec: 33450
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 +-------------
>  1 file changed, 1 insertion(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 76a3b5d5e9dc..36d972492883 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -517,7 +517,7 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  				     struct i915_wa_list *wal)
>  {
> -	/* WaDisableBankHangMode:icl */
> +	/* Wa_1406697149 (WaDisableBankHangMode:icl) */
>  	wa_write(wal,
>  		 GEN8_L3CNTLREG,
>  		 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
> @@ -1587,11 +1587,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  			     _3D_CHICKEN3,
>  			     _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
>  
> -		/* WaPipelineFlushCoherentLines:icl */
> -		wa_write_or(wal,
> -			    GEN8_L3SQCREG4,
> -			    GEN8_LQSC_FLUSH_COHERENT_LINES);
> -
>  		/*
>  		 * Wa_1405543622:icl
>  		 * Formerly known as WaGAPZPriorityScheme
> @@ -1621,13 +1616,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  			    GEN8_L3SQCREG4,
>  			    GEN11_LQSC_CLEAN_EVICT_DISABLE);
>  
> -		/* WaForwardProgressSoftReset:icl */
> -		wa_write_or(wal,
> -			    GEN10_SCRATCH_LNCF2,
> -			    PMFLUSHDONE_LNICRSDROP |
> -			    PMFLUSH_GAPL3UNBLOCK |
> -			    PMFLUSHDONE_LNEBLK);
> -
>  		/* Wa_1606682166:icl */
>  		wa_write_or(wal,
>  			    GEN7_SARCHKMD,

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[Intel-gfx] [PATCH 3/7] drm/i915: Program DFR enable/disable as a GT workaround

[Matt Roper]

DFR programming (which we enable as an optimization on gen11, but must
ensure is disabled on gen12) should be handled as a GT workaround rather
than clock gating initialization.  This will ensure that the programming
of these registers is verified with our typical workaround checks.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
 drivers/gpu/drm/i915/intel_pm.c             | 8 --------
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 36d972492883..685c6115d380 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -965,6 +965,12 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+
+	/*
+	 * This is not a documented workaround, but rather an optimization
+	 * to reduce sampler power.
+	 */
+	wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
 }
 
 /*
@@ -998,6 +1004,9 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
 
 	/* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */
 	wa_14011060649(i915, wal);
+
+	/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
+	wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef5304d3c2ec..8a84abfaa4b0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7345,10 +7345,6 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
 		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
-	/* This is not an Wa. Enable to reduce Sampler power */
-	intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
-		   intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
-
 	/*Wa_14010594013:icl, ehl */
 	intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
 			 0, CNL_DELAY_PMRSP);
@@ -7367,10 +7363,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
 		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   TGL_VRH_GATING_DIS);
 
-	/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
-	intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
-			 0, DFR_DISABLE);
-
 	/* Wa_14013723622:tgl,rkl,dg1,adl-s */
 	if (DISPLAY_VER(dev_priv) == 12)
 		intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
-- 
2.25.4

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Re: [Intel-gfx] [PATCH 3/7] drm/i915: Program DFR enable/disable as a GT workaround

[Souza, Jose]

On Fri, 2021-07-16 at 22:14 -0700, Matt Roper wrote:
> DFR programming (which we enable as an optimization on gen11, but must
> ensure is disabled on gen12) should be handled as a GT workaround rather
> than clock gating initialization.  This will ensure that the programming
> of these registers is verified with our typical workaround checks.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
>  drivers/gpu/drm/i915/intel_pm.c             | 8 --------
>  2 files changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 36d972492883..685c6115d380 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -965,6 +965,12 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> +
> +	/*
> +	 * This is not a documented workaround, but rather an optimization
> +	 * to reduce sampler power.
> +	 */
> +	wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
>  }
>  
>  /*
> @@ -998,6 +1004,9 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
>  
>  	/* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */
>  	wa_14011060649(i915, wal);
> +
> +	/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
> +	wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ef5304d3c2ec..8a84abfaa4b0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7345,10 +7345,6 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
>  	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>  
> -	/* This is not an Wa. Enable to reduce Sampler power */
> -	intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
> -		   intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
> -
>  	/*Wa_14010594013:icl, ehl */
>  	intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
>  			 0, CNL_DELAY_PMRSP);
> @@ -7367,10 +7363,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>  			   TGL_VRH_GATING_DIS);
>  
> -	/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
> -	intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
> -			 0, DFR_DISABLE);
> -
>  	/* Wa_14013723622:tgl,rkl,dg1,adl-s */
>  	if (DISPLAY_VER(dev_priv) == 12)
>  		intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,

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[Intel-gfx] [PATCH 4/7] drm/i915/adl_s: Wa_14011765242 is also needed on A1 display stepping

[Matt Roper]

Extend the workaround bound to include A1 display.

Bspec: 54370
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
 drivers/gpu/drm/i915/intel_step.h        | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d2a514d2551d..dd63dd2c45ad 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -261,8 +261,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 	enum pipe pipe;
 
-	/* Wa_14011765242: adl-s A0 */
-	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+	/* Wa_14011765242: adl-s A0,A1 */
+	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A1))
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_scalers[pipe] = 0;
 	else if (GRAPHICS_VER(dev_priv) >= 10) {
diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h
index 88a77159703e..41567d9b7c35 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -22,6 +22,7 @@ struct intel_step_info {
 enum intel_step {
 	STEP_NONE = 0,
 	STEP_A0,
+	STEP_A1,
 	STEP_A2,
 	STEP_B0,
 	STEP_B1,
-- 
2.25.4

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Re: [Intel-gfx] [PATCH 4/7] drm/i915/adl_s: Wa_14011765242 is also needed on A1 display stepping

[Souza, Jose]

On Fri, 2021-07-16 at 22:14 -0700, Matt Roper wrote:
> Extend the workaround bound to include A1 display.
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Bspec: 54370
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
>  drivers/gpu/drm/i915/intel_step.h        | 1 +
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index d2a514d2551d..dd63dd2c45ad 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -261,8 +261,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
>  	enum pipe pipe;
>  
> -	/* Wa_14011765242: adl-s A0 */
> -	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> +	/* Wa_14011765242: adl-s A0,A1 */
> +	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A1))
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_scalers[pipe] = 0;
>  	else if (GRAPHICS_VER(dev_priv) >= 10) {
> diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h
> index 88a77159703e..41567d9b7c35 100644
> --- a/drivers/gpu/drm/i915/intel_step.h
> +++ b/drivers/gpu/drm/i915/intel_step.h
> @@ -22,6 +22,7 @@ struct intel_step_info {
>  enum intel_step {
>  	STEP_NONE = 0,
>  	STEP_A0,
> +	STEP_A1,
>  	STEP_A2,
>  	STEP_B0,
>  	STEP_B1,

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[Intel-gfx] [PATCH 5/7] drm/i915/rkl: Wa_1409767108 also applies to RKL

[Matt Roper]

Bspec: 53273
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 64be896bcd8b..e3aaf9678b07 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5800,8 +5800,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 
 	if (IS_ALDERLAKE_S(dev_priv) ||
 	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
+	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
 	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
-		/* Wa_1409767108:tgl,dg1,adl-s */
+		/* Wa_1409767108:tgl,rkl,dg1,adl-s */
 		table = wa_1409767108_buddy_page_masks;
 	else
 		table = tgl_buddy_page_masks;
-- 
2.25.4

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Re: [Intel-gfx] [PATCH 5/7] drm/i915/rkl: Wa_1409767108 also applies to RKL

[Souza, Jose]

On Fri, 2021-07-16 at 22:14 -0700, Matt Roper wrote:

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Bspec: 53273
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 64be896bcd8b..e3aaf9678b07 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5800,8 +5800,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>  
>  	if (IS_ALDERLAKE_S(dev_priv) ||
>  	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> +	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
>  	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> -		/* Wa_1409767108:tgl,dg1,adl-s */
> +		/* Wa_1409767108:tgl,rkl,dg1,adl-s */
>  		table = wa_1409767108_buddy_page_masks;
>  	else
>  		table = tgl_buddy_page_masks;

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[Intel-gfx] [PATCH 6/7] drm/i915/rkl: Wa_1408330847 no longer applies to RKL

[Matt Roper]

RKL doesn't have PSR2 support, so PSR2-related workarounds no longer
apply.

Bspec: 53273
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d436490ab28c..0a3d42c8d47d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -592,9 +592,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 		val |= EDP_PSR2_SU_SDP_SCANLINE;
 
 	if (intel_dp->psr.psr2_sel_fetch_enabled) {
-		/* WA 1408330847 */
-		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-		    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+		/* Wa_1408330847 */
+		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
 			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
 				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
@@ -1339,10 +1338,9 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 	intel_psr_exit(intel_dp);
 	intel_psr_wait_exit_locked(intel_dp);
 
-	/* WA 1408330847 */
+	/* Wa_1408330847 */
 	if (intel_dp->psr.psr2_sel_fetch_enabled &&
-	    (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-	     IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
+	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
 
-- 
2.25.4

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Re: [Intel-gfx] [PATCH 6/7] drm/i915/rkl: Wa_1408330847 no longer applies to RKL

[Souza, Jose]

On Fri, 2021-07-16 at 22:14 -0700, Matt Roper wrote:
> RKL doesn't have PSR2 support, so PSR2-related workarounds no longer
> apply.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Bspec: 53273
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index d436490ab28c..0a3d42c8d47d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -592,9 +592,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  		val |= EDP_PSR2_SU_SDP_SCANLINE;
>  
>  	if (intel_dp->psr.psr2_sel_fetch_enabled) {
> -		/* WA 1408330847 */
> -		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> -		    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> +		/* Wa_1408330847 */
> +		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> @@ -1339,10 +1338,9 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  	intel_psr_exit(intel_dp);
>  	intel_psr_wait_exit_locked(intel_dp);
>  
> -	/* WA 1408330847 */
> +	/* Wa_1408330847 */
>  	if (intel_dp->psr.psr2_sel_fetch_enabled &&
> -	    (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> -	     IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
> +	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>  

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[Intel-gfx] [PATCH 7/7] drm/i915: Make workaround upper bounds exclusive

[Matt Roper]

Workarounds are documented in the bspec with an exclusive upper bound
(i.e., a "fixed" stepping that no longer needs the workaround).  This
makes our driver's use of an inclusive upper bound for stepping ranges
confusing; the differing notation between code and bspec makes it very
easy for mistakes to creep in.

Let's switch the upper bound of our IS_{GT,DISP}_STEP macros over to use
an exclusive upper bound like the bspec does.  This also has the benefit
of helping make sure workarounds are properly handled for new minor
steppings that show up (e.g., an A1 between the A0 and B0 we already
knew about) --- if the new intermediate stepping pulls in hardware fixes
early, there will be an update to the workaround definition which lets
us know we need to change our code.  If the new stepping does not pull a
hardware fix earlier, then the new stepping will already be captured
properly by the "[begin, fix)" range in the code.

We'll probably need to be extra vigilant in code review of new
workarounds for the near future to make sure developers notice the new
semantics of workaround bounds.  But we just migrated a bunch of our
platforms from the IS_REVID bounds over to IS_{GT,DISP}_STEP, so people
are already adjusting to the new macros and now is a good time to make
this change too.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  2 +-
 .../drm/i915/display/intel_display_power.c    |  8 +++---
 drivers/gpu/drm/i915/display/intel_psr.c      | 18 ++++++------
 .../drm/i915/display/skl_universal_plane.c    |  8 +++---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  2 +-
 drivers/gpu/drm/i915/gt/intel_region_lmem.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 28 +++++++++----------
 drivers/gpu/drm/i915/i915_drv.h               |  4 +--
 drivers/gpu/drm/i915/intel_device_info.c      |  2 +-
 drivers/gpu/drm/i915/intel_pm.c               |  8 +++---
 10 files changed, 41 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 71067a62264d..944fb13b9d98 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2879,7 +2879,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
 		/* Wa_22011320316:adl-p[a0] */
-		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			dev_priv->cdclk.table = adlp_a_step_cdclk_table;
 		else
 			dev_priv->cdclk.table = adlp_cdclk_table;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e3aaf9678b07..bec380e58f40 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5799,10 +5799,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	int config, i;
 
 	if (IS_ALDERLAKE_S(dev_priv) ||
-	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
-		/* Wa_1409767108:tgl,rkl,dg1,adl-s */
+	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
+		/* Wa_1409767108:tgl,dg1,adl-s */
 		table = wa_1409767108_buddy_page_masks;
 	else
 		table = tgl_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 0a3d42c8d47d..f0381edefded 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -546,7 +546,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	val |= intel_psr2_get_tp_time(intel_dp);
 
 	/* Wa_22012278275:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
+	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
 		static const u8 map[] = {
 			2, /* 5 lines */
 			1, /* 6 lines */
@@ -593,7 +593,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	if (intel_dp->psr.psr2_sel_fetch_enabled) {
 		/* Wa_1408330847 */
-		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
 				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
@@ -733,7 +733,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 		return;
 
 	/* Wa_16011303918:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		return;
 
 	/*
@@ -780,7 +780,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 	}
 
 	/* Wa_14010254185 Wa_14010103792 */
-	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
+	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
 		return false;
@@ -939,7 +939,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 
 	/* Wa_2209313811 */
 	if (!crtc_state->enable_psr2_sel_fetch &&
-	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
+	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
 		drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
 		return false;
 	}
@@ -966,7 +966,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 
 	/* Wa_16011303918:adl-p */
 	if (crtc_state->vrr.enable &&
-	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) {
+	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");
 		return false;
@@ -1160,7 +1160,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
 			     IGNORE_PSR2_HW_TRACKING : 0);
 
 	/* Wa_16011168373:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
+	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
 	    intel_dp->psr.psr2_enabled)
 		intel_de_rmw(dev_priv,
 			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
@@ -1340,12 +1340,12 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	/* Wa_1408330847 */
 	if (intel_dp->psr.psr2_sel_fetch_enabled &&
-	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
 
 	/* Wa_16011168373:adl-p */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
+	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
 	    intel_dp->psr.psr2_enabled)
 		intel_de_rmw(dev_priv,
 			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 628b678d9a71..3ad04bf2a0fd 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1910,11 +1910,11 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
 {
 	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
 	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
-	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
+	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0))
 		return false;
 
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		return false;
 
 	return plane_id < PLANE_SPRITE4;
@@ -1938,7 +1938,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		/* Wa_22011186057 */
-		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			return false;
 		break;
 	default:
@@ -1995,7 +1995,7 @@ static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
 					    enum plane_id plane_id)
 {
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		return adlp_step_a_plane_format_modifiers;
 	else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
 		return gen12_plane_format_modifiers_mc_ccs;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 87b06572fd2e..a69f5c438c72 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
 			vf_flush_wa = true;
 
 		/* WaForGAMHang:kbl */
-		if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_B0))
+		if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_C0))
 			dc_flush_wa = true;
 	}
 
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 50d11a84e7a9..e3a2a2fa5f94 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
 static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
 				     u64 *start, u32 *size)
 {
-	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
+	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_C0))
 		return false;
 
 	*start = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 685c6115d380..247f0331ebee 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -838,7 +838,7 @@ skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaInPlaceDecompressionHang:skl */
-	if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0 - 1))
+	if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0))
 		wa_write_or(wal,
 			    GEN9_GAMT_ECO_REG_RW_IA,
 			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
@@ -850,7 +850,7 @@ kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	gen9_gt_workarounds_init(i915, wal);
 
 	/* WaDisableDynamicCreditSharing:kbl */
-	if (IS_KBL_GT_STEP(i915, 0, STEP_B0))
+	if (IS_KBL_GT_STEP(i915, 0, STEP_C0))
 		wa_write_or(wal,
 			    GAMT_CHKN_BIT_REG,
 			    GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
@@ -961,7 +961,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 
 	/* Wa_1607087056:icl,ehl,jsl */
 	if (IS_ICELAKE(i915) ||
-	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
+	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_B0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1015,19 +1015,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	gen12_gt_workarounds_init(i915, wal);
 
 	/* Wa_1409420604:tgl */
-	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
+	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
 		wa_write_or(wal,
 			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
 			    CPSSUNIT_CLKGATE_DIS);
 
 	/* Wa_1607087056:tgl also know as BUG:1409180338 */
-	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
+	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 
 	/* Wa_1408615072:tgl[a0] */
-	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
+	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
 		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
 			    VSUNIT_CLKGATE_DIS_TGL);
 }
@@ -1038,7 +1038,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	gen12_gt_workarounds_init(i915, wal);
 
 	/* Wa_1607087056:dg1 */
-	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
+	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1436,7 +1436,7 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
 	tgl_whitelist_build(engine);
 
 	/* GEN:BUG:1409280441:dg1 */
-	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
+	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_B0) &&
 	    (engine->class == RENDER_CLASS ||
 	     engine->class == COPY_ENGINE_CLASS))
 		whitelist_reg_ext(w, RING_ID(engine->mmio_base),
@@ -1504,8 +1504,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
-	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
+	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
+	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) {
 		/*
 		 * Wa_1607138336:tgl[a0],dg1[a0]
 		 * Wa_1607063988:tgl[a0],dg1[a0]
@@ -1515,7 +1515,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
 	}
 
-	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
+	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) {
 		/*
 		 * Wa_1606679103:tgl
 		 * (see also Wa_1606682166:icl)
@@ -1550,7 +1550,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	}
 
 	if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
-	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
+	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
 		/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
@@ -1564,7 +1564,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	}
 
 
-	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
+	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
 	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
 		/*
 		 * Wa_1607030317:tgl
@@ -1925,7 +1925,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	struct drm_i915_private *i915 = engine->i915;
 
 	/* WaKBLVECSSemaphoreWaitPoll:kbl */
-	if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_E0)) {
+	if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_F0)) {
 		wa_write(wal,
 			 RING_SEMA_WAIT_POLL(engine->mmio_base),
 			 1);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index da5f230e2d4b..b42405afb28e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1332,11 +1332,11 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 
 #define IS_DISPLAY_STEP(__i915, since, until) \
 	(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
-	 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
+	 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
 
 #define IS_GT_STEP(__i915, since, until) \
 	(drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
-	 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
+	 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) < (until))
 
 static __always_inline unsigned int
 __platform_mask_index(const struct intel_runtime_info *info,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index dd63dd2c45ad..5c83b2ec69da 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -262,7 +262,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	enum pipe pipe;
 
 	/* Wa_14011765242: adl-s A0,A1 */
-	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A1))
+	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_scalers[pipe] = 0;
 	else if (GRAPHICS_VER(dev_priv) >= 10) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8a84abfaa4b0..597383430ca6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7359,7 +7359,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
 				   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
 	/* Wa_1409825376:tgl (pre-prod)*/
-	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1))
+	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
 		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   TGL_VRH_GATING_DIS);
 
@@ -7382,7 +7382,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
 	gen12lp_init_clock_gating(dev_priv);
 
 	/* Wa_1409836686:dg1[a0] */
-	if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0))
+	if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_B0))
 		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   DPT_GATING_DIS);
 }
@@ -7467,12 +7467,12 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 		   FBC_LLC_FULLY_OPEN);
 
 	/* WaDisableSDEUnitClockGating:kbl */
-	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
+	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
 		intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
 			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableGamClockGating:kbl */
-	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
+	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
 		intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
 			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Make workaround upper bounds exclusive

[Souza, Jose]

On Fri, 2021-07-16 at 22:14 -0700, Matt Roper wrote:
> Workarounds are documented in the bspec with an exclusive upper bound
> (i.e., a "fixed" stepping that no longer needs the workaround).  This
> makes our driver's use of an inclusive upper bound for stepping ranges
> confusing; the differing notation between code and bspec makes it very
> easy for mistakes to creep in.
> 
> Let's switch the upper bound of our IS_{GT,DISP}_STEP macros over to use
> an exclusive upper bound like the bspec does.  This also has the benefit
> of helping make sure workarounds are properly handled for new minor
> steppings that show up (e.g., an A1 between the A0 and B0 we already
> knew about) --- if the new intermediate stepping pulls in hardware fixes
> early, there will be an update to the workaround definition which lets
> us know we need to change our code.  If the new stepping does not pull a
> hardware fix earlier, then the new stepping will already be captured
> properly by the "[begin, fix)" range in the code.
> 
> We'll probably need to be extra vigilant in code review of new
> workarounds for the near future to make sure developers notice the new
> semantics of workaround bounds.  But we just migrated a bunch of our
> platforms from the IS_REVID bounds over to IS_{GT,DISP}_STEP, so people
> are already adjusting to the new macros and now is a good time to make
> this change too.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |  2 +-
>  .../drm/i915/display/intel_display_power.c    |  8 +++---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 18 ++++++------
>  .../drm/i915/display/skl_universal_plane.c    |  8 +++---
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  2 +-
>  drivers/gpu/drm/i915/gt/intel_region_lmem.c   |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 28 +++++++++----------
>  drivers/gpu/drm/i915/i915_drv.h               |  4 +--
>  drivers/gpu/drm/i915/intel_device_info.c      |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c               |  8 +++---
>  10 files changed, 41 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 71067a62264d..944fb13b9d98 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2879,7 +2879,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
>  		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
>  		/* Wa_22011320316:adl-p[a0] */
> -		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> +		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  			dev_priv->cdclk.table = adlp_a_step_cdclk_table;
>  		else
>  			dev_priv->cdclk.table = adlp_cdclk_table;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index e3aaf9678b07..bec380e58f40 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5799,10 +5799,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>  	int config, i;
>  
>  	if (IS_ALDERLAKE_S(dev_priv) ||
> -	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> -	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> -	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> -		/* Wa_1409767108:tgl,rkl,dg1,adl-s */
> +	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> +		/* Wa_1409767108:tgl,dg1,adl-s */
>  		table = wa_1409767108_buddy_page_masks;
>  	else
>  		table = tgl_buddy_page_masks;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 0a3d42c8d47d..f0381edefded 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -546,7 +546,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	val |= intel_psr2_get_tp_time(intel_dp);
>  
>  	/* Wa_22012278275:adl-p */
> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
>  		static const u8 map[] = {
>  			2, /* 5 lines */
>  			1, /* 6 lines */
> @@ -593,7 +593,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	if (intel_dp->psr.psr2_sel_fetch_enabled) {
>  		/* Wa_1408330847 */
> -		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> +		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> @@ -733,7 +733,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
>  		return;
>  
>  	/* Wa_16011303918:adl-p */
> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  		return;
>  
>  	/*
> @@ -780,7 +780,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>  	}
>  
>  	/* Wa_14010254185 Wa_14010103792 */
> -	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
> +	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
>  		return false;
> @@ -939,7 +939,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  
>  	/* Wa_2209313811 */
>  	if (!crtc_state->enable_psr2_sel_fetch &&
> -	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
> +	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
>  		drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
>  		return false;
>  	}
> @@ -966,7 +966,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  
>  	/* Wa_16011303918:adl-p */
>  	if (crtc_state->vrr.enable &&
> -	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) {
> +	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");
>  		return false;
> @@ -1160,7 +1160,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
>  			     IGNORE_PSR2_HW_TRACKING : 0);
>  
>  	/* Wa_16011168373:adl-p */
> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
>  	    intel_dp->psr.psr2_enabled)
>  		intel_de_rmw(dev_priv,
>  			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> @@ -1340,12 +1340,12 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  
>  	/* Wa_1408330847 */
>  	if (intel_dp->psr.psr2_sel_fetch_enabled &&
> -	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> +	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>  
>  	/* Wa_16011168373:adl-p */
> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
>  	    intel_dp->psr.psr2_enabled)
>  		intel_de_rmw(dev_priv,
>  			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 628b678d9a71..3ad04bf2a0fd 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1910,11 +1910,11 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>  {
>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> -	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> +	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0))
>  		return false;
>  
>  	/* Wa_22011186057 */
> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  		return false;
>  
>  	return plane_id < PLANE_SPRITE4;
> @@ -1938,7 +1938,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		/* Wa_22011186057 */
> -		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> +		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  			return false;
>  		break;
>  	default:
> @@ -1995,7 +1995,7 @@ static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
>  					    enum plane_id plane_id)
>  {
>  	/* Wa_22011186057 */
> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  		return adlp_step_a_plane_format_modifiers;
>  	else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
>  		return gen12_plane_format_modifiers_mc_ccs;
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 87b06572fd2e..a69f5c438c72 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
>  			vf_flush_wa = true;
>  
>  		/* WaForGAMHang:kbl */
> -		if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_B0))
> +		if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_C0))
>  			dc_flush_wa = true;
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 50d11a84e7a9..e3a2a2fa5f94 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
>  static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
>  				     u64 *start, u32 *size)
>  {
> -	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
> +	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_C0))
>  		return false;
>  
>  	*start = 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 685c6115d380..247f0331ebee 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -838,7 +838,7 @@ skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
>  
>  	/* WaInPlaceDecompressionHang:skl */
> -	if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0 - 1))
> +	if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0))
>  		wa_write_or(wal,
>  			    GEN9_GAMT_ECO_REG_RW_IA,
>  			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> @@ -850,7 +850,7 @@ kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  	gen9_gt_workarounds_init(i915, wal);
>  
>  	/* WaDisableDynamicCreditSharing:kbl */
> -	if (IS_KBL_GT_STEP(i915, 0, STEP_B0))
> +	if (IS_KBL_GT_STEP(i915, 0, STEP_C0))
>  		wa_write_or(wal,
>  			    GAMT_CHKN_BIT_REG,
>  			    GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
> @@ -961,7 +961,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  
>  	/* Wa_1607087056:icl,ehl,jsl */
>  	if (IS_ICELAKE(i915) ||
> -	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
> +	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_B0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> @@ -1015,19 +1015,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  	gen12_gt_workarounds_init(i915, wal);
>  
>  	/* Wa_1409420604:tgl */
> -	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
> +	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
>  		wa_write_or(wal,
>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>  			    CPSSUNIT_CLKGATE_DIS);
>  
>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
> -	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
> +	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>  
>  	/* Wa_1408615072:tgl[a0] */
> -	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
> +	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>  			    VSUNIT_CLKGATE_DIS_TGL);
>  }
> @@ -1038,7 +1038,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  	gen12_gt_workarounds_init(i915, wal);
>  
>  	/* Wa_1607087056:dg1 */
> -	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> @@ -1436,7 +1436,7 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
>  	tgl_whitelist_build(engine);
>  
>  	/* GEN:BUG:1409280441:dg1 */
> -	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
> +	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_B0) &&
>  	    (engine->class == RENDER_CLASS ||
>  	     engine->class == COPY_ENGINE_CLASS))
>  		whitelist_reg_ext(w, RING_ID(engine->mmio_base),
> @@ -1504,8 +1504,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  {
>  	struct drm_i915_private *i915 = engine->i915;
>  
> -	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
> -	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
> +	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) {
>  		/*
>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>  		 * Wa_1607063988:tgl[a0],dg1[a0]
> @@ -1515,7 +1515,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>  	}
>  
> -	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
> +	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) {
>  		/*
>  		 * Wa_1606679103:tgl
>  		 * (see also Wa_1606682166:icl)
> @@ -1550,7 +1550,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  	}
>  
>  	if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> -	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
> +	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
>  	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>  		/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
>  		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> @@ -1564,7 +1564,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  	}
>  
>  
> -	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
>  	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>  		/*
>  		 * Wa_1607030317:tgl
> @@ -1925,7 +1925,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  	struct drm_i915_private *i915 = engine->i915;
>  
>  	/* WaKBLVECSSemaphoreWaitPoll:kbl */
> -	if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_E0)) {
> +	if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_F0)) {
>  		wa_write(wal,
>  			 RING_SEMA_WAIT_POLL(engine->mmio_base),
>  			 1);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index da5f230e2d4b..b42405afb28e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1332,11 +1332,11 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
>  
>  #define IS_DISPLAY_STEP(__i915, since, until) \
>  	(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
> -	 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
> +	 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
>  
>  #define IS_GT_STEP(__i915, since, until) \
>  	(drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
> -	 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
> +	 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) < (until))

Would be nice to have some comment about bound in here.

Did not manually checked each workaround against bspec, only checked the old and new until values and it makes sense.
With the comment requested above:

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


>  
>  static __always_inline unsigned int
>  __platform_mask_index(const struct intel_runtime_info *info,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index dd63dd2c45ad..5c83b2ec69da 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -262,7 +262,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  	enum pipe pipe;
>  
>  	/* Wa_14011765242: adl-s A0,A1 */
> -	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A1))
> +	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_scalers[pipe] = 0;
>  	else if (GRAPHICS_VER(dev_priv) >= 10) {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8a84abfaa4b0..597383430ca6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7359,7 +7359,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
>  				   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>  
>  	/* Wa_1409825376:tgl (pre-prod)*/
> -	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1))
> +	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>  			   TGL_VRH_GATING_DIS);
>  
> @@ -7382,7 +7382,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
>  	gen12lp_init_clock_gating(dev_priv);
>  
>  	/* Wa_1409836686:dg1[a0] */
> -	if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0))
> +	if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_B0))
>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>  			   DPT_GATING_DIS);
>  }
> @@ -7467,12 +7467,12 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
>  		   FBC_LLC_FULLY_OPEN);
>  
>  	/* WaDisableSDEUnitClockGating:kbl */
> -	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
> +	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
>  		intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>  			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>  
>  	/* WaDisableGamClockGating:kbl */
> -	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
> +	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
>  		intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
>  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>  

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Make workaround upper bounds exclusive

[Jani Nikula]

On Mon, 19 Jul 2021, "Souza, Jose" <jose.souza@intel.com> wrote:
> On Fri, 2021-07-16 at 22:14 -0700, Matt Roper wrote:
>> Workarounds are documented in the bspec with an exclusive upper bound
>> (i.e., a "fixed" stepping that no longer needs the workaround).  This
>> makes our driver's use of an inclusive upper bound for stepping ranges
>> confusing; the differing notation between code and bspec makes it very
>> easy for mistakes to creep in.
>> 
>> Let's switch the upper bound of our IS_{GT,DISP}_STEP macros over to use
>> an exclusive upper bound like the bspec does.  This also has the benefit
>> of helping make sure workarounds are properly handled for new minor
>> steppings that show up (e.g., an A1 between the A0 and B0 we already
>> knew about) --- if the new intermediate stepping pulls in hardware fixes
>> early, there will be an update to the workaround definition which lets
>> us know we need to change our code.  If the new stepping does not pull a
>> hardware fix earlier, then the new stepping will already be captured
>> properly by the "[begin, fix)" range in the code.
>> 
>> We'll probably need to be extra vigilant in code review of new
>> workarounds for the near future to make sure developers notice the new
>> semantics of workaround bounds.  But we just migrated a bunch of our
>> platforms from the IS_REVID bounds over to IS_{GT,DISP}_STEP, so people
>> are already adjusting to the new macros and now is a good time to make
>> this change too.
>> 
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

It's been merged already, but I think this is a good example of a patch
where simple review is just not enough. Needs maintainers in Cc and acks
on top.

BR,
Jani.


>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c    |  2 +-
>>  .../drm/i915/display/intel_display_power.c    |  8 +++---
>>  drivers/gpu/drm/i915/display/intel_psr.c      | 18 ++++++------
>>  .../drm/i915/display/skl_universal_plane.c    |  8 +++---
>>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  2 +-
>>  drivers/gpu/drm/i915/gt/intel_region_lmem.c   |  2 +-
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 28 +++++++++----------
>>  drivers/gpu/drm/i915/i915_drv.h               |  4 +--
>>  drivers/gpu/drm/i915/intel_device_info.c      |  2 +-
>>  drivers/gpu/drm/i915/intel_pm.c               |  8 +++---
>>  10 files changed, 41 insertions(+), 41 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 71067a62264d..944fb13b9d98 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2879,7 +2879,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>>  		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
>>  		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
>>  		/* Wa_22011320316:adl-p[a0] */
>> -		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
>> +		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>  			dev_priv->cdclk.table = adlp_a_step_cdclk_table;
>>  		else
>>  			dev_priv->cdclk.table = adlp_cdclk_table;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index e3aaf9678b07..bec380e58f40 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -5799,10 +5799,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>>  	int config, i;
>>  
>>  	if (IS_ALDERLAKE_S(dev_priv) ||
>> -	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
>> -	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
>> -	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>> -		/* Wa_1409767108:tgl,rkl,dg1,adl-s */
>> +	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>> +	    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>> +	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
>> +		/* Wa_1409767108:tgl,dg1,adl-s */
>>  		table = wa_1409767108_buddy_page_masks;
>>  	else
>>  		table = tgl_buddy_page_masks;
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 0a3d42c8d47d..f0381edefded 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -546,7 +546,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>  	val |= intel_psr2_get_tp_time(intel_dp);
>>  
>>  	/* Wa_22012278275:adl-p */
>> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
>> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
>>  		static const u8 map[] = {
>>  			2, /* 5 lines */
>>  			1, /* 6 lines */
>> @@ -593,7 +593,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>  
>>  	if (intel_dp->psr.psr2_sel_fetch_enabled) {
>>  		/* Wa_1408330847 */
>> -		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
>> +		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
>> @@ -733,7 +733,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
>>  		return;
>>  
>>  	/* Wa_16011303918:adl-p */
>> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
>> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>  		return;
>>  
>>  	/*
>> @@ -780,7 +780,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>>  	}
>>  
>>  	/* Wa_14010254185 Wa_14010103792 */
>> -	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
>> +	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
>>  		drm_dbg_kms(&dev_priv->drm,
>>  			    "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
>>  		return false;
>> @@ -939,7 +939,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>>  
>>  	/* Wa_2209313811 */
>>  	if (!crtc_state->enable_psr2_sel_fetch &&
>> -	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
>> +	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
>>  		drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
>>  		return false;
>>  	}
>> @@ -966,7 +966,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>>  
>>  	/* Wa_16011303918:adl-p */
>>  	if (crtc_state->vrr.enable &&
>> -	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) {
>> +	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
>>  		drm_dbg_kms(&dev_priv->drm,
>>  			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");
>>  		return false;
>> @@ -1160,7 +1160,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
>>  			     IGNORE_PSR2_HW_TRACKING : 0);
>>  
>>  	/* Wa_16011168373:adl-p */
>> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
>> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
>>  	    intel_dp->psr.psr2_enabled)
>>  		intel_de_rmw(dev_priv,
>>  			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
>> @@ -1340,12 +1340,12 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>  
>>  	/* Wa_1408330847 */
>>  	if (intel_dp->psr.psr2_sel_fetch_enabled &&
>> -	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
>> +	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>>  
>>  	/* Wa_16011168373:adl-p */
>> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
>> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
>>  	    intel_dp->psr.psr2_enabled)
>>  		intel_de_rmw(dev_priv,
>>  			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> index 628b678d9a71..3ad04bf2a0fd 100644
>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> @@ -1910,11 +1910,11 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>>  {
>>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
>> -	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
>> +	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0))
>>  		return false;
>>  
>>  	/* Wa_22011186057 */
>> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
>> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>  		return false;
>>  
>>  	return plane_id < PLANE_SPRITE4;
>> @@ -1938,7 +1938,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>>  		/* Wa_22011186057 */
>> -		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
>> +		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>  			return false;
>>  		break;
>>  	default:
>> @@ -1995,7 +1995,7 @@ static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
>>  					    enum plane_id plane_id)
>>  {
>>  	/* Wa_22011186057 */
>> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
>> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>>  		return adlp_step_a_plane_format_modifiers;
>>  	else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
>>  		return gen12_plane_format_modifiers_mc_ccs;
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> index 87b06572fd2e..a69f5c438c72 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> @@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
>>  			vf_flush_wa = true;
>>  
>>  		/* WaForGAMHang:kbl */
>> -		if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_B0))
>> +		if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_C0))
>>  			dc_flush_wa = true;
>>  	}
>>  
>> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> index 50d11a84e7a9..e3a2a2fa5f94 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> @@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
>>  static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
>>  				     u64 *start, u32 *size)
>>  {
>> -	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
>> +	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_C0))
>>  		return false;
>>  
>>  	*start = 0;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 685c6115d380..247f0331ebee 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -838,7 +838,7 @@ skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>  		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/* WaInPlaceDecompressionHang:skl */
>> -	if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0 - 1))
>> +	if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0))
>>  		wa_write_or(wal,
>>  			    GEN9_GAMT_ECO_REG_RW_IA,
>>  			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
>> @@ -850,7 +850,7 @@ kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>  	gen9_gt_workarounds_init(i915, wal);
>>  
>>  	/* WaDisableDynamicCreditSharing:kbl */
>> -	if (IS_KBL_GT_STEP(i915, 0, STEP_B0))
>> +	if (IS_KBL_GT_STEP(i915, 0, STEP_C0))
>>  		wa_write_or(wal,
>>  			    GAMT_CHKN_BIT_REG,
>>  			    GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
>> @@ -961,7 +961,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>  
>>  	/* Wa_1607087056:icl,ehl,jsl */
>>  	if (IS_ICELAKE(i915) ||
>> -	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
>> +	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_B0))
>>  		wa_write_or(wal,
>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>> @@ -1015,19 +1015,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>  	gen12_gt_workarounds_init(i915, wal);
>>  
>>  	/* Wa_1409420604:tgl */
>> -	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
>> +	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
>>  		wa_write_or(wal,
>>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>>  			    CPSSUNIT_CLKGATE_DIS);
>>  
>>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
>> -	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
>> +	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
>>  		wa_write_or(wal,
>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>>  
>>  	/* Wa_1408615072:tgl[a0] */
>> -	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
>> +	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
>>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>>  			    VSUNIT_CLKGATE_DIS_TGL);
>>  }
>> @@ -1038,7 +1038,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>  	gen12_gt_workarounds_init(i915, wal);
>>  
>>  	/* Wa_1607087056:dg1 */
>> -	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
>> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0))
>>  		wa_write_or(wal,
>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>> @@ -1436,7 +1436,7 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
>>  	tgl_whitelist_build(engine);
>>  
>>  	/* GEN:BUG:1409280441:dg1 */
>> -	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
>> +	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_B0) &&
>>  	    (engine->class == RENDER_CLASS ||
>>  	     engine->class == COPY_ENGINE_CLASS))
>>  		whitelist_reg_ext(w, RING_ID(engine->mmio_base),
>> @@ -1504,8 +1504,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  {
>>  	struct drm_i915_private *i915 = engine->i915;
>>  
>> -	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
>> -	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
>> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
>> +	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) {
>>  		/*
>>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>>  		 * Wa_1607063988:tgl[a0],dg1[a0]
>> @@ -1515,7 +1515,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>>  	}
>>  
>> -	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
>> +	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) {
>>  		/*
>>  		 * Wa_1606679103:tgl
>>  		 * (see also Wa_1606682166:icl)
>> @@ -1550,7 +1550,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  	}
>>  
>>  	if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
>> -	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
>> +	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
>>  	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>>  		/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
>>  		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
>> @@ -1564,7 +1564,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  	}
>>  
>>  
>> -	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
>> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
>>  	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>>  		/*
>>  		 * Wa_1607030317:tgl
>> @@ -1925,7 +1925,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  	struct drm_i915_private *i915 = engine->i915;
>>  
>>  	/* WaKBLVECSSemaphoreWaitPoll:kbl */
>> -	if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_E0)) {
>> +	if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_F0)) {
>>  		wa_write(wal,
>>  			 RING_SEMA_WAIT_POLL(engine->mmio_base),
>>  			 1);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index da5f230e2d4b..b42405afb28e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1332,11 +1332,11 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
>>  
>>  #define IS_DISPLAY_STEP(__i915, since, until) \
>>  	(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
>> -	 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
>> +	 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
>>  
>>  #define IS_GT_STEP(__i915, since, until) \
>>  	(drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
>> -	 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
>> +	 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) < (until))
>
> Would be nice to have some comment about bound in here.
>
> Did not manually checked each workaround against bspec, only checked the old and new until values and it makes sense.
> With the comment requested above:
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
>
>>  
>>  static __always_inline unsigned int
>>  __platform_mask_index(const struct intel_runtime_info *info,
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index dd63dd2c45ad..5c83b2ec69da 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -262,7 +262,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>>  	enum pipe pipe;
>>  
>>  	/* Wa_14011765242: adl-s A0,A1 */
>> -	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A1))
>> +	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
>>  		for_each_pipe(dev_priv, pipe)
>>  			runtime->num_scalers[pipe] = 0;
>>  	else if (GRAPHICS_VER(dev_priv) >= 10) {
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 8a84abfaa4b0..597383430ca6 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7359,7 +7359,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
>>  				   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>>  
>>  	/* Wa_1409825376:tgl (pre-prod)*/
>> -	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1))
>> +	if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
>>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>>  			   TGL_VRH_GATING_DIS);
>>  
>> @@ -7382,7 +7382,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	gen12lp_init_clock_gating(dev_priv);
>>  
>>  	/* Wa_1409836686:dg1[a0] */
>> -	if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0))
>> +	if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_B0))
>>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>>  			   DPT_GATING_DIS);
>>  }
>> @@ -7467,12 +7467,12 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  		   FBC_LLC_FULLY_OPEN);
>>  
>>  	/* WaDisableSDEUnitClockGating:kbl */
>> -	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
>> +	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
>>  		intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>>  			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/* WaDisableGamClockGating:kbl */
>> -	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
>> +	if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
>>  		intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
>>  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>>  
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Make workaround upper bounds exclusive

[Vivi, Rodrigo]

On Tue, 2021-08-10 at 15:58 +0300, Jani Nikula wrote:
> On Mon, 19 Jul 2021, "Souza, Jose" <jose.souza@intel.com> wrote:
> > On Fri, 2021-07-16 at 22:14 -0700, Matt Roper wrote:
> > > Workarounds are documented in the bspec with an exclusive upper
> > > bound
> > > (i.e., a "fixed" stepping that no longer needs the workaround). 
> > > This
> > > makes our driver's use of an inclusive upper bound for stepping
> > > ranges
> > > confusing; the differing notation between code and bspec makes it
> > > very
> > > easy for mistakes to creep in.
> > > 
> > > Let's switch the upper bound of our IS_{GT,DISP}_STEP macros over
> > > to use
> > > an exclusive upper bound like the bspec does.  This also has the
> > > benefit
> > > of helping make sure workarounds are properly handled for new
> > > minor
> > > steppings that show up (e.g., an A1 between the A0 and B0 we
> > > already
> > > knew about) --- if the new intermediate stepping pulls in
> > > hardware fixes
> > > early, there will be an update to the workaround definition which
> > > lets
> > > us know we need to change our code.  If the new stepping does not
> > > pull a
> > > hardware fix earlier, then the new stepping will already be
> > > captured
> > > properly by the "[begin, fix)" range in the code.
> > > 
> > > We'll probably need to be extra vigilant in code review of new
> > > workarounds for the near future to make sure developers notice
> > > the new
> > > semantics of workaround bounds.  But we just migrated a bunch of
> > > our
> > > platforms from the IS_REVID bounds over to IS_{GT,DISP}_STEP, so
> > > people
> > > are already adjusting to the new macros and now is a good time to
> > > make
> > > this change too.
> > > 
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> 
> It's been merged already, but I think this is a good example of a
> patch
> where simple review is just not enough. Needs maintainers in Cc and
> acks
> on top.

I agree. But I like the approach of getting this aligned with all other
internal tools we have to track w/a.
late-acked-by me...

> 
> BR,
> Jani.
> 
> 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_cdclk.c    |  2 +-
> > >  .../drm/i915/display/intel_display_power.c    |  8 +++---
> > >  drivers/gpu/drm/i915/display/intel_psr.c      | 18 ++++++------
> > >  .../drm/i915/display/skl_universal_plane.c    |  8 +++---
> > >  drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  2 +-
> > >  drivers/gpu/drm/i915/gt/intel_region_lmem.c   |  2 +-
> > >  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 28 +++++++++----
> > > ------
> > >  drivers/gpu/drm/i915/i915_drv.h               |  4 +--
> > >  drivers/gpu/drm/i915/intel_device_info.c      |  2 +-
> > >  drivers/gpu/drm/i915/intel_pm.c               |  8 +++---
> > >  10 files changed, 41 insertions(+), 41 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > index 71067a62264d..944fb13b9d98 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > @@ -2879,7 +2879,7 @@ void intel_init_cdclk_hooks(struct
> > > drm_i915_private *dev_priv)
> > >                 dev_priv->display.modeset_calc_cdclk =
> > > bxt_modeset_calc_cdclk;
> > >                 dev_priv->display.calc_voltage_level =
> > > tgl_calc_voltage_level;
> > >                 /* Wa_22011320316:adl-p[a0] */
> > > -               if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0,
> > > STEP_A0))
> > > +               if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0,
> > > STEP_B0))
> > >                         dev_priv->cdclk.table =
> > > adlp_a_step_cdclk_table;
> > >                 else
> > >                         dev_priv->cdclk.table = adlp_cdclk_table;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index e3aaf9678b07..bec380e58f40 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -5799,10 +5799,10 @@ static void tgl_bw_buddy_init(struct
> > > drm_i915_private *dev_priv)
> > >         int config, i;
> > >  
> > >         if (IS_ALDERLAKE_S(dev_priv) ||
> > > -           IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> > > -           IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> > > -           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > -               /* Wa_1409767108:tgl,rkl,dg1,adl-s */
> > > +           IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > +           IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > +           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > +               /* Wa_1409767108:tgl,dg1,adl-s */
> > >                 table = wa_1409767108_buddy_page_masks;
> > >         else
> > >                 table = tgl_buddy_page_masks;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 0a3d42c8d47d..f0381edefded 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -546,7 +546,7 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > >         val |= intel_psr2_get_tp_time(intel_dp);
> > >  
> > >         /* Wa_22012278275:adl-p */
> > > -       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
> > > +       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
> > >                 static const u8 map[] = {
> > >                         2, /* 5 lines */
> > >                         1, /* 6 lines */
> > > @@ -593,7 +593,7 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > >  
> > >         if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > >                 /* Wa_1408330847 */
> > > -               if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0,
> > > STEP_A0))
> > > +               if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0,
> > > STEP_B0))
> > >                         intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > >                                     
> > > DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > >                                     
> > > DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> > > @@ -733,7 +733,7 @@ tgl_dc3co_exitline_compute_config(struct
> > > intel_dp *intel_dp,
> > >                 return;
> > >  
> > >         /* Wa_16011303918:adl-p */
> > > -       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> > > +       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > >                 return;
> > >  
> > >         /*
> > > @@ -780,7 +780,7 @@ static bool
> > > intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > >         }
> > >  
> > >         /* Wa_14010254185 Wa_14010103792 */
> > > -       if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
> > > +       if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > >                 drm_dbg_kms(&dev_priv->drm,
> > >                             "PSR2 sel fetch not enabled, missing
> > > the implementation of WAs\n");
> > >                 return false;
> > > @@ -939,7 +939,7 @@ static bool intel_psr2_config_valid(struct
> > > intel_dp *intel_dp,
> > >  
> > >         /* Wa_2209313811 */
> > >         if (!crtc_state->enable_psr2_sel_fetch &&
> > > -           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
> > > +           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > >                 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is
> > > not supported this Display stepping\n");
> > >                 return false;
> > >         }
> > > @@ -966,7 +966,7 @@ static bool intel_psr2_config_valid(struct
> > > intel_dp *intel_dp,
> > >  
> > >         /* Wa_16011303918:adl-p */
> > >         if (crtc_state->vrr.enable &&
> > > -           IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) {
> > > +           IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> > >                 drm_dbg_kms(&dev_priv->drm,
> > >                             "PSR2 not enabled, not compatible
> > > with HW stepping + VRR\n");
> > >                 return false;
> > > @@ -1160,7 +1160,7 @@ static void intel_psr_enable_source(struct
> > > intel_dp *intel_dp)
> > >                              IGNORE_PSR2_HW_TRACKING : 0);
> > >  
> > >         /* Wa_16011168373:adl-p */
> > > -       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
> > > +       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
> > >             intel_dp->psr.psr2_enabled)
> > >                 intel_de_rmw(dev_priv,
> > >                              TRANS_SET_CONTEXT_LATENCY(intel_dp-
> > > >psr.transcoder),
> > > @@ -1340,12 +1340,12 @@ static void
> > > intel_psr_disable_locked(struct intel_dp *intel_dp)
> > >  
> > >         /* Wa_1408330847 */
> > >         if (intel_dp->psr.psr2_sel_fetch_enabled &&
> > > -           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> > > +           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > >                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > >                              DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> > >  
> > >         /* Wa_16011168373:adl-p */
> > > -       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
> > > +       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
> > >             intel_dp->psr.psr2_enabled)
> > >                 intel_de_rmw(dev_priv,
> > >                              TRANS_SET_CONTEXT_LATENCY(intel_dp-
> > > >psr.transcoder),
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 628b678d9a71..3ad04bf2a0fd 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -1910,11 +1910,11 @@ static bool
> > > gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
> > >  {
> > >         /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> > >         if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> > > -           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > +           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0))
> > >                 return false;
> > >  
> > >         /* Wa_22011186057 */
> > > -       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> > > +       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > >                 return false;
> > >  
> > >         return plane_id < PLANE_SPRITE4;
> > > @@ -1938,7 +1938,7 @@ static bool
> > > gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > >         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > >         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > >                 /* Wa_22011186057 */
> > > -               if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0,
> > > STEP_A0))
> > > +               if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0,
> > > STEP_B0))
> > >                         return false;
> > >                 break;
> > >         default:
> > > @@ -1995,7 +1995,7 @@ static const u64
> > > *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
> > >                                             enum plane_id
> > > plane_id)
> > >  {
> > >         /* Wa_22011186057 */
> > > -       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> > > +       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > >                 return adlp_step_a_plane_format_modifiers;
> > >         else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
> > >                 return gen12_plane_format_modifiers_mc_ccs;
> > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > index 87b06572fd2e..a69f5c438c72 100644
> > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > @@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request
> > > *rq, u32 mode)
> > >                         vf_flush_wa = true;
> > >  
> > >                 /* WaForGAMHang:kbl */
> > > -               if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_B0))
> > > +               if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_C0))
> > >                         dc_flush_wa = true;
> > >         }
> > >  
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> > > b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> > > index 50d11a84e7a9..e3a2a2fa5f94 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> > > @@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
> > >  static bool get_legacy_lowmem_region(struct intel_uncore
> > > *uncore,
> > >                                      u64 *start, u32 *size)
> > >  {
> > > -       if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
> > > +       if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_C0))
> > >                 return false;
> > >  
> > >         *start = 0;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 685c6115d380..247f0331ebee 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -838,7 +838,7 @@ skl_gt_workarounds_init(struct
> > > drm_i915_private *i915, struct i915_wa_list *wal)
> > >                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
> > >  
> > >         /* WaInPlaceDecompressionHang:skl */
> > > -       if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0 - 1))
> > > +       if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0))
> > >                 wa_write_or(wal,
> > >                             GEN9_GAMT_ECO_REG_RW_IA,
> > >                             GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> > > @@ -850,7 +850,7 @@ kbl_gt_workarounds_init(struct
> > > drm_i915_private *i915, struct i915_wa_list *wal)
> > >         gen9_gt_workarounds_init(i915, wal);
> > >  
> > >         /* WaDisableDynamicCreditSharing:kbl */
> > > -       if (IS_KBL_GT_STEP(i915, 0, STEP_B0))
> > > +       if (IS_KBL_GT_STEP(i915, 0, STEP_C0))
> > >                 wa_write_or(wal,
> > >                             GAMT_CHKN_BIT_REG,
> > >                            
> > > GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
> > > @@ -961,7 +961,7 @@ icl_gt_workarounds_init(struct
> > > drm_i915_private *i915, struct i915_wa_list *wal)
> > >  
> > >         /* Wa_1607087056:icl,ehl,jsl */
> > >         if (IS_ICELAKE(i915) ||
> > > -           IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
> > > +           IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_B0))
> > >                 wa_write_or(wal,
> > >                             SLICE_UNIT_LEVEL_CLKGATE,
> > >                             L3_CLKGATE_DIS |
> > > L3_CR2X_CLKGATE_DIS);
> > > @@ -1015,19 +1015,19 @@ tgl_gt_workarounds_init(struct
> > > drm_i915_private *i915, struct i915_wa_list *wal)
> > >         gen12_gt_workarounds_init(i915, wal);
> > >  
> > >         /* Wa_1409420604:tgl */
> > > -       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
> > > +       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
> > >                 wa_write_or(wal,
> > >                             SUBSLICE_UNIT_LEVEL_CLKGATE2,
> > >                             CPSSUNIT_CLKGATE_DIS);
> > >  
> > >         /* Wa_1607087056:tgl also know as BUG:1409180338 */
> > > -       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
> > > +       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
> > >                 wa_write_or(wal,
> > >                             SLICE_UNIT_LEVEL_CLKGATE,
> > >                             L3_CLKGATE_DIS |
> > > L3_CR2X_CLKGATE_DIS);
> > >  
> > >         /* Wa_1408615072:tgl[a0] */
> > > -       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
> > > +       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
> > >                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> > >                             VSUNIT_CLKGATE_DIS_TGL);
> > >  }
> > > @@ -1038,7 +1038,7 @@ dg1_gt_workarounds_init(struct
> > > drm_i915_private *i915, struct i915_wa_list *wal)
> > >         gen12_gt_workarounds_init(i915, wal);
> > >  
> > >         /* Wa_1607087056:dg1 */
> > > -       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
> > > +       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0))
> > >                 wa_write_or(wal,
> > >                             SLICE_UNIT_LEVEL_CLKGATE,
> > >                             L3_CLKGATE_DIS |
> > > L3_CR2X_CLKGATE_DIS);
> > > @@ -1436,7 +1436,7 @@ static void dg1_whitelist_build(struct
> > > intel_engine_cs *engine)
> > >         tgl_whitelist_build(engine);
> > >  
> > >         /* GEN:BUG:1409280441:dg1 */
> > > -       if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
> > > +       if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_B0) &&
> > >             (engine->class == RENDER_CLASS ||
> > >              engine->class == COPY_ENGINE_CLASS))
> > >                 whitelist_reg_ext(w, RING_ID(engine->mmio_base),
> > > @@ -1504,8 +1504,8 @@ rcs_engine_wa_init(struct intel_engine_cs
> > > *engine, struct i915_wa_list *wal)
> > >  {
> > >         struct drm_i915_private *i915 = engine->i915;
> > >  
> > > -       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
> > > -           IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
> > > +       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
> > > +           IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) {
> > >                 /*
> > >                  * Wa_1607138336:tgl[a0],dg1[a0]
> > >                  * Wa_1607063988:tgl[a0],dg1[a0]
> > > @@ -1515,7 +1515,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> > > *engine, struct i915_wa_list *wal)
> > >                             GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > >         }
> > >  
> > > -       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
> > > +       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) {
> > >                 /*
> > >                  * Wa_1606679103:tgl
> > >                  * (see also Wa_1606682166:icl)
> > > @@ -1550,7 +1550,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> > > *engine, struct i915_wa_list *wal)
> > >         }
> > >  
> > >         if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> > > -           IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
> > > +           IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
> > >             IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > >                 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> > >                 wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> > > @@ -1564,7 +1564,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> > > *engine, struct i915_wa_list *wal)
> > >         }
> > >  
> > >  
> > > -       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
> > > +       if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) ||
> > >             IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > >                 /*
> > >                  * Wa_1607030317:tgl
> > > @@ -1925,7 +1925,7 @@ xcs_engine_wa_init(struct intel_engine_cs
> > > *engine, struct i915_wa_list *wal)
> > >         struct drm_i915_private *i915 = engine->i915;
> > >  
> > >         /* WaKBLVECSSemaphoreWaitPoll:kbl */
> > > -       if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_E0)) {
> > > +       if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_F0)) {
> > >                 wa_write(wal,
> > >                          RING_SEMA_WAIT_POLL(engine->mmio_base),
> > >                          1);
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index da5f230e2d4b..b42405afb28e 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1332,11 +1332,11 @@ static inline struct drm_i915_private
> > > *pdev_to_i915(struct pci_dev *pdev)
> > >  
> > >  #define IS_DISPLAY_STEP(__i915, since, until) \
> > >         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915)
> > > == STEP_NONE), \
> > > -        INTEL_DISPLAY_STEP(__i915) >= (since) &&
> > > INTEL_DISPLAY_STEP(__i915) <= (until))
> > > +        INTEL_DISPLAY_STEP(__i915) >= (since) &&
> > > INTEL_DISPLAY_STEP(__i915) < (until))
> > >  
> > >  #define IS_GT_STEP(__i915, since, until) \
> > >         (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) ==
> > > STEP_NONE), \
> > > -        INTEL_GT_STEP(__i915) >= (since) &&
> > > INTEL_GT_STEP(__i915) <= (until))
> > > +        INTEL_GT_STEP(__i915) >= (since) &&
> > > INTEL_GT_STEP(__i915) < (until))
> > 
> > Would be nice to have some comment about bound in here.
> > 
> > Did not manually checked each workaround against bspec, only
> > checked the old and new until values and it makes sense.
> > With the comment requested above:
> > 
> > Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> > 
> > 
> > >  
> > >  static __always_inline unsigned int
> > >  __platform_mask_index(const struct intel_runtime_info *info,
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index dd63dd2c45ad..5c83b2ec69da 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -262,7 +262,7 @@ void intel_device_info_runtime_init(struct
> > > drm_i915_private *dev_priv)
> > >         enum pipe pipe;
> > >  
> > >         /* Wa_14011765242: adl-s A0,A1 */
> > > -       if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A1))
> > > +       if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
> > >                 for_each_pipe(dev_priv, pipe)
> > >                         runtime->num_scalers[pipe] = 0;
> > >         else if (GRAPHICS_VER(dev_priv) >= 10) {
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 8a84abfaa4b0..597383430ca6 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -7359,7 +7359,7 @@ static void
> > > gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
> > >                                   
> > > ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> > >  
> > >         /* Wa_1409825376:tgl (pre-prod)*/
> > > -       if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1))
> > > +       if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > >                 intel_uncore_write(&dev_priv->uncore,
> > > GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore,
> > > GEN9_CLKGATE_DIS_3) |
> > >                            TGL_VRH_GATING_DIS);
> > >  
> > > @@ -7382,7 +7382,7 @@ static void dg1_init_clock_gating(struct
> > > drm_i915_private *dev_priv)
> > >         gen12lp_init_clock_gating(dev_priv);
> > >  
> > >         /* Wa_1409836686:dg1[a0] */
> > > -       if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0))
> > > +       if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_B0))
> > >                 intel_uncore_write(&dev_priv->uncore,
> > > GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore,
> > > GEN9_CLKGATE_DIS_3) |
> > >                            DPT_GATING_DIS);
> > >  }
> > > @@ -7467,12 +7467,12 @@ static void kbl_init_clock_gating(struct
> > > drm_i915_private *dev_priv)
> > >                    FBC_LLC_FULLY_OPEN);
> > >  
> > >         /* WaDisableSDEUnitClockGating:kbl */
> > > -       if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
> > > +       if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
> > >                 intel_uncore_write(&dev_priv->uncore,
> > > GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6)
> > > |
> > >                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> > >  
> > >         /* WaDisableGamClockGating:kbl */
> > > -       if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
> > > +       if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
> > >                 intel_uncore_write(&dev_priv->uncore,
> > > GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1)
> > > |
> > >                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> > >  
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

[Intel-gfx] ✗ Fi.CI.DOCS: warning for More workaround updates

[Patchwork]

== Series Details ==

Series: More workaround updates
URL   : https://patchwork.freedesktop.org/series/92669/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'jump_whitelist' description in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'shadow_map' description in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'batch_map' description in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Function parameter or member 'trampoline' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'jump_whitelist' description in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'shadow_map' description in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'batch_map' description in 'intel_engine_cmd_parser'


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[Intel-gfx] ✓ Fi.CI.BAT: success for More workaround updates

[Patchwork]

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== Series Details ==

Series: More workaround updates
URL   : https://patchwork.freedesktop.org/series/92669/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10346 -> Patchwork_20640
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/index.html

Known issues
------------

  Here are the changes found in Patchwork_20640 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html

  * igt@core_hotunplug@unbind-rebind:
    - fi-bdw-5557u:       NOTRUN -> [WARN][2] ([i915#3718])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718


Participating hosts (41 -> 35)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus fi-tgl-y bat-jsl-1 


Build changes
-------------

  * Linux: CI_DRM_10346 -> Patchwork_20640

  CI-20190529: 20190529
  CI_DRM_10346: 6c4e3c031a995e641cc0d9563d21043415fb8d12 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6144: bc65ee9ee6593716306448c9fb82c77f284f2148 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20640: fae76d62ac8ff6dc3d11546abd41305f544c8024 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

fae76d62ac8f drm/i915: Make workaround upper bounds exclusive
5d962f65530f drm/i915/rkl: Wa_1408330847 no longer applies to RKL
a04accd6c6dc drm/i915/rkl: Wa_1409767108 also applies to RKL
00c4dd9a43c2 drm/i915/adl_s: Wa_14011765242 is also needed on A1 display stepping
2f52e703776a drm/i915: Program DFR enable/disable as a GT workaround
a83a0ab9a15c drm/i915/icl: Drop a couple unnecessary workarounds
b4df960619ce drm/i915: Fix application of WaInPlaceDecompressionHang

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/index.html

[-- Attachment #1.2: Type: text/html, Size: 3361 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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[Intel-gfx] ✗ Fi.CI.IGT: failure for More workaround updates

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 30246 bytes --]

== Series Details ==

Series: More workaround updates
URL   : https://patchwork.freedesktop.org/series/92669/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10346_full -> Patchwork_20640_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20640_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20640_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20640_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_eio@kms:
    - shard-skl:          [PASS][1] -> [TIMEOUT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl6/igt@gem_eio@kms.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl5/igt@gem_eio@kms.html

  * igt@gem_request_retire@retire-vma-not-inactive:
    - shard-iclb:         [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb6/igt@gem_request_retire@retire-vma-not-inactive.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb5/igt@gem_request_retire@retire-vma-not-inactive.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-iclb:         NOTRUN -> [SKIP][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@gen9_exec_parse@bb-start-far.html

  
Known issues
------------

  Here are the changes found in Patchwork_20640_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
    - shard-apl:          NOTRUN -> [DMESG-WARN][6] ([i915#180])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vecs0.html

  * igt@gem_ctx_persistence@engines-hostile-preempt:
    - shard-snb:          NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-snb2/igt@gem_ctx_persistence@engines-hostile-preempt.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [PASS][8] -> [FAIL][9] ([i915#2410])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
    - shard-tglb:         NOTRUN -> [FAIL][12] ([i915#2842]) +4 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglb:         [PASS][13] -> [FAIL][14] ([i915#2842]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-sync@rcs0:
    - shard-kbl:          [PASS][15] -> [SKIP][16] ([fdo#109271]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl2/igt@gem_exec_fair@basic-sync@rcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl6/igt@gem_exec_fair@basic-sync@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-snb:          NOTRUN -> [SKIP][17] ([fdo#109271]) +143 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-snb2/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_exec_whisper@basic-forked-all:
    - shard-glk:          [PASS][18] -> [DMESG-WARN][19] ([i915#118] / [i915#95])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-glk4/igt@gem_exec_whisper@basic-forked-all.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-glk3/igt@gem_exec_whisper@basic-forked-all.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2190])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl3/igt@gem_huc_copy@huc-copy.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([i915#644])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-glk6/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          NOTRUN -> [WARN][23] ([i915#2658]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-snb:          NOTRUN -> [WARN][24] ([i915#2658]) +1 similar issue
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-snb2/igt@gem_pwrite@basic-exhaustion.html
    - shard-kbl:          NOTRUN -> [WARN][25] ([i915#2658])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
    - shard-iclb:         NOTRUN -> [SKIP][26] ([i915#768])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html

  * igt@gen7_exec_parse@chained-batch:
    - shard-iclb:         NOTRUN -> [SKIP][27] ([fdo#109289]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@gen7_exec_parse@chained-batch.html

  * igt@i915_pm_lpsp@kms-lpsp:
    - shard-skl:          NOTRUN -> [SKIP][28] ([fdo#109271]) +109 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@i915_pm_lpsp@kms-lpsp.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - shard-iclb:         NOTRUN -> [SKIP][29] ([fdo#110892])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-skl:          [PASS][30] -> [FAIL][31] ([i915#2521])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][32] ([i915#3722])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-skl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3777])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#110723]) +1 similar issue
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [FAIL][37] ([i915#3678])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][38] ([i915#3689]) +5 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html

  * igt@kms_chamelium@dp-hpd-fast:
    - shard-snb:          NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-snb2/igt@kms_chamelium@dp-hpd-fast.html

  * igt@kms_chamelium@dp-hpd-storm-disable:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_chamelium@dp-hpd-storm-disable.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +18 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-aspect-ratio:
    - shard-kbl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@kms_chamelium@hdmi-aspect-ratio.html

  * igt@kms_chamelium@vga-edid-read:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_color@pipe-c-ctm-max:
    - shard-skl:          [PASS][44] -> [DMESG-WARN][45] ([i915#1982]) +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl7/igt@kms_color@pipe-c-ctm-max.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl4/igt@kms_color@pipe-c-ctm-max.html

  * igt@kms_color@pipe-d-ctm-negative:
    - shard-iclb:         NOTRUN -> [SKIP][46] ([fdo#109278] / [i915#1149])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_color@pipe-d-ctm-negative.html

  * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
    - shard-skl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([i915#3319]) +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement:
    - shard-glk:          NOTRUN -> [SKIP][49] ([fdo#109271]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-glk3/igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([fdo#109279] / [i915#3359]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-dpms:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([fdo#109278]) +11 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_cursor_crc@pipe-d-cursor-dpms.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-iclb:         NOTRUN -> [SKIP][52] ([fdo#109274] / [fdo#109278])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_dp_tiled_display@basic-test-pattern:
    - shard-tglb:         NOTRUN -> [SKIP][53] ([i915#426])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_dp_tiled_display@basic-test-pattern.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [PASS][54] -> [INCOMPLETE][55] ([i915#180])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [PASS][56] -> [FAIL][57] ([i915#79]) +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][58] -> [DMESG-WARN][59] ([i915#180]) +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate@c-edp1:
    - shard-skl:          NOTRUN -> [FAIL][60] ([i915#2122]) +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
    - shard-apl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2672])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
    - shard-kbl:          NOTRUN -> [SKIP][62] ([fdo#109271]) +27 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-iclb:         NOTRUN -> [SKIP][63] ([fdo#109280]) +3 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt:
    - shard-tglb:         NOTRUN -> [SKIP][64] ([fdo#111825]) +4 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-skl:          [PASS][66] -> [INCOMPLETE][67] ([i915#198] / [i915#2828])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#533]) +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-apl:          NOTRUN -> [FAIL][69] ([fdo#108145] / [i915#265])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][71] ([i915#265]) +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][72] -> [FAIL][73] ([fdo#108145] / [i915#265])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_lowres@pipe-c-tiling-none:
    - shard-tglb:         NOTRUN -> [SKIP][74] ([i915#3536])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_plane_lowres@pipe-c-tiling-none.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2733])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl6/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
    - shard-apl:          NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658]) +4 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
    - shard-skl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
    - shard-kbl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [PASS][79] -> [SKIP][80] ([fdo#109441])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb2/igt@kms_psr@psr2_basic.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_psr@psr2_basic.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-iclb:         NOTRUN -> [SKIP][81] ([fdo#109441])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-tglb:         NOTRUN -> [FAIL][82] ([i915#132] / [i915#3467])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_vrr@flip-basic:
    - shard-iclb:         NOTRUN -> [SKIP][83] ([fdo#109502])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_vrr@flip-basic.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2437]) +1 similar issue
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-tglb:         NOTRUN -> [SKIP][85] ([i915#2437])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@nouveau_crc@pipe-b-source-rg:
    - shard-iclb:         NOTRUN -> [SKIP][86] ([i915#2530])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@nouveau_crc@pipe-b-source-rg.html

  * igt@nouveau_crc@pipe-d-source-outp-inactive:
    - shard-tglb:         NOTRUN -> [SKIP][87] ([i915#2530])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@nouveau_crc@pipe-d-source-outp-inactive.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][88] -> [FAIL][89] ([i915#1542])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl7/igt@perf@blocking.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl3/igt@perf@blocking.html

  * igt@perf@polling-parameterized:
    - shard-iclb:         [PASS][90] -> [FAIL][91] ([i915#1542])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb7/igt@perf@polling-parameterized.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb6/igt@perf@polling-parameterized.html

  * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
    - shard-apl:          NOTRUN -> [SKIP][92] ([fdo#109271]) +186 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html

  * igt@prime_nv_test@i915_import_gtt_mmap:
    - shard-tglb:         NOTRUN -> [SKIP][93] ([fdo#109291]) +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb3/igt@prime_nv_test@i915_import_gtt_mmap.html

  * igt@sysfs_clients@pidname:
    - shard-skl:          NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#2994])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@sysfs_clients@pidname.html

  * igt@sysfs_clients@recycle-many:
    - shard-apl:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2994])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@sysfs_clients@recycle-many.html

  
#### Possible fixes ####

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [TIMEOUT][96] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-tglb6/igt@gem_eio@unwedge-stress.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          [FAIL][98] ([i915#2842]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-glk8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [FAIL][100] ([i915#2842]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
    - shard-kbl:          [FAIL][102] ([i915#2842]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@gem_exec_fair@basic-none@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-tglb:         [FAIL][104] ([i915#2842]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-tglb1/igt@gem_exec_fair@basic-pace@vcs1.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb5/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][106] ([i915#2849]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_mmap_gtt@cpuset-big-copy:
    - shard-iclb:         [FAIL][108] ([i915#307]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][110] ([i915#180]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-skl:          [INCOMPLETE][112] ([i915#300]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][114] ([i915#2346] / [i915#533]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-panning-interruptible@d-edp1:
    - shard-tglb:         [INCOMPLETE][116] -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-tglb6/igt@kms_flip@flip-vs-panning-interruptible@d-edp1.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_flip@flip-vs-panning-interruptible@d-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
    - shard-skl:          [INCOMPLETE][118] ([i915#198] / [i915#2910]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-iclb:         [INCOMPLETE][120] ([i915#1185]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][122] ([fdo#108145] / [i915#265]) -> [PASS][123] +1 similar issue
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@perf@polling-small-buf:
    - shard-skl:          [FAIL][124] ([i915#1722]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl2/igt@perf@polling-small-buf.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@perf@polling-small-buf.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         [FAIL][126] ([i915#2842]) -> [FAIL][127] ([i915#2852])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-iclb:         [SKIP][128] ([i915#2920]) -> [SKIP][129] ([i915#658])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][130], [FAIL][131], [FAIL][132]) ([i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][133], [FAIL][134]) ([i915#3002] / [i915#3363])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl4/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl3/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl3/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl3/igt@runner@aborted.html
    - shard-iclb:         ([FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#1814] / [i915#3002]) -> ([FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143]) ([i915#1814] / [i915#2426] / [i915#3002] / [i915#3690])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb7/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb2/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb2/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb1/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb6/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb6/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for More workaround updates

[Matt Roper]

On Sat, Jul 17, 2021 at 04:46:32PM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: More workaround updates
> URL   : https://patchwork.freedesktop.org/series/92669/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_10346_full -> Patchwork_20640_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_20640_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_20640_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_20640_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@gem_eio@kms:
>     - shard-skl:          [PASS][1] -> [TIMEOUT][2]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl6/igt@gem_eio@kms.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl5/igt@gem_eio@kms.html
> 

https://gitlab.freedesktop.org/drm/intel/-/issues/3649

>   * igt@gem_request_retire@retire-vma-not-inactive:
>     - shard-iclb:         [PASS][3] -> [INCOMPLETE][4]
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb6/igt@gem_request_retire@retire-vma-not-inactive.html
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb5/igt@gem_request_retire@retire-vma-not-inactive.html

https://gitlab.freedesktop.org/drm/intel/-/issues/3697

> 
>   * igt@gen9_exec_parse@bb-start-far:
>     - shard-iclb:         NOTRUN -> [SKIP][5]
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@gen9_exec_parse@bb-start-far.html
> 

Change to cmdparser version reporting wouldn't be caused by this series.
Appears to be triggered by the cmdparser changes in this series:

        https://patchwork.freedesktop.org/series/90891/



First three patches applied to gt-next, next three to intel-next.  The
final patch was split into separate GT and display halves and applied
through the corresponding trees.


Matt

>   
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_20640_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_ctx_isolation@preservation-s3@vecs0:
>     - shard-apl:          NOTRUN -> [DMESG-WARN][6] ([i915#180])
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vecs0.html
> 
>   * igt@gem_ctx_persistence@engines-hostile-preempt:
>     - shard-snb:          NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099])
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-snb2/igt@gem_ctx_persistence@engines-hostile-preempt.html
> 
>   * igt@gem_ctx_persistence@many-contexts:
>     - shard-tglb:         [PASS][8] -> [FAIL][9] ([i915#2410])
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
> 
>   * igt@gem_exec_fair@basic-none@vcs0:
>     - shard-kbl:          [PASS][10] -> [FAIL][11] ([i915#2842])
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
>     - shard-tglb:         NOTRUN -> [FAIL][12] ([i915#2842]) +4 similar issues
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@gem_exec_fair@basic-none@vcs0.html
> 
>   * igt@gem_exec_fair@basic-pace-solo@rcs0:
>     - shard-tglb:         [PASS][13] -> [FAIL][14] ([i915#2842]) +2 similar issues
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> 
>   * igt@gem_exec_fair@basic-sync@rcs0:
>     - shard-kbl:          [PASS][15] -> [SKIP][16] ([fdo#109271]) +2 similar issues
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl2/igt@gem_exec_fair@basic-sync@rcs0.html
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl6/igt@gem_exec_fair@basic-sync@rcs0.html
> 
>   * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
>     - shard-snb:          NOTRUN -> [SKIP][17] ([fdo#109271]) +143 similar issues
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-snb2/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
> 
>   * igt@gem_exec_whisper@basic-forked-all:
>     - shard-glk:          [PASS][18] -> [DMESG-WARN][19] ([i915#118] / [i915#95])
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-glk4/igt@gem_exec_whisper@basic-forked-all.html
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-glk3/igt@gem_exec_whisper@basic-forked-all.html
> 
>   * igt@gem_huc_copy@huc-copy:
>     - shard-apl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2190])
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl3/igt@gem_huc_copy@huc-copy.html
> 
>   * igt@gem_ppgtt@flink-and-close-vma-leak:
>     - shard-glk:          [PASS][21] -> [FAIL][22] ([i915#644])
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-glk6/igt@gem_ppgtt@flink-and-close-vma-leak.html
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
> 
>   * igt@gem_pread@exhaustion:
>     - shard-apl:          NOTRUN -> [WARN][23] ([i915#2658]) +1 similar issue
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@gem_pread@exhaustion.html
> 
>   * igt@gem_pwrite@basic-exhaustion:
>     - shard-snb:          NOTRUN -> [WARN][24] ([i915#2658]) +1 similar issue
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-snb2/igt@gem_pwrite@basic-exhaustion.html
>     - shard-kbl:          NOTRUN -> [WARN][25] ([i915#2658])
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@gem_pwrite@basic-exhaustion.html
> 
>   * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
>     - shard-iclb:         NOTRUN -> [SKIP][26] ([i915#768])
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html
> 
>   * igt@gen7_exec_parse@chained-batch:
>     - shard-iclb:         NOTRUN -> [SKIP][27] ([fdo#109289]) +1 similar issue
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@gen7_exec_parse@chained-batch.html
> 
>   * igt@i915_pm_lpsp@kms-lpsp:
>     - shard-skl:          NOTRUN -> [SKIP][28] ([fdo#109271]) +109 similar issues
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@i915_pm_lpsp@kms-lpsp.html
> 
>   * igt@i915_pm_rpm@modeset-non-lpsp-stress:
>     - shard-iclb:         NOTRUN -> [SKIP][29] ([fdo#110892])
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
> 
>   * igt@kms_async_flips@alternate-sync-async-flip:
>     - shard-skl:          [PASS][30] -> [FAIL][31] ([i915#2521])
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
> 
>   * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
>     - shard-skl:          NOTRUN -> [FAIL][32] ([i915#3722])
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
> 
>   * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
>     - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) +1 similar issue
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
> 
>   * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
>     - shard-skl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3777])
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
> 
>   * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
>     - shard-kbl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777])
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
> 
>   * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
>     - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#110723]) +1 similar issue
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
> 
>   * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
>     - shard-skl:          NOTRUN -> [FAIL][37] ([i915#3678])
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
> 
>   * igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:
>     - shard-tglb:         NOTRUN -> [SKIP][38] ([i915#3689]) +5 similar issues
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html
> 
>   * igt@kms_chamelium@dp-hpd-fast:
>     - shard-snb:          NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +8 similar issues
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-snb2/igt@kms_chamelium@dp-hpd-fast.html
> 
>   * igt@kms_chamelium@dp-hpd-storm-disable:
>     - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +1 similar issue
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_chamelium@dp-hpd-storm-disable.html
> 
>   * igt@kms_chamelium@dp-mode-timings:
>     - shard-apl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +18 similar issues
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_chamelium@dp-mode-timings.html
> 
>   * igt@kms_chamelium@hdmi-aspect-ratio:
>     - shard-kbl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +1 similar issue
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@kms_chamelium@hdmi-aspect-ratio.html
> 
>   * igt@kms_chamelium@vga-edid-read:
>     - shard-iclb:         NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827]) +1 similar issue
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_chamelium@vga-edid-read.html
> 
>   * igt@kms_color@pipe-c-ctm-max:
>     - shard-skl:          [PASS][44] -> [DMESG-WARN][45] ([i915#1982]) +1 similar issue
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl7/igt@kms_color@pipe-c-ctm-max.html
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl4/igt@kms_color@pipe-c-ctm-max.html
> 
>   * igt@kms_color@pipe-d-ctm-negative:
>     - shard-iclb:         NOTRUN -> [SKIP][46] ([fdo#109278] / [i915#1149])
>    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_color@pipe-d-ctm-negative.html
> 
>   * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
>     - shard-skl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +11 similar issues
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
>     - shard-tglb:         NOTRUN -> [SKIP][48] ([i915#3319]) +2 similar issues
>    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement:
>     - shard-glk:          NOTRUN -> [SKIP][49] ([fdo#109271]) +1 similar issue
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-glk3/igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement.html
> 
>   * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
>     - shard-tglb:         NOTRUN -> [SKIP][50] ([fdo#109279] / [i915#3359]) +1 similar issue
>    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html
> 
>   * igt@kms_cursor_crc@pipe-d-cursor-dpms:
>     - shard-iclb:         NOTRUN -> [SKIP][51] ([fdo#109278]) +11 similar issues
>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_cursor_crc@pipe-d-cursor-dpms.html
> 
>   * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
>     - shard-iclb:         NOTRUN -> [SKIP][52] ([fdo#109274] / [fdo#109278])
>    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
> 
>   * igt@kms_dp_tiled_display@basic-test-pattern:
>     - shard-tglb:         NOTRUN -> [SKIP][53] ([i915#426])
>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_dp_tiled_display@basic-test-pattern.html
> 
>   * igt@kms_fbcon_fbt@fbc-suspend:
>     - shard-apl:          [PASS][54] -> [INCOMPLETE][55] ([i915#180])
>    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
>     - shard-skl:          [PASS][56] -> [FAIL][57] ([i915#79]) +1 similar issue
>    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
>    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
> 
>   * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
>     - shard-apl:          [PASS][58] -> [DMESG-WARN][59] ([i915#180]) +2 similar issues
>    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
>    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
> 
>   * igt@kms_flip@plain-flip-fb-recreate@c-edp1:
>     - shard-skl:          NOTRUN -> [FAIL][60] ([i915#2122]) +1 similar issue
>    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
> 
>   * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
>     - shard-apl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2672])
>    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
>     - shard-kbl:          NOTRUN -> [SKIP][62] ([fdo#109271]) +27 similar issues
>    [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
>     - shard-iclb:         NOTRUN -> [SKIP][63] ([fdo#109280]) +3 similar issues
>    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt:
>     - shard-tglb:         NOTRUN -> [SKIP][64] ([fdo#111825]) +4 similar issues
>    [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html
> 
>   * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
>     - shard-apl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533])
>    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
> 
>   * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
>     - shard-skl:          [PASS][66] -> [INCOMPLETE][67] ([i915#198] / [i915#2828])
>    [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
>    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
> 
>   * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
>     - shard-skl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#533]) +1 similar issue
>    [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
> 
>   * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
>     - shard-apl:          NOTRUN -> [FAIL][69] ([fdo#108145] / [i915#265])
>    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
> 
>   * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
>     - shard-skl:          NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) +1 similar issue
>    [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
> 
>   * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
>     - shard-apl:          NOTRUN -> [FAIL][71] ([i915#265]) +1 similar issue
>    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
> 
>   * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
>     - shard-skl:          [PASS][72] -> [FAIL][73] ([fdo#108145] / [i915#265])
>    [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
>    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
> 
>   * igt@kms_plane_lowres@pipe-c-tiling-none:
>     - shard-tglb:         NOTRUN -> [SKIP][74] ([i915#3536])
>    [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_plane_lowres@pipe-c-tiling-none.html
> 
>   * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
>     - shard-apl:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2733])
>    [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl6/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
> 
>   * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
>     - shard-apl:          NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658]) +4 similar issues
>    [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
> 
>   * igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
>     - shard-skl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) +1 similar issue
>    [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
> 
>   * igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
>     - shard-kbl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658])
>    [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
> 
>   * igt@kms_psr@psr2_basic:
>     - shard-iclb:         [PASS][79] -> [SKIP][80] ([fdo#109441])
>    [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb2/igt@kms_psr@psr2_basic.html
>    [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_psr@psr2_basic.html
> 
>   * igt@kms_psr@psr2_cursor_mmap_gtt:
>     - shard-iclb:         NOTRUN -> [SKIP][81] ([fdo#109441])
>    [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_gtt.html
> 
>   * igt@kms_psr@psr2_primary_page_flip:
>     - shard-tglb:         NOTRUN -> [FAIL][82] ([i915#132] / [i915#3467])
>    [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_psr@psr2_primary_page_flip.html
> 
>   * igt@kms_vrr@flip-basic:
>     - shard-iclb:         NOTRUN -> [SKIP][83] ([fdo#109502])
>    [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_vrr@flip-basic.html
> 
>   * igt@kms_writeback@writeback-check-output:
>     - shard-apl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2437]) +1 similar issue
>    [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@kms_writeback@writeback-check-output.html
> 
>   * igt@kms_writeback@writeback-invalid-parameters:
>     - shard-tglb:         NOTRUN -> [SKIP][85] ([i915#2437])
>    [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_writeback@writeback-invalid-parameters.html
> 
>   * igt@nouveau_crc@pipe-b-source-rg:
>     - shard-iclb:         NOTRUN -> [SKIP][86] ([i915#2530])
>    [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@nouveau_crc@pipe-b-source-rg.html
> 
>   * igt@nouveau_crc@pipe-d-source-outp-inactive:
>     - shard-tglb:         NOTRUN -> [SKIP][87] ([i915#2530])
>    [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@nouveau_crc@pipe-d-source-outp-inactive.html
> 
>   * igt@perf@blocking:
>     - shard-skl:          [PASS][88] -> [FAIL][89] ([i915#1542])
>    [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl7/igt@perf@blocking.html
>    [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl3/igt@perf@blocking.html
> 
>   * igt@perf@polling-parameterized:
>     - shard-iclb:         [PASS][90] -> [FAIL][91] ([i915#1542])
>    [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb7/igt@perf@polling-parameterized.html
>    [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb6/igt@perf@polling-parameterized.html
> 
>   * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
>     - shard-apl:          NOTRUN -> [SKIP][92] ([fdo#109271]) +186 similar issues
>    [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
> 
>   * igt@prime_nv_test@i915_import_gtt_mmap:
>     - shard-tglb:         NOTRUN -> [SKIP][93] ([fdo#109291]) +1 similar issue
>    [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb3/igt@prime_nv_test@i915_import_gtt_mmap.html
> 
>   * igt@sysfs_clients@pidname:
>     - shard-skl:          NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#2994])
>    [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@sysfs_clients@pidname.html
> 
>   * igt@sysfs_clients@recycle-many:
>     - shard-apl:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2994])
>    [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-apl8/igt@sysfs_clients@recycle-many.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_eio@unwedge-stress:
>     - shard-tglb:         [TIMEOUT][96] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][97]
>    [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-tglb6/igt@gem_eio@unwedge-stress.html
>    [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb2/igt@gem_eio@unwedge-stress.html
> 
>   * igt@gem_exec_fair@basic-none-rrul@rcs0:
>     - shard-glk:          [FAIL][98] ([i915#2842]) -> [PASS][99]
>    [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-glk8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>    [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
> 
>   * igt@gem_exec_fair@basic-none-share@rcs0:
>     - shard-iclb:         [FAIL][100] ([i915#2842]) -> [PASS][101]
>    [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
>    [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
> 
>   * igt@gem_exec_fair@basic-none@rcs0:
>     - shard-kbl:          [FAIL][102] ([i915#2842]) -> [PASS][103]
>    [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html
>    [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@gem_exec_fair@basic-none@rcs0.html
> 
>   * igt@gem_exec_fair@basic-pace@vcs1:
>     - shard-tglb:         [FAIL][104] ([i915#2842]) -> [PASS][105]
>    [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-tglb1/igt@gem_exec_fair@basic-pace@vcs1.html
>    [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb5/igt@gem_exec_fair@basic-pace@vcs1.html
> 
>   * igt@gem_exec_fair@basic-throttle@rcs0:
>     - shard-iclb:         [FAIL][106] ([i915#2849]) -> [PASS][107]
>    [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
>    [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
> 
>   * igt@gem_mmap_gtt@cpuset-big-copy:
>     - shard-iclb:         [FAIL][108] ([i915#307]) -> [PASS][109]
>    [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy.html
>    [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy.html
> 
>   * igt@kms_cursor_crc@pipe-b-cursor-suspend:
>     - shard-kbl:          [DMESG-WARN][110] ([i915#180]) -> [PASS][111]
>    [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
>    [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-suspend:
>     - shard-skl:          [INCOMPLETE][112] ([i915#300]) -> [PASS][113]
>    [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>    [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> 
>   * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
>     - shard-skl:          [FAIL][114] ([i915#2346] / [i915#533]) -> [PASS][115]
>    [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
>    [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
> 
>   * igt@kms_flip@flip-vs-panning-interruptible@d-edp1:
>     - shard-tglb:         [INCOMPLETE][116] -> [PASS][117]
>    [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-tglb6/igt@kms_flip@flip-vs-panning-interruptible@d-edp1.html
>    [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-tglb1/igt@kms_flip@flip-vs-panning-interruptible@d-edp1.html
> 
>   * igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
>     - shard-skl:          [INCOMPLETE][118] ([i915#198] / [i915#2910]) -> [PASS][119]
>    [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
>    [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
> 
>   * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
>     - shard-iclb:         [INCOMPLETE][120] ([i915#1185]) -> [PASS][121]
>    [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
>    [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
> 
>   * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>     - shard-skl:          [FAIL][122] ([fdo#108145] / [i915#265]) -> [PASS][123] +1 similar issue
>    [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>    [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> 
>   * igt@perf@polling-small-buf:
>     - shard-skl:          [FAIL][124] ([i915#1722]) -> [PASS][125]
>    [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-skl2/igt@perf@polling-small-buf.html
>    [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-skl10/igt@perf@polling-small-buf.html
> 
>   
> #### Warnings ####
> 
>   * igt@gem_exec_fair@basic-none-rrul@rcs0:
>     - shard-iclb:         [FAIL][126] ([i915#2842]) -> [FAIL][127] ([i915#2852])
>    [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>    [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
> 
>   * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
>     - shard-iclb:         [SKIP][128] ([i915#2920]) -> [SKIP][129] ([i915#658])
>    [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
>    [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
> 
>   * igt@runner@aborted:
>     - shard-kbl:          ([FAIL][130], [FAIL][131], [FAIL][132]) ([i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][133], [FAIL][134]) ([i915#3002] / [i915#3363])
>    [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl4/igt@runner@aborted.html
>    [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl3/igt@runner@aborted.html
>    [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-kbl3/igt@runner@aborted.html
>    [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl7/igt@runner@aborted.html
>    [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-kbl3/igt@runner@aborted.html
>     - shard-iclb:         ([FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#1814] / [i915#3002]) -> ([FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143]) ([i915#1814] / [i915#2426] / [i915#3002] / [i915#3690])
>    [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb7/igt@runner@aborted.html
>    [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb2/igt@runner@aborted.html
>    [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb2/igt@runner@aborted.html
>    [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10346/shard-iclb1/igt@runner@aborted.html
>    [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb6/igt@runner@aborted.html
>    [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/shard-iclb6/igt@runner@aborted.html
>    [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20640/index.html

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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